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tsunami_io.cc
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1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * Authors: Ali Saidi
29  * Andrew Schultz
30  * Miguel Serrano
31  */
32 
37 #include "dev/alpha/tsunami_io.hh"
38 
39 #include <sys/time.h>
40 
41 #include <deque>
42 #include <string>
43 #include <vector>
44 
45 #include "base/time.hh"
46 #include "base/trace.hh"
47 #include "debug/Tsunami.hh"
48 #include "dev/alpha/tsunami.hh"
50 #include "dev/alpha/tsunamireg.h"
51 #include "dev/rtcreg.h"
52 #include "mem/packet.hh"
53 #include "mem/packet_access.hh"
54 #include "mem/port.hh"
55 #include "sim/system.hh"
56 
57 // clang complains about std::set being overloaded with Packet::set if
58 // we open up the entire namespace std
59 using std::string;
60 using std::ostream;
61 
62 TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p)
63  : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency),
64  tsunami(p->tsunami)
65 {
66 }
67 
69  : BasicPioDevice(p, 0x100), tsunami(p->tsunami),
70  pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p)
71 {
72  // set the back pointer from tsunami to myself
73  tsunami->io = this;
74 
75  timerData = 0;
76  picr = 0;
77  picInterrupting = false;
78 }
79 
80 Tick
82 {
83  return SimClock::Frequency / params()->frequency;
84 }
85 
86 Tick
88 {
89  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
90 
91  Addr daddr = pkt->getAddr() - pioAddr;
92 
93  DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
94  pkt->getSize(), daddr);
95 
96  if (pkt->getSize() == sizeof(uint8_t)) {
97  switch(daddr) {
98  // PIC1 mask read
99  case TSDEV_PIC1_MASK:
100  pkt->setLE(~mask1);
101  break;
102  case TSDEV_PIC2_MASK:
103  pkt->setLE(~mask2);
104  break;
105  case TSDEV_PIC1_ISR:
106  // !!! If this is modified 64bit case needs to be too
107  // Pal code has to do a 64 bit physical read because there is
108  // no load physical byte instruction
109  pkt->setLE(picr);
110  break;
111  case TSDEV_PIC2_ISR:
112  // PIC2 not implemnted... just return 0
113  pkt->setLE(0x00);
114  break;
115  case TSDEV_TMR0_DATA:
116  pkt->setLE(pitimer.readCounter(0));
117  break;
118  case TSDEV_TMR1_DATA:
119  pkt->setLE(pitimer.readCounter(1));
120  break;
121  case TSDEV_TMR2_DATA:
122  pkt->setLE(pitimer.readCounter(2));
123  break;
124  case TSDEV_RTC_DATA:
125  pkt->setLE(rtc.readData(rtcAddr));
126  break;
127  case TSDEV_CTRL_PORTB:
128  if (pitimer.outputHigh(2))
129  pkt->setLE(PORTB_SPKR_HIGH);
130  else
131  pkt->setLE(0x00);
132  break;
133  default:
134  panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
135  }
136  } else if (pkt->getSize() == sizeof(uint64_t)) {
137  if (daddr == TSDEV_PIC1_ISR)
138  pkt->setLE<uint64_t>(picr);
139  else
140  panic("I/O Read - invalid addr - va %#x size %d\n",
141  pkt->getAddr(), pkt->getSize());
142  } else {
143  panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
144  }
145  pkt->makeAtomicResponse();
146  return pioDelay;
147 }
148 
149 Tick
151 {
152  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
153  Addr daddr = pkt->getAddr() - pioAddr;
154 
155  DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
156  pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff,
157  (uint32_t)pkt->getLE<uint8_t>());
158 
159  assert(pkt->getSize() == sizeof(uint8_t));
160 
161  switch(daddr) {
162  case TSDEV_PIC1_MASK:
163  mask1 = ~(pkt->getLE<uint8_t>());
164  if ((picr & mask1) && !picInterrupting) {
165  picInterrupting = true;
166  tsunami->cchip->postDRIR(55);
167  DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
168  }
169  if ((!(picr & mask1)) && picInterrupting) {
170  picInterrupting = false;
171  tsunami->cchip->clearDRIR(55);
172  DPRINTF(Tsunami, "clearing pic interrupt\n");
173  }
174  break;
175  case TSDEV_PIC2_MASK:
176  mask2 = pkt->getLE<uint8_t>();
177  //PIC2 Not implemented to interrupt
178  break;
179  case TSDEV_PIC1_ACK:
180  // clear the interrupt on the PIC
181  picr &= ~(1 << (pkt->getLE<uint8_t>() & 0xF));
182  if (!(picr & mask1))
183  tsunami->cchip->clearDRIR(55);
184  break;
185  case TSDEV_DMA1_MODE:
186  mode1 = pkt->getLE<uint8_t>();
187  break;
188  case TSDEV_DMA2_MODE:
189  mode2 = pkt->getLE<uint8_t>();
190  break;
191  case TSDEV_TMR0_DATA:
192  pitimer.writeCounter(0, pkt->getLE<uint8_t>());
193  break;
194  case TSDEV_TMR1_DATA:
195  pitimer.writeCounter(1, pkt->getLE<uint8_t>());
196  break;
197  case TSDEV_TMR2_DATA:
198  pitimer.writeCounter(2, pkt->getLE<uint8_t>());
199  break;
200  case TSDEV_TMR_CTRL:
201  pitimer.writeControl(pkt->getLE<uint8_t>());
202  break;
203  case TSDEV_RTC_ADDR:
204  rtcAddr = pkt->getLE<uint8_t>();
205  break;
206  case TSDEV_RTC_DATA:
207  rtc.writeData(rtcAddr, pkt->getLE<uint8_t>());
208  break;
209  case TSDEV_KBD:
210  case TSDEV_DMA1_CMND:
211  case TSDEV_DMA2_CMND:
212  case TSDEV_DMA1_MMASK:
213  case TSDEV_DMA2_MMASK:
214  case TSDEV_PIC2_ACK:
215  case TSDEV_DMA1_RESET:
216  case TSDEV_DMA2_RESET:
217  case TSDEV_DMA1_MASK:
218  case TSDEV_DMA2_MASK:
219  case TSDEV_CTRL_PORTB:
220  break;
221  default:
222  panic("I/O Write - va%#x size %d data %#x\n",
223  pkt->getAddr(), pkt->getSize(), pkt->getLE<uint8_t>());
224  }
225 
226  pkt->makeAtomicResponse();
227  return pioDelay;
228 }
229 
230 void
231 TsunamiIO::postPIC(uint8_t bitvector)
232 {
233  //PIC2 Is not implemented, because nothing of interest there
234  picr |= bitvector;
235  if (picr & mask1) {
236  tsunami->cchip->postDRIR(55);
237  DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
238  }
239 }
240 
241 void
242 TsunamiIO::clearPIC(uint8_t bitvector)
243 {
244  //PIC2 Is not implemented, because nothing of interest there
245  picr &= ~bitvector;
246  if (!(picr & mask1)) {
247  tsunami->cchip->clearDRIR(55);
248  DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
249  }
250 }
251 
252 void
254 {
263 
264  // Serialize the timers
265  pitimer.serialize("pitimer", cp);
266  rtc.serialize("rtc", cp);
267 }
268 
269 void
271 {
280 
281  // Unserialize the timers
282  pitimer.unserialize("pitimer", cp);
283  rtc.unserialize("rtc", cp);
284 }
285 
286 void
288 {
289  rtc.startup();
290  pitimer.startup();
291 }
292 
293 TsunamiIO *
294 TsunamiIOParams::create()
295 {
296  return new TsunamiIO(this);
297 }
#define TSDEV_RTC_DATA
Definition: tsunamireg.h:140
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:167
#define DPRINTF(x,...)
Definition: trace.hh:229
Emulation of the Tsunami CChip CSRs.
uint8_t readData(const uint8_t addr)
RTC read data.
Definition: mc146818.cc:232
void writeControl(const CtrlReg data)
Write control word.
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: tsunami_io.cc:253
Real-Time Clock (MC146818)
Definition: mc146818.hh:41
void postDRIR(uint32_t interrupt)
post an interrupt to the CPU.
#define TSDEV_DMA2_CMND
Definition: tsunamireg.h:131
void writeData(const uint8_t addr, const uint8_t data)
RTC write data.
Definition: mc146818.cc:139
Top level class for Tsunami Chipset emulation.
Definition: tsunami.hh:56
#define TSDEV_DMA2_MODE
Definition: tsunamireg.h:120
uint8_t mode1
Mode of PIC1.
Definition: tsunami_io.hh:78
void clearPIC(uint8_t bitvector)
Clear a posted interrupt.
Definition: tsunami_io.cc:242
void startup() override
Start running.
Definition: tsunami_io.cc:287
Tsunami * tsunami
Definition: tsunami_io.hh:60
Definition: cprintf.cc:42
uint8_t readCounter(unsigned int num)
#define TSDEV_TMR2_DATA
Definition: tsunamireg.h:126
TsunamiCChip * cchip
Pointer to the Tsunami CChip.
Definition: tsunami.hh:72
Tick Frequency
The simulated frequency of curTick(). (In ticks per second)
Definition: core.cc:49
#define TSDEV_DMA1_MASK
Definition: tsunamireg.h:121
#define TSDEV_DMA2_MASK
Definition: tsunamireg.h:122
#define TSDEV_DMA2_MMASK
Definition: tsunamireg.h:134
void writeCounter(unsigned int num, const uint8_t data)
void startup()
Start ticking.
void setLE(T v)
Set the value in the data pointer to v as little endian.
Bitfield< 31 > n
uint16_t timerData
The interval is set via two writes to the PIT.
Definition: tsunami_io.hh:103
bool picInterrupting
Is the pic interrupting right now or not.
Definition: tsunami_io.hh:87
unsigned getSize() const
Definition: packet.hh:736
bool outputHigh(unsigned int num)
#define TSDEV_TMR1_DATA
Definition: tsunamireg.h:125
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:645
#define TSDEV_TMR0_DATA
Definition: tsunamireg.h:124
uint8_t rtcAddr
Definition: tsunami_io.hh:97
void serialize(const std::string &base, CheckpointOut &cp) const
Serialize this object to the given output stream.
Definition: mc146818.cc:269
Addr pioSize
Size that the device&#39;s address range.
Definition: io_device.hh:160
void makeAtomicResponse()
Definition: packet.hh:949
uint64_t Tick
Tick count type.
Definition: types.hh:63
#define TSDEV_DMA1_MMASK
Definition: tsunamireg.h:133
Declaration of top level class for the Tsunami chipset.
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: tsunami_io.cc:270
const Params * params() const
Definition: tsunami_io.hh:121
Addr getAddr() const
Definition: packet.hh:726
RTC(const std::string &n, const TsunamiIOParams *p)
Definition: tsunami_io.cc:62
#define TSDEV_PIC1_MASK
Definition: tsunamireg.h:111
Port Object Declaration.
Tsunami * tsunami
A pointer to the Tsunami device which be belong to.
Definition: tsunami_io.hh:90
#define TSDEV_PIC1_ACK
Definition: tsunamireg.h:115
#define TSDEV_RTC_ADDR
Definition: tsunamireg.h:139
#define TSDEV_PIC2_MASK
Definition: tsunamireg.h:112
#define TSDEV_DMA1_CMND
Definition: tsunamireg.h:129
Tsunami I/O Space mapping including RTC/timer interrupts.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
#define TSDEV_DMA2_RESET
Definition: tsunamireg.h:118
#define TSDEV_PIC2_ISR
Definition: tsunamireg.h:114
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:255
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: tsunami_io.cc:150
TsunamiIO(const Params *p)
Initialize all the data for devices supported by Tsunami I/O.
Definition: tsunami_io.cc:68
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:643
TsunamiIOParams Params
Definition: tsunami_io.hh:113
uint8_t mode2
Mode of PIC2.
Definition: tsunami_io.hh:81
Tick frequency() const
Return the freqency of the RTC.
Definition: tsunami_io.cc:81
uint8_t mask2
Mask of the PIC2.
Definition: tsunami_io.hh:75
Declaration of the Packet class.
std::ostream CheckpointOut
Definition: serialize.hh:68
virtual void startup()
Start ticking.
Definition: mc146818.cc:127
#define TSDEV_TMR_CTRL
Definition: tsunamireg.h:127
Intel8254Timer pitimer
Intel 8253 Periodic Interval Timer.
Definition: tsunami_io.hh:93
List of Tsunami CSRs.
void unserialize(const std::string &base, CheckpointIn &cp)
Reconstruct the state of this object from a checkpoint.
Definition: mc146818.cc:289
#define TSDEV_CTRL_PORTB
Definition: tsunamireg.h:123
#define TSDEV_DMA1_MODE
Definition: tsunamireg.h:119
uint8_t picr
Raw PIC interrupt register before masking.
Definition: tsunami_io.hh:84
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:163
#define PORTB_SPKR_HIGH
Definition: tsunamireg.h:150
#define TSDEV_DMA1_RESET
Definition: tsunamireg.h:117
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
void clearDRIR(uint32_t interrupt)
clear an interrupt previously posted to the CPU.
Tsunami I/O device is a catch all for all the south bridge stuff we care to implement.
Definition: tsunami_io.hh:52
TsunamiIO * io
Pointer to the TsunamiIO device which has the RTC.
Definition: tsunami.hh:66
#define TSDEV_PIC1_ISR
Definition: tsunamireg.h:113
uint8_t mask1
Mask of the PIC1.
Definition: tsunami_io.hh:72
void postPIC(uint8_t bitvector)
Post an PIC interrupt to the CPU via the CChip.
Definition: tsunami_io.cc:231
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: tsunami_io.cc:87
Bitfield< 0 > p
const std::string & name() const
Definition: mc146818.hh:88
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:157
#define TSDEV_PIC2_ACK
Definition: tsunamireg.h:116
#define TSDEV_KBD
Definition: tsunamireg.h:137
void serialize(const std::string &base, CheckpointOut &cp) const
Serialize this object to the given output stream.
void unserialize(const std::string &base, CheckpointIn &cp)
Reconstruct the state of this object from a checkpoint.

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