gem5  v20.1.0.0
thread_context.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
29 #define __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
30 
31 #include <list>
32 #include <map>
33 #include <memory>
34 
35 #include "cpu/base.hh"
36 #include "cpu/thread_context.hh"
37 #include "iris/IrisInstance.h"
38 #include "iris/detail/IrisErrorCode.h"
39 #include "iris/detail/IrisObjects.h"
40 #include "sim/system.hh"
41 
42 namespace Iris
43 {
44 
45 // This class is the base for ThreadContexts which read and write state using
46 // the Iris API.
48 {
49  public:
50  typedef std::map<std::string, iris::ResourceInfo> ResourceMap;
51 
53  typedef std::map<int, std::string> IdxNameMap;
54 
55  protected:
57  int _threadId;
63 
64  std::string _irisPath;
65  iris::InstanceId _instId = iris::IRIS_UINT64_MAX;
66 
67  // Temporary holding places for the vector reg accessors to return.
68  // These are not updated live, only when requested.
71 
74 
75  virtual void initFromIrisInstance(const ResourceMap &resources);
76 
77  iris::ResourceId extractResourceId(
78  const ResourceMap &resources, const std::string &name);
80  const ResourceMap &resources, const IdxNameMap &idx_names);
81 
82 
88 
89  iris::ResourceId pcRscId = iris::IRIS_UINT64_MAX;
90  iris::ResourceId icountRscId;
91 
94 
97 
98  std::unique_ptr<PortProxy> virtProxy = nullptr;
99  std::unique_ptr<PortProxy> physProxy = nullptr;
100 
101 
102  // A queue to keep track of instruction count based events.
104  // A helper function to maintain the IRIS step count. This makes sure the
105  // step count is correct even after IRIS resets it for us, and also handles
106  // events which are supposed to happen at the current instruction count.
107  void maintainStepping();
108 
109 
110  using BpId = uint64_t;
111  struct BpInfo
112  {
116  std::shared_ptr<EventList> events;
117 
118  BpInfo(Addr _pc) : pc(_pc), events(new EventList) {}
119 
120  bool empty() const { return events->empty(); }
121  bool validIds() const { return !ids.empty(); }
122  void clearIds() { ids.clear(); }
123  };
124 
125  using BpInfoPtr = std::unique_ptr<BpInfo>;
126  using BpInfoMap = std::map<Addr, BpInfoPtr>;
127  using BpInfoIt = BpInfoMap::iterator;
128 
130 
132 
133  void installBp(BpInfoIt it);
134  void uninstallBp(BpInfoIt it);
135  void delBp(BpInfoIt it);
136 
137  virtual const std::vector<iris::MemorySpaceId> &getBpSpaceIds() const = 0;
138 
139 
140  iris::IrisErrorCode instanceRegistryChanged(
141  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
142  uint64_t sInstId, bool syncEc, std::string &error_message_out);
143  iris::IrisErrorCode phaseInitLeave(
144  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
145  uint64_t sInstId, bool syncEc, std::string &error_message_out);
146  iris::IrisErrorCode simulationTimeEvent(
147  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
148  uint64_t sInstId, bool syncEc, std::string &error_message_out);
149  iris::IrisErrorCode breakpointHit(
150  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
151  uint64_t sInstId, bool syncEc, std::string &error_message_out);
152  iris::IrisErrorCode semihostingEvent(
153  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
154  uint64_t sInstId, bool syncEc, std::string &error_message_out);
155 
156  iris::EventStreamId regEventStreamId;
157  iris::EventStreamId initEventStreamId;
158  iris::EventStreamId timeEventStreamId;
159  iris::EventStreamId breakpointEventStreamId;
160  iris::EventStreamId semihostingEventStreamId;
161 
162  mutable iris::IrisInstance client;
163  iris::IrisCppAdapter &call() const { return client.irisCall(); }
164  iris::IrisCppAdapter &noThrow() const { return client.irisCallNoThrow(); }
165 
166  bool translateAddress(Addr &paddr, iris::MemorySpaceId p_space,
167  Addr vaddr, iris::MemorySpaceId v_space);
168 
169  public:
170  ThreadContext(::BaseCPU *cpu, int id, System *system,
171  ::BaseTLB *dtb, ::BaseTLB *itb, ::BaseISA *isa,
172  iris::IrisConnectionInterface *iris_if,
173  const std::string &iris_path);
174  virtual ~ThreadContext();
175 
176  virtual bool translateAddress(Addr &paddr, Addr vaddr) = 0;
177 
178  bool schedule(PCEvent *e) override;
179  bool remove(PCEvent *e) override;
180 
181  void scheduleInstCountEvent(Event *event, Tick count) override;
182  void descheduleInstCountEvent(Event *event) override;
183  Tick getCurrentInstCount() override;
184 
185  ::BaseCPU *getCpuPtr() override { return _cpu; }
186  int cpuId() const override { return _cpu->cpuId(); }
187  uint32_t socketId() const override { return _cpu->socketId(); }
188 
189  int threadId() const override { return _threadId; }
190  void setThreadId(int id) override { _threadId = id; }
191 
192  int contextId() const override { return _contextId; }
193  void setContextId(int id) override { _contextId = id; }
194 
195  BaseTLB *
196  getITBPtr() override
197  {
198  return _itb;
199  }
200  BaseTLB *
201  getDTBPtr() override
202  {
203  return _dtb;
204  }
205  CheckerCPU *getCheckerCpuPtr() override { return nullptr; }
207  getDecoderPtr() override
208  {
209  panic("%s not implemented.", __FUNCTION__);
210  }
211 
212  System *getSystemPtr() override { return _cpu->system; }
213 
214  BaseISA *
215  getIsaPtr() override
216  {
217  return _isa;
218  }
219 
220  PortProxy &getPhysProxy() override { return *physProxy; }
221  PortProxy &getVirtProxy() override { return *virtProxy; }
222  void initMemProxies(::ThreadContext *tc) override;
223 
224  Process *
225  getProcessPtr() override
226  {
227  panic("%s not implemented.", __FUNCTION__);
228  }
229  void
231  {
232  panic("%s not implemented.", __FUNCTION__);
233  }
234 
235  Status status() const override;
236  void setStatus(Status new_status) override;
237  void activate() override { setStatus(Active); }
238  void suspend() override { setStatus(Suspended); }
239  void halt() override { setStatus(Halted); }
240 
241  void
242  takeOverFrom(::ThreadContext *old_context) override
243  {
244  panic("%s not implemented.", __FUNCTION__);
245  }
246 
247  void regStats(const std::string &name) override {}
248 
249  // Not necessarily the best location for these...
250  // Having an extra function just to read these is obnoxious
251  Tick
252  readLastActivate() override
253  {
254  panic("%s not implemented.", __FUNCTION__);
255  }
257  {
258  panic("%s not implemented.", __FUNCTION__);
259  }
260 
261  void
262  copyArchRegs(::ThreadContext *tc) override
263  {
264  panic("%s not implemented.", __FUNCTION__);
265  }
266 
267  void
268  clearArchRegs() override
269  {
270  warn("Ignoring clearArchRegs()");
271  }
272 
273  //
274  // New accessors for new decoder.
275  //
276  RegVal readIntReg(RegIndex reg_idx) const override;
277 
278  RegVal
279  readFloatReg(RegIndex reg_idx) const override
280  {
281  panic("%s not implemented.", __FUNCTION__);
282  }
283 
284  const VecRegContainer &readVecReg(const RegId &reg) const override;
286  getWritableVecReg(const RegId &reg) override
287  {
288  panic("%s not implemented.", __FUNCTION__);
289  }
290 
295  readVec8BitLaneReg(const RegId &reg) const override
296  {
297  panic("%s not implemented.", __FUNCTION__);
298  }
299 
302  readVec16BitLaneReg(const RegId &reg) const override
303  {
304  panic("%s not implemented.", __FUNCTION__);
305  }
306 
309  readVec32BitLaneReg(const RegId &reg) const override
310  {
311  panic("%s not implemented.", __FUNCTION__);
312  }
313 
316  readVec64BitLaneReg(const RegId &reg) const override
317  {
318  panic("%s not implemented.", __FUNCTION__);
319  }
320 
322  void
324  {
325  panic("%s not implemented.", __FUNCTION__);
326  }
327  void
329  const LaneData<LaneSize::TwoByte> &val) override
330  {
331  panic("%s not implemented.", __FUNCTION__);
332  }
333  void
335  const LaneData<LaneSize::FourByte> &val) override
336  {
337  panic("%s not implemented.", __FUNCTION__);
338  }
339  void
341  const LaneData<LaneSize::EightByte> &val) override
342  {
343  panic("%s not implemented.", __FUNCTION__);
344  }
347  const VecElem &
348  readVecElem(const RegId &reg) const override
349  {
350  panic("%s not implemented.", __FUNCTION__);
351  }
352 
353  const VecPredRegContainer &readVecPredReg(const RegId &reg) const override;
355  getWritableVecPredReg(const RegId &reg) override
356  {
357  panic("%s not implemented.", __FUNCTION__);
358  }
359 
360  RegVal
361  readCCReg(RegIndex reg_idx) const override
362  {
363  return readCCRegFlat(reg_idx);
364  }
365 
366  void setIntReg(RegIndex reg_idx, RegVal val) override;
367 
368  void
369  setFloatReg(RegIndex reg_idx, RegVal val) override
370  {
371  panic("%s not implemented.", __FUNCTION__);
372  }
373 
374  void
375  setVecReg(const RegId &reg, const VecRegContainer &val) override
376  {
377  panic("%s not implemented.", __FUNCTION__);
378  }
379 
380  void
381  setVecElem(const RegId& reg, const VecElem& val) override
382  {
383  panic("%s not implemented.", __FUNCTION__);
384  }
385 
386  void
388  const VecPredRegContainer &val) override
389  {
390  panic("%s not implemented.", __FUNCTION__);
391  }
392 
393  void
394  setCCReg(RegIndex reg_idx, RegVal val) override
395  {
396  setCCRegFlat(reg_idx, val);
397  }
398 
399  void pcStateNoRecord(const ArmISA::PCState &val) override { pcState(val); }
400  MicroPC microPC() const override { return 0; }
401 
402  ArmISA::PCState pcState() const override;
403  void pcState(const ArmISA::PCState &val) override;
404  Addr instAddr() const override;
405  Addr nextInstAddr() const override;
406 
407  RegVal readMiscRegNoEffect(RegIndex misc_reg) const override;
408  RegVal
409  readMiscReg(RegIndex misc_reg) override
410  {
411  return readMiscRegNoEffect(misc_reg);
412  }
413 
414  void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override;
415  void
416  setMiscReg(RegIndex misc_reg, const RegVal val) override
417  {
418  setMiscRegNoEffect(misc_reg, val);
419  }
420 
421  RegId
422  flattenRegId(const RegId& regId) const override
423  {
424  panic("%s not implemented.", __FUNCTION__);
425  }
426 
427  // Also not necessarily the best location for these two. Hopefully will go
428  // away once we decide upon where st cond failures goes.
429  unsigned
430  readStCondFailures() const override
431  {
432  panic("%s not implemented.", __FUNCTION__);
433  }
434 
435  void
436  setStCondFailures(unsigned sc_failures) override
437  {
438  panic("%s not implemented.", __FUNCTION__);
439  }
440 
441  // Same with st cond failures.
442  Counter
443  readFuncExeInst() const override
444  {
445  panic("%s not implemented.", __FUNCTION__);
446  }
447 
460  RegVal readIntRegFlat(RegIndex idx) const override;
461  void setIntRegFlat(RegIndex idx, uint64_t val) override;
462 
463  RegVal
464  readFloatRegFlat(RegIndex idx) const override
465  {
466  panic("%s not implemented.", __FUNCTION__);
467  }
468  void
470  {
471  panic("%s not implemented.", __FUNCTION__);
472  }
473 
474  const VecRegContainer &readVecRegFlat(RegIndex idx) const override;
477  {
478  panic("%s not implemented.", __FUNCTION__);
479  }
480  void
482  {
483  panic("%s not implemented.", __FUNCTION__);
484  }
485 
486  const VecElem&
487  readVecElemFlat(RegIndex idx, const ElemIndex& elemIdx) const override
488  {
489  panic("%s not implemented.", __FUNCTION__);
490  }
491  void
492  setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx,
493  const VecElem &val) override
494  {
495  panic("%s not implemented.", __FUNCTION__);
496  }
497 
498  const VecPredRegContainer &readVecPredRegFlat(RegIndex idx) const override;
501  {
502  panic("%s not implemented.", __FUNCTION__);
503  }
504  void
506  {
507  panic("%s not implemented.", __FUNCTION__);
508  }
509 
510  RegVal readCCRegFlat(RegIndex idx) const override;
511  void setCCRegFlat(RegIndex idx, RegVal val) override;
514  // hardware transactional memory
515  void
516  htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
517  {
518  panic("%s not implemented.", __FUNCTION__);
519  }
520 
523  {
524  panic("%s not implemented.", __FUNCTION__);
525  }
526 
527  void
529  {
530  panic("%s not implemented.", __FUNCTION__);
531  }
532 };
533 
534 } // namespace Iris
535 
536 #endif // __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
Iris::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override
Definition: thread_context.cc:571
Iris::ThreadContext::initMemProxies
void initMemProxies(::ThreadContext *tc) override
Definition: thread_context.cc:477
Iris::ThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.cc:591
Iris::ThreadContext::getVirtProxy
PortProxy & getVirtProxy() override
Definition: thread_context.hh:221
warn
#define warn(...)
Definition: logging.hh:239
Iris::ThreadContext::noThrow
iris::IrisCppAdapter & noThrow() const
Definition: thread_context.hh:164
Iris::ThreadContext::setVecReg
void setVecReg(const RegId &reg, const VecRegContainer &val) override
Definition: thread_context.hh:375
system.hh
Iris::ThreadContext::uninstallBp
void uninstallBp(BpInfoIt it)
Definition: thread_context.cc:170
Iris::ThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.hh:522
Iris::ThreadContext::readVecRegFlat
const VecRegContainer & readVecRegFlat(RegIndex idx) const override
Definition: thread_context.cc:673
VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:47
Iris::ThreadContext::enableAfterPseudoEvent
Event * enableAfterPseudoEvent
Definition: thread_context.hh:73
Iris
Definition: cpu.cc:34
Iris::ThreadContext::setProcessPtr
void setProcessPtr(Process *p) override
Definition: thread_context.hh:230
Iris::ThreadContext::pcState
ArmISA::PCState pcState() const override
Definition: thread_context.cc:513
Process
Definition: process.hh:65
Iris::ThreadContext::virtProxy
std::unique_ptr< PortProxy > virtProxy
Definition: thread_context.hh:98
Iris::ThreadContext::maintainStepping
void maintainStepping()
Definition: thread_context.cc:116
Iris::ThreadContext::timeEventStreamId
iris::EventStreamId timeEventStreamId
Definition: thread_context.hh:158
Iris::ThreadContext::readFloatRegFlat
RegVal readFloatRegFlat(RegIndex idx) const override
Definition: thread_context.hh:464
Iris::ThreadContext::pcRscId
iris::ResourceId pcRscId
Definition: thread_context.hh:89
Iris::ThreadContext::setVecElemFlat
void setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, const VecElem &val) override
Definition: thread_context.hh:492
Iris::ThreadContext::BpInfo::BpInfo
BpInfo(Addr _pc)
Definition: thread_context.hh:118
Iris::ThreadContext::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Definition: thread_context.hh:436
ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:231
Iris::ThreadContext::setContextId
void setContextId(int id) override
Definition: thread_context.hh:193
Iris::ThreadContext::miscRegIds
ResourceIds miscRegIds
Definition: thread_context.hh:83
Iris::ThreadContext::breakpointEventStreamId
iris::EventStreamId breakpointEventStreamId
Definition: thread_context.hh:159
Iris::ThreadContext::setVecElem
void setVecElem(const RegId &reg, const VecElem &val) override
Definition: thread_context.hh:381
Iris::ThreadContext::vecPredRegs
std::vector< ArmISA::VecPredRegContainer > vecPredRegs
Definition: thread_context.hh:70
Iris::ThreadContext::ccRegIds
ResourceIds ccRegIds
Definition: thread_context.hh:87
Iris::ThreadContext::physProxy
std::unique_ptr< PortProxy > physProxy
Definition: thread_context.hh:99
Iris::ThreadContext::readVecPredRegFlat
const VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
Definition: thread_context.cc:708
Iris::ThreadContext::getDTBPtr
BaseTLB * getDTBPtr() override
Definition: thread_context.hh:201
Iris::ThreadContext::BpInfo::pc
Addr pc
Definition: thread_context.hh:113
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
Iris::ThreadContext::ResourceIds
std::vector< iris::ResourceId > ResourceIds
Definition: thread_context.hh:52
Iris::ThreadContext::BpInfo
Definition: thread_context.hh:111
Iris::ThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) override
Definition: thread_context.hh:528
Iris::ThreadContext::getWritableVecPredReg
VecPredRegContainer & getWritableVecPredReg(const RegId &reg) override
Definition: thread_context.hh:355
Iris::ThreadContext::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: thread_context.hh:361
Iris::ThreadContext::setIntRegFlat
void setIntRegFlat(RegIndex idx, uint64_t val) override
Definition: thread_context.cc:620
Iris::ThreadContext::getPhysProxy
PortProxy & getPhysProxy() override
Definition: thread_context.hh:220
Iris::ThreadContext::takeOverFrom
void takeOverFrom(::ThreadContext *old_context) override
Definition: thread_context.hh:242
Iris::ThreadContext::initEventStreamId
iris::EventStreamId initEventStreamId
Definition: thread_context.hh:157
Iris::ThreadContext::readVec16BitLaneReg
ConstVecLane16 readVec16BitLaneReg(const RegId &reg) const override
Reads source vector 16bit operand.
Definition: thread_context.hh:302
CheckerCPU
CheckerCPU class.
Definition: cpu.hh:85
std::vector< iris::ResourceId >
Iris::ThreadContext::instanceRegistryChanged
iris::IrisErrorCode instanceRegistryChanged(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:190
Iris::ThreadContext::installBp
void installBp(BpInfoIt it)
Definition: thread_context.cc:158
Iris::ThreadContext::getWritableVecPredRegFlat
VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx) override
Definition: thread_context.hh:500
Iris::ThreadContext::regEventStreamId
iris::EventStreamId regEventStreamId
Definition: thread_context.hh:156
BaseCPU::socketId
uint32_t socketId() const
Reads this CPU's Socket ID.
Definition: base.hh:181
HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:44
X86ISA::count
count
Definition: misc.hh:703
Iris::ThreadContext::readFuncExeInst
Counter readFuncExeInst() const override
Definition: thread_context.hh:443
Iris::ThreadContext::_dtb
::BaseTLB * _dtb
Definition: thread_context.hh:60
Iris::ThreadContext::schedule
bool schedule(PCEvent *e) override
Definition: thread_context.cc:396
Iris::ThreadContext::getBpSpaceIds
virtual const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const =0
Iris::ThreadContext::_threadId
int _threadId
Definition: thread_context.hh:57
Iris::ThreadContext::translations
std::vector< iris::MemorySupportedAddressTranslationResult > translations
Definition: thread_context.hh:96
Iris::ThreadContext::setVecLane
void setVecLane(const RegId &reg, const LaneData< LaneSize::EightByte > &val) override
Definition: thread_context.hh:340
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
Iris::ThreadContext::getOrAllocBp
BpInfoIt getOrAllocBp(Addr pc)
Definition: thread_context.cc:145
Iris::ThreadContext::_contextId
ContextID _contextId
Definition: thread_context.hh:58
BaseTLB
Definition: tlb.hh:50
Iris::ThreadContext::status
Status status() const override
Definition: thread_context.cc:492
Iris::ThreadContext::getITBPtr
BaseTLB * getITBPtr() override
Definition: thread_context.hh:196
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
Iris::ThreadContext::nextInstAddr
Addr nextInstAddr() const override
Definition: thread_context.cc:557
Iris::ThreadContext::getDecoderPtr
ArmISA::Decoder * getDecoderPtr() override
Definition: thread_context.hh:207
Iris::ThreadContext::setThreadId
void setThreadId(int id) override
Definition: thread_context.hh:190
Iris::ThreadContext::translateAddress
bool translateAddress(Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)
Definition: thread_context.cc:420
Iris::ThreadContext::memorySpaces
std::vector< iris::MemorySpaceInfo > memorySpaces
Definition: thread_context.hh:95
Iris::ThreadContext::~ThreadContext
virtual ~ThreadContext()
Definition: thread_context.cc:373
Iris::ThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.hh:239
Iris::ThreadContext::readVecElem
const VecElem & readVecElem(const RegId &reg) const override
Definition: thread_context.hh:348
ThreadContext::VecElem
TheISA::VecElem VecElem
Definition: thread_context.hh:93
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
Counter
int64_t Counter
Statistics counter type.
Definition: types.hh:58
Iris::ThreadContext::setVecLane
void setVecLane(const RegId &reg, const LaneData< LaneSize::Byte > &val) override
Write a lane of the destination vector register.
Definition: thread_context.hh:323
Iris::ThreadContext::phaseInitLeave
iris::IrisErrorCode phaseInitLeave(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:212
Iris::ThreadContext::semihostingEvent
iris::IrisErrorCode semihostingEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:285
Iris::ThreadContext::readVec32BitLaneReg
ConstVecLane32 readVec32BitLaneReg(const RegId &reg) const override
Reads source vector 32bit operand.
Definition: thread_context.hh:309
Iris::ThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const override
Definition: thread_context.hh:279
Iris::ThreadContext::instAddr
Addr instAddr() const override
Definition: thread_context.cc:551
Iris::ThreadContext::breakpointHit
iris::IrisErrorCode breakpointHit(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:264
Iris::ThreadContext::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:369
Iris::ThreadContext::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: thread_context.hh:422
Iris::ThreadContext::BpInfo::validIds
bool validIds() const
Definition: thread_context.hh:121
Event
Definition: eventq.hh:246
VecLaneT
Vector Lane abstraction Another view of a container.
Definition: vec_reg.hh:262
Iris::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: thread_context.cc:578
Iris::ThreadContext::getIsaPtr
BaseISA * getIsaPtr() override
Definition: thread_context.hh:215
Iris::ThreadContext::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.hh:469
System
Definition: system.hh:73
Iris::ThreadContext::BpInfo::events
std::shared_ptr< EventList > events
Definition: thread_context.hh:116
ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:115
MipsISA::vaddr
vaddr
Definition: pra_constants.hh:275
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:297
Iris::ThreadContext::BpInfoPtr
std::unique_ptr< BpInfo > BpInfoPtr
Definition: thread_context.hh:125
Iris::ThreadContext::setVecRegFlat
void setVecRegFlat(RegIndex idx, const VecRegContainer &val) override
Definition: thread_context.hh:481
Iris::ThreadContext::setVecLane
void setVecLane(const RegId &reg, const LaneData< LaneSize::TwoByte > &val) override
Definition: thread_context.hh:328
Iris::ThreadContext::readVecPredReg
const VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: thread_context.cc:679
Iris::ThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.cc:632
Iris::ThreadContext::contextId
int contextId() const override
Definition: thread_context.hh:192
Iris::ThreadContext::IdxNameMap
std::map< int, std::string > IdxNameMap
Definition: thread_context.hh:53
Iris::ThreadContext::BpInfo::ids
std::vector< BpId > ids
Definition: thread_context.hh:114
Iris::ThreadContext::getWritableVecRegFlat
VecRegContainer & getWritableVecRegFlat(RegIndex idx) override
Definition: thread_context.hh:476
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
Iris::ThreadContext::vecRegs
std::vector< ArmISA::VecRegContainer > vecRegs
Definition: thread_context.hh:69
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ThreadContext::Status
Status
Definition: thread_context.hh:98
Iris::ThreadContext::call
iris::IrisCppAdapter & call() const
Definition: thread_context.hh:163
Iris::ThreadContext::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: thread_context.cc:450
BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:122
Iris::ThreadContext::microPC
MicroPC microPC() const override
Definition: thread_context.hh:400
Iris::ThreadContext::readStCondFailures
unsigned readStCondFailures() const override
Definition: thread_context.hh:430
name
const std::string & name()
Definition: trace.cc:50
Iris::ThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: thread_context.cc:563
Iris::ThreadContext::icountRscId
iris::ResourceId icountRscId
Definition: thread_context.hh:90
Iris::ThreadContext::intReg32Ids
ResourceIds intReg32Ids
Definition: thread_context.hh:84
Iris::ThreadContext::regStats
void regStats(const std::string &name) override
Definition: thread_context.hh:247
ArmISA::Decoder
Definition: decoder.hh:58
ArmISA::e
Bitfield< 9 > e
Definition: miscregs_types.hh:61
Iris::ThreadContext::remove
bool remove(PCEvent *e) override
Definition: thread_context.cc:408
Iris::ThreadContext::readVec8BitLaneReg
ConstVecLane8 readVec8BitLaneReg(const RegId &reg) const override
Vector Register Lane Interfaces.
Definition: thread_context.hh:295
Iris::ThreadContext::socketId
uint32_t socketId() const override
Definition: thread_context.hh:187
Iris::ThreadContext::pcStateNoRecord
void pcStateNoRecord(const ArmISA::PCState &val) override
Definition: thread_context.hh:399
Iris::ThreadContext::getCheckerCpuPtr
CheckerCPU * getCheckerCpuPtr() override
Definition: thread_context.hh:205
Iris::ThreadContext::semihostingEventStreamId
iris::EventStreamId semihostingEventStreamId
Definition: thread_context.hh:160
ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:106
Iris::ThreadContext::setVecLane
void setVecLane(const RegId &reg, const LaneData< LaneSize::FourByte > &val) override
Definition: thread_context.hh:334
ArmISA::ids
Bitfield< 39, 36 > ids
Definition: miscregs_types.hh:150
Iris::ThreadContext::client
iris::IrisInstance client
Definition: thread_context.hh:162
Iris::ThreadContext::setVecPredRegFlat
void setVecPredRegFlat(RegIndex idx, const VecPredRegContainer &val) override
Definition: thread_context.hh:505
PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:80
base.hh
Iris::ThreadContext::extractResourceMap
void extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
Definition: thread_context.cc:100
Iris::ThreadContext::ThreadContext
ThreadContext(::BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB *itb, ::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
Definition: thread_context.cc:306
Iris::ThreadContext::getCpuPtr
::BaseCPU * getCpuPtr() override
Definition: thread_context.hh:185
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
RegIndex
uint16_t RegIndex
Definition: types.hh:52
BaseCPU::system
System * system
Definition: base.hh:371
Iris::ThreadContext::intReg64Ids
ResourceIds intReg64Ids
Definition: thread_context.hh:85
Iris::ThreadContext::delBp
void delBp(BpInfoIt it)
Definition: thread_context.cc:178
Iris::ThreadContext::readLastSuspend
Tick readLastSuspend() override
Definition: thread_context.hh:256
Iris::ThreadContext::clearArchRegs
void clearArchRegs() override
Definition: thread_context.hh:268
Iris::ThreadContext::readVecElemFlat
const VecElem & readVecElemFlat(RegIndex idx, const ElemIndex &elemIdx) const override
Definition: thread_context.hh:487
Iris::ThreadContext::_system
System * _system
Definition: thread_context.hh:59
ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:55
Iris::ThreadContext::BpInfoIt
BpInfoMap::iterator BpInfoIt
Definition: thread_context.hh:127
Iris::ThreadContext::_itb
::BaseTLB * _itb
Definition: thread_context.hh:61
Iris::ThreadContext::extractResourceId
iris::ResourceId extractResourceId(const ResourceMap &resources, const std::string &name)
Definition: thread_context.cc:93
Iris::ThreadContext::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: thread_context.hh:409
Iris::ThreadContext::BpInfo::clearIds
void clearIds()
Definition: thread_context.hh:122
ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:102
Iris::ThreadContext::bps
BpInfoMap bps
Definition: thread_context.hh:129
Iris::ThreadContext::BpInfoMap
std::map< Addr, BpInfoPtr > BpInfoMap
Definition: thread_context.hh:126
Iris::ThreadContext::setStatus
void setStatus(Status new_status) override
Definition: thread_context.cc:498
Iris::ThreadContext::readVec64BitLaneReg
ConstVecLane64 readVec64BitLaneReg(const RegId &reg) const override
Reads source vector 64bit operand.
Definition: thread_context.hh:316
Iris::ThreadContext::vecPredRegIds
ResourceIds vecPredRegIds
Definition: thread_context.hh:93
Iris::ThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, const RegVal val) override
Definition: thread_context.hh:416
Iris::ThreadContext::_isa
::BaseISA * _isa
Definition: thread_context.hh:62
Iris::ThreadContext::_irisPath
std::string _irisPath
Definition: thread_context.hh:64
PCEvent
Definition: pc_event.hh:42
Iris::ThreadContext::BpInfo::empty
bool empty() const
Definition: thread_context.hh:120
Iris::ThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.hh:516
Iris::ThreadContext::flattenedIntIds
ResourceIds flattenedIntIds
Definition: thread_context.hh:86
Iris::ThreadContext::getProcessPtr
Process * getProcessPtr() override
Definition: thread_context.hh:225
Iris::ThreadContext::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: thread_context.cc:461
Iris::ThreadContext::getSystemPtr
System * getSystemPtr() override
Definition: thread_context.hh:212
EventQueue
Queue of events sorted in time order.
Definition: eventq.hh:617
Iris::ThreadContext::readLastActivate
Tick readLastActivate() override
Definition: thread_context.hh:252
Iris::ThreadContext::threadId
int threadId() const override
Definition: thread_context.hh:189
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
std::list< PCEvent * >
MicroPC
uint16_t MicroPC
Definition: types.hh:144
Iris::ThreadContext::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: thread_context.cc:468
Iris::ThreadContext::_instId
iris::InstanceId _instId
Definition: thread_context.hh:65
Iris::ThreadContext::_status
Status _status
Definition: thread_context.hh:72
Iris::ThreadContext::ResourceMap
std::map< std::string, iris::ResourceInfo > ResourceMap
Definition: thread_context.hh:50
Iris::ThreadContext::cpuId
int cpuId() const override
Definition: thread_context.hh:186
BaseISA
Definition: isa.hh:47
Iris::ThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:642
Iris::ThreadContext::comInstEventQueue
EventQueue comInstEventQueue
Definition: thread_context.hh:103
Iris::ThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.hh:237
Iris::ThreadContext::simulationTimeEvent
iris::IrisErrorCode simulationTimeEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:242
Iris::ThreadContext::getWritableVecReg
VecRegContainer & getWritableVecReg(const RegId &reg) override
Definition: thread_context.hh:286
Iris::ThreadContext
Definition: thread_context.hh:47
Iris::BaseCPU
Definition: cpu.hh:58
thread_context.hh
LaneData
LaneSize is an abstraction of a LS byte value for the execution and thread contexts to handle values ...
Definition: vec_reg.hh:458
Iris::ThreadContext::BpId
uint64_t BpId
Definition: thread_context.hh:110
BaseCPU::cpuId
int cpuId() const
Reads this CPU's ID.
Definition: base.hh:178
RegVal
uint64_t RegVal
Definition: types.hh:168
Iris::ThreadContext::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: thread_context.cc:607
Iris::ThreadContext::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:394
VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:156
Iris::ThreadContext::initFromIrisInstance
virtual void initFromIrisInstance(const ResourceMap &resources)
Definition: thread_context.cc:56
ArmISA::id
Bitfield< 33 > id
Definition: miscregs_types.hh:247
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
Iris::ThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.hh:238
Iris::ThreadContext::_cpu
::BaseCPU * _cpu
Definition: thread_context.hh:56
Iris::ThreadContext::copyArchRegs
void copyArchRegs(::ThreadContext *tc) override
Definition: thread_context.hh:262
Iris::ThreadContext::readVecReg
const VecRegContainer & readVecReg(const RegId &reg) const override
Definition: thread_context.cc:651
Iris::ThreadContext::setVecPredReg
void setVecPredReg(const RegId &reg, const VecPredRegContainer &val) override
Definition: thread_context.hh:387
Iris::ThreadContext::vecRegIds
ResourceIds vecRegIds
Definition: thread_context.hh:92

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