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Sequencer.hh
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1/*
2 * Copyright (c) 2019-2021 ARM Limited
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4 *
5 * The license below extends only to copyright in the software and shall
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10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
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13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
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26 * this software without specific prior written permission.
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34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39 */
40
41#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
42#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
43
44#include <iostream>
45#include <list>
46#include <unordered_map>
47
50#include "mem/ruby/protocol/MachineType.hh"
51#include "mem/ruby/protocol/RubyRequestType.hh"
52#include "mem/ruby/protocol/SequencerRequestType.hh"
55#include "params/RubySequencer.hh"
56
57namespace gem5
58{
59
60namespace ruby
61{
62
64{
66 RubyRequestType m_type;
67 RubyRequestType m_second_type;
69 SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
70 RubyRequestType _m_second_type, Cycles _issue_time)
71 : pkt(_pkt), m_type(_m_type), m_second_type(_m_second_type),
72 issue_time(_issue_time)
73 {}
74
75 bool functionalWrite(Packet *func_pkt) const
76 {
77 // Follow-up on RubyRequest::functionalWrite
78 // This makes sure the hitCallback won't overrite the value we
79 // expect to find
80 assert(func_pkt->isWrite());
81 return func_pkt->trySatisfyFunctional(pkt);
82 }
83};
84
85std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
86
87class Sequencer : public RubyPort
88{
89 public:
90 typedef RubySequencerParams Params;
91 Sequencer(const Params &);
92 ~Sequencer();
93
98 void writeCallbackScFail(Addr address,
100
101 // Public Methods
102 virtual void wakeup(); // Used only for deadlock detection
103 void resetStats() override;
105
106 void writeCallback(Addr address,
108 const bool externalHit = false,
109 const MachineType mach = MachineType_NUM,
110 const Cycles initialRequestTime = Cycles(0),
111 const Cycles forwardRequestTime = Cycles(0),
112 const Cycles firstResponseTime = Cycles(0),
113 const bool noCoales = false);
114
115 // Write callback that prevents coalescing
117 {
118 writeCallback(address, data, true, MachineType_NUM, Cycles(0),
119 Cycles(0), Cycles(0), true);
120 }
121
122 void readCallback(Addr address,
124 const bool externalHit = false,
125 const MachineType mach = MachineType_NUM,
126 const Cycles initialRequestTime = Cycles(0),
127 const Cycles forwardRequestTime = Cycles(0),
128 const Cycles firstResponseTime = Cycles(0));
129
130 void atomicCallback(Addr address,
132 const bool externalHit = false,
133 const MachineType mach = MachineType_NUM,
134 const Cycles initialRequestTime = Cycles(0),
135 const Cycles forwardRequestTime = Cycles(0),
136 const Cycles firstResponseTime = Cycles(0));
137
138 void unaddressedCallback(Addr unaddressedReqId,
139 RubyRequestType requestType,
140 const MachineType mach = MachineType_NUM,
141 const Cycles initialRequestTime = Cycles(0),
142 const Cycles forwardRequestTime = Cycles(0),
143 const Cycles firstResponseTime = Cycles(0));
144
146 void invL1Callback();
147 void invL1();
148
149 RequestStatus makeRequest(PacketPtr pkt) override;
150 virtual bool empty() const;
151 int outstandingCount() const override { return m_outstanding_count; }
152
153 bool isDeadlockEventScheduled() const override
154 { return deadlockCheckEvent.scheduled(); }
155
158
159 virtual void print(std::ostream& out) const;
160
161 void markRemoved();
162 void evictionCallback(Addr address);
163 int coreId() const { return m_coreId; }
164
165 virtual int functionalWrite(Packet *func_pkt) override;
166
167 void recordRequestType(SequencerRequestType requestType);
169
173
177
180
183
188
191
193 getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
194 { return *m_missTypeMachLatencyHist[r][t]; }
195
198
200 getInitialToForwardDelayHist(const MachineType t) const
201 { return *m_InitialToForwardDelayHist[t]; }
202
206
210
211 statistics::Counter getIncompleteTimes(const MachineType t) const
212 { return m_IncompleteTimes[t]; }
213
214 protected:
215 void issueRequest(PacketPtr pkt, RubyRequestType type);
216 virtual void hitCallback(SequencerRequest* srequest, DataBlock& data,
217 bool llscSuccess,
218 const MachineType mach, const bool externalHit,
219 const Cycles initialRequestTime,
220 const Cycles forwardRequestTime,
221 const Cycles firstResponseTime,
222 const bool was_coalesced);
223
224 virtual bool processReadCallback(SequencerRequest &seq_req,
226 const bool rubyRequest,
227 bool externalHit,
228 const MachineType mach,
229 Cycles initialRequestTime,
230 Cycles forwardRequestTime,
231 Cycles firstResponseTime);
232
233 void recordMissLatency(SequencerRequest* srequest, bool llscSuccess,
234 const MachineType respondingMach,
235 bool isExternalHit, Cycles initialRequestTime,
236 Cycles forwardRequestTime,
237 Cycles firstResponseTime);
238
239 private:
240 // Private copy constructor and assignment operator
241 Sequencer(const Sequencer& obj);
243
244 protected:
245 // RequestTable contains both read and write requests, handles aliasing
246 std::unordered_map<Addr, std::list<SequencerRequest>> m_RequestTable;
247 // UnadressedRequestTable contains "unaddressed" requests,
248 // guaranteed not to alias each other
249 std::unordered_map<uint64_t, SequencerRequest> m_UnaddressedRequestTable;
250
252
253 virtual RequestStatus insertRequest(PacketPtr pkt,
254 RubyRequestType primary_type,
255 RubyRequestType secondary_type);
256
258
259 private:
261
263
265
267
268 // The cache access latency for top-level caches (L0/L1). These are
269 // currently assessed at the beginning of each memory access through the
270 // sequencer.
271 // TODO: Migrate these latencies into top-level cache controllers.
274
275 // Global outstanding request count, across all request tables
278
280
282
284
287
291
296
301
306
312
319
321
322 // support for LL/SC
323
328 void llscLoadLinked(const Addr);
329
334 void llscClearMonitor(const Addr);
335
344 bool llscStoreConditional(const Addr);
345
346
351
356 uint64_t getCurrentUnaddressedTransactionID() const;
357
358 public:
365 bool llscCheckMonitor(const Addr);
366
367
373};
374
375inline std::ostream&
376operator<<(std::ostream& out, const Sequencer& obj)
377{
378 obj.print(out);
379 out << std::flush;
380 return out;
381}
382
383} // namespace ruby
384} // namespace gem5
385
386#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
const char data[]
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
bool isWrite() const
Definition packet.hh:594
bool trySatisfyFunctional(PacketPtr other)
Check a functional request against a memory value stored in another packet (i.e.
Definition packet.hh:1399
statistics::Histogram m_outstandReqHist
Histogram for number of outstanding requests per cycle.
Definition Sequencer.hh:286
void resetStats() override
Callback to reset stats.
Definition Sequencer.cc:281
statistics::Histogram & getLatencyHist()
Definition Sequencer.hh:170
Sequencer(const Sequencer &obj)
std::unordered_map< Addr, std::list< SequencerRequest > > m_RequestTable
Definition Sequencer.hh:246
int outstandingCount() const override
Definition Sequencer.hh:151
virtual bool empty() const
Definition Sequencer.cc:933
void writeCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0), const bool noCoales=false)
Definition Sequencer.cc:464
statistics::Histogram & getMissTypeLatencyHist(uint32_t t)
Definition Sequencer.hh:186
std::vector< statistics::Counter > m_IncompleteTimes
Definition Sequencer.hh:318
bool llscCheckMonitor(const Addr)
Searches for cache line address in the global monitor tagged with this Sequencer object's version id.
Definition Sequencer.cc:207
virtual int functionalWrite(Packet *func_pkt) override
Definition Sequencer.cc:264
std::vector< statistics::Histogram * > m_InitialToForwardDelayHist
Definition Sequencer.hh:315
RubySystem * m_ruby_system
Definition Sequencer.hh:257
statistics::Histogram & getMissMachLatencyHist(uint32_t t) const
Definition Sequencer.hh:189
std::vector< statistics::Histogram * > m_hitMachLatencyHist
Histograms for profiling the latencies for requests that did not required external messages.
Definition Sequencer.hh:299
void recordMissLatency(SequencerRequest *srequest, bool llscSuccess, const MachineType respondingMach, bool isExternalHit, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime)
Definition Sequencer.cc:391
void completeHitCallback(std::vector< PacketPtr > &list)
Definition Sequencer.cc:851
std::vector< statistics::Histogram * > m_typeLatencyHist
Definition Sequencer.hh:290
PacketPtr m_cache_inv_pkt
Definition Sequencer.hh:264
void atomicCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))
Definition Sequencer.cc:640
bool isDeadlockEventScheduled() const override
Definition Sequencer.hh:153
void writeCallbackScFail(Addr address, DataBlock &data)
Proxy function to writeCallback that first invalidates the line address in the local monitor.
Definition Sequencer.cc:457
statistics::Histogram & getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
Definition Sequencer.hh:181
CacheMemory * m_dataCache_ptr
Definition Sequencer.hh:266
std::vector< statistics::Histogram * > m_FirstResponseToCompletionDelayHist
Definition Sequencer.hh:317
void incrementUnaddressedTransactionCnt()
Increment the unaddressed transaction counter.
statistics::Histogram & getTypeLatencyHist(uint32_t t)
Definition Sequencer.hh:171
virtual void hitCallback(SequencerRequest *srequest, DataBlock &data, bool llscSuccess, const MachineType mach, const bool externalHit, const Cycles initialRequestTime, const Cycles forwardRequestTime, const Cycles firstResponseTime, const bool was_coalesced)
Definition Sequencer.cc:696
statistics::Counter getIncompleteTimes(const MachineType t) const
Definition Sequencer.hh:211
void llscLoadLinked(const Addr)
Places the cache line address into the global monitor tagged with this Sequencer object's version id.
Definition Sequencer.cc:157
uint64_t getCurrentUnaddressedTransactionID() const
Generate the current unaddressed transaction ID based on the counter and the Sequencer object's versi...
statistics::Histogram m_latencyHist
Histogram for holding latency profile of all requests.
Definition Sequencer.hh:289
statistics::Histogram & getHitMachLatencyHist(uint32_t t)
Definition Sequencer.hh:178
void issueRequest(PacketPtr pkt, RubyRequestType type)
bool llscStoreConditional(const Addr)
Searches for cache line address in the global monitor tagged with this Sequencer object's version id.
Definition Sequencer.cc:184
statistics::Histogram & getIssueToInitialDelayHist(uint32_t t) const
Definition Sequencer.hh:196
statistics::Histogram & getInitialToForwardDelayHist(const MachineType t) const
Definition Sequencer.hh:200
void unaddressedCallback(Addr unaddressedReqId, RubyRequestType requestType, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))
Definition Sequencer.cc:801
virtual RequestStatus insertRequest(PacketPtr pkt, RubyRequestType primary_type, RubyRequestType secondary_type)
Definition Sequencer.cc:313
Sequencer & operator=(const Sequencer &obj)
EventFunctionWrapper deadlockCheckEvent
Definition Sequencer.hh:320
std::unordered_map< uint64_t, SequencerRequest > m_UnaddressedRequestTable
Definition Sequencer.hh:249
uint64_t m_unaddressedTransactionCnt
Definition Sequencer.hh:281
std::vector< statistics::Histogram * > m_hitTypeLatencyHist
Definition Sequencer.hh:295
statistics::Histogram m_hitLatencyHist
Histogram for holding latency profile of all requests that hit in the controller connected to this se...
Definition Sequencer.hh:294
RequestStatus makeRequest(PacketPtr pkt) override
Definition Sequencer.cc:940
statistics::Histogram & getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
Definition Sequencer.hh:193
void descheduleDeadlockEvent() override
Definition Sequencer.hh:156
Cycles m_data_cache_hit_latency
Definition Sequencer.hh:272
statistics::Histogram & getFirstResponseToCompletionDelayHist(const MachineType t) const
Definition Sequencer.hh:208
void llscClearLocalMonitor()
Removes all addresses from the local monitor.
Definition Sequencer.cc:223
void recordRequestType(SequencerRequestType requestType)
std::vector< statistics::Histogram * > m_IssueToInitialDelayHist
Histograms for recording the breakdown of miss latency.
Definition Sequencer.hh:314
virtual void print(std::ostream &out) const
statistics::Histogram & getOutstandReqHist()
Definition Sequencer.hh:168
statistics::Histogram & getHitLatencyHist()
Definition Sequencer.hh:174
virtual bool processReadCallback(SequencerRequest &seq_req, DataBlock &data, const bool rubyRequest, bool externalHit, const MachineType mach, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime)
Definition Sequencer.cc:568
statistics::Histogram & getHitTypeLatencyHist(uint32_t t)
Definition Sequencer.hh:175
RubySequencerParams Params
Definition Sequencer.hh:90
std::vector< std::vector< statistics::Histogram * > > m_hitTypeMachLatencyHist
Definition Sequencer.hh:300
statistics::Histogram & getMissLatencyHist()
Definition Sequencer.hh:184
void llscClearMonitor(const Addr)
Removes the cache line address from the global monitor.
Definition Sequencer.cc:170
void writeUniqueCallback(Addr address, DataBlock &data)
Definition Sequencer.hh:116
Cycles m_inst_cache_hit_latency
Definition Sequencer.hh:273
virtual void wakeup()
Definition Sequencer.cc:229
void evictionCallback(Addr address)
std::vector< statistics::Histogram * > m_ForwardToFirstResponseDelayHist
Definition Sequencer.hh:316
statistics::Histogram & getForwardRequestToFirstResponseHist(const MachineType t) const
Definition Sequencer.hh:204
void readCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))
Definition Sequencer.cc:595
std::vector< statistics::Histogram * > m_missMachLatencyHist
Histograms for profiling the latencies for requests that required external messages.
Definition Sequencer.hh:309
std::vector< statistics::Histogram * > m_missTypeLatencyHist
Definition Sequencer.hh:305
statistics::Histogram m_missLatencyHist
Histogram for holding latency profile of all requests that miss in the controller connected to this s...
Definition Sequencer.hh:304
std::vector< std::vector< statistics::Histogram * > > m_missTypeMachLatencyHist
Definition Sequencer.hh:311
A simple histogram stat.
STL vector class.
Definition stl.hh:37
void deschedule(Event &event)
Definition eventq.hh:1021
bool scheduled() const
Determine if the current event is scheduled.
Definition eventq.hh:458
Bitfield< 5 > t
Definition misc_types.hh:71
double Counter
All counters are of 64-bit values.
Definition types.hh:46
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
std::ostream & operator<<(std::ostream &os, const BaseSemihosting::InPlaceArg &ipa)
SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, RubyRequestType _m_second_type, Cycles _issue_time)
Definition Sequencer.hh:69
RubyRequestType m_second_type
Definition Sequencer.hh:67
bool functionalWrite(Packet *func_pkt) const
Definition Sequencer.hh:75

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