41 #ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
42 #define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
46 #include <unordered_map>
49 #include "mem/ruby/protocol/MachineType.hh"
50 #include "mem/ruby/protocol/RubyRequestType.hh"
51 #include "mem/ruby/protocol/SequencerRequestType.hh"
54 #include "params/RubySequencer.hh"
69 RubyRequestType _m_second_type,
Cycles _issue_time)
107 const bool externalHit =
false,
108 const MachineType mach = MachineType_NUM,
112 const bool noCoales =
false);
123 const bool externalHit =
false,
124 const MachineType mach = MachineType_NUM,
130 RubyRequestType requestType,
131 const MachineType mach = MachineType_NUM,
137 virtual bool empty()
const;
146 virtual void print(std::ostream& out)
const;
206 const MachineType mach,
const bool externalHit,
207 const Cycles initialRequestTime,
208 const Cycles forwardRequestTime,
209 const Cycles firstResponseTime,
210 const bool was_coalesced);
213 const MachineType respondingMach,
214 bool isExternalHit,
Cycles initialRequestTime,
215 Cycles forwardRequestTime,
216 Cycles firstResponseTime);
232 RubyRequestType primary_type,
233 RubyRequestType secondary_type);
Cycles is a wrapper class for representing cycle counts, i.e.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
bool trySatisfyFunctional(PacketPtr other)
Check a functional request against a memory value stored in another packet (i.e.
statistics::Histogram m_outstandReqHist
Histogram for number of outstanding requests per cycle.
void resetStats() override
Callback to reset stats.
statistics::Histogram & getHitLatencyHist()
Cycles m_deadlock_threshold
Sequencer(const Sequencer &obj)
std::unordered_map< Addr, std::list< SequencerRequest > > m_RequestTable
int outstandingCount() const override
virtual bool empty() const
void writeCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0), const bool noCoales=false)
statistics::Histogram & getHitTypeLatencyHist(uint32_t t)
statistics::Histogram & getForwardRequestToFirstResponseHist(const MachineType t) const
std::vector< statistics::Counter > m_IncompleteTimes
bool llscCheckMonitor(const Addr)
Searches for cache line address in the global monitor tagged with this Sequencer object's version id.
statistics::Histogram & getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
virtual int functionalWrite(Packet *func_pkt) override
std::vector< statistics::Histogram * > m_InitialToForwardDelayHist
statistics::Histogram & getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
std::vector< statistics::Histogram * > m_hitMachLatencyHist
Histograms for profiling the latencies for requests that did not required external messages.
void recordMissLatency(SequencerRequest *srequest, bool llscSuccess, const MachineType respondingMach, bool isExternalHit, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime)
statistics::Histogram & getMissTypeLatencyHist(uint32_t t)
statistics::Histogram & getMissLatencyHist()
std::vector< statistics::Histogram * > m_typeLatencyHist
statistics::Histogram & getOutstandReqHist()
bool isDeadlockEventScheduled() const override
void writeCallbackScFail(Addr address, DataBlock &data)
Proxy function to writeCallback that first invalidates the line address in the local monitor.
CacheMemory * m_dataCache_ptr
statistics::Histogram & getLatencyHist()
std::vector< statistics::Histogram * > m_FirstResponseToCompletionDelayHist
void incrementUnaddressedTransactionCnt()
Increment the unaddressed transaction counter.
statistics::Histogram & getIssueToInitialDelayHist(uint32_t t) const
void hitCallback(SequencerRequest *srequest, DataBlock &data, bool llscSuccess, const MachineType mach, const bool externalHit, const Cycles initialRequestTime, const Cycles forwardRequestTime, const Cycles firstResponseTime, const bool was_coalesced)
statistics::Counter getIncompleteTimes(const MachineType t) const
void llscLoadLinked(const Addr)
Places the cache line address into the global monitor tagged with this Sequencer object's version id.
uint64_t getCurrentUnaddressedTransactionID() const
Generate the current unaddressed transaction ID based on the counter and the Sequencer object's versi...
Sequencer(const Params &)
statistics::Histogram m_latencyHist
Histogram for holding latency profile of all requests.
Sequencer & operator=(const Sequencer &obj)
void issueRequest(PacketPtr pkt, RubyRequestType type)
bool llscStoreConditional(const Addr)
Searches for cache line address in the global monitor tagged with this Sequencer object's version id.
void unaddressedCallback(Addr unaddressedReqId, RubyRequestType requestType, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))
virtual RequestStatus insertRequest(PacketPtr pkt, RubyRequestType primary_type, RubyRequestType secondary_type)
statistics::Histogram & getTypeLatencyHist(uint32_t t)
EventFunctionWrapper deadlockCheckEvent
std::unordered_map< uint64_t, SequencerRequest > m_UnaddressedRequestTable
uint64_t m_unaddressedTransactionCnt
std::vector< statistics::Histogram * > m_hitTypeLatencyHist
bool m_runningGarnetStandalone
bool m_deadlock_check_scheduled
statistics::Histogram & getFirstResponseToCompletionDelayHist(const MachineType t) const
statistics::Histogram m_hitLatencyHist
Histogram for holding latency profile of all requests that hit in the controller connected to this se...
RequestStatus makeRequest(PacketPtr pkt) override
statistics::Histogram & getInitialToForwardDelayHist(const MachineType t) const
void descheduleDeadlockEvent() override
Cycles m_data_cache_hit_latency
int m_max_outstanding_requests
void llscClearLocalMonitor()
Removes all addresses from the local monitor.
void recordRequestType(SequencerRequestType requestType)
std::vector< statistics::Histogram * > m_IssueToInitialDelayHist
Histograms for recording the breakdown of miss latency.
virtual void print(std::ostream &out) const
RubySequencerParams Params
std::vector< std::vector< statistics::Histogram * > > m_hitTypeMachLatencyHist
void llscClearMonitor(const Addr)
Removes the cache line address from the global monitor.
void writeUniqueCallback(Addr address, DataBlock &data)
Cycles m_inst_cache_hit_latency
void evictionCallback(Addr address)
statistics::Histogram & getMissMachLatencyHist(uint32_t t) const
std::vector< statistics::Histogram * > m_ForwardToFirstResponseDelayHist
void readCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))
std::vector< statistics::Histogram * > m_missMachLatencyHist
Histograms for profiling the latencies for requests that required external messages.
std::vector< statistics::Histogram * > m_missTypeLatencyHist
statistics::Histogram m_missLatencyHist
Histogram for holding latency profile of all requests that miss in the controller connected to this s...
statistics::Histogram & getHitMachLatencyHist(uint32_t t)
std::vector< std::vector< statistics::Histogram * > > m_missTypeMachLatencyHist
void deschedule(Event &event)
bool scheduled() const
Determine if the current event is scheduled.
std::ostream & operator<<(std::ostream &os, const BoolVec &myvector)
double Counter
All counters are of 64-bit values.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, RubyRequestType _m_second_type, Cycles _issue_time)
RubyRequestType m_second_type
bool functionalWrite(Packet *func_pkt) const