gem5  v21.1.0.2
Sequencer.hh
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40 
41 #ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
42 #define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
43 
44 #include <iostream>
45 #include <list>
46 #include <unordered_map>
47 
49 #include "mem/ruby/protocol/MachineType.hh"
50 #include "mem/ruby/protocol/RubyRequestType.hh"
51 #include "mem/ruby/protocol/SequencerRequestType.hh"
54 #include "params/RubySequencer.hh"
55 
56 namespace gem5
57 {
58 
59 namespace ruby
60 {
61 
63 {
65  RubyRequestType m_type;
66  RubyRequestType m_second_type;
68  SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
69  RubyRequestType _m_second_type, Cycles _issue_time)
70  : pkt(_pkt), m_type(_m_type), m_second_type(_m_second_type),
71  issue_time(_issue_time)
72  {}
73 
74  bool functionalWrite(Packet *func_pkt) const
75  {
76  // Follow-up on RubyRequest::functionalWrite
77  // This makes sure the hitCallback won't overrite the value we
78  // expect to find
79  assert(func_pkt->isWrite());
80  return func_pkt->trySatisfyFunctional(pkt);
81  }
82 };
83 
84 std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
85 
86 class Sequencer : public RubyPort
87 {
88  public:
89  typedef RubySequencerParams Params;
90  Sequencer(const Params &);
91  ~Sequencer();
92 
97  void writeCallbackScFail(Addr address,
98  DataBlock& data);
99 
100  // Public Methods
101  virtual void wakeup(); // Used only for deadlock detection
102  void resetStats() override;
103  void collateStats();
104 
105  void writeCallback(Addr address,
106  DataBlock& data,
107  const bool externalHit = false,
108  const MachineType mach = MachineType_NUM,
109  const Cycles initialRequestTime = Cycles(0),
110  const Cycles forwardRequestTime = Cycles(0),
111  const Cycles firstResponseTime = Cycles(0),
112  const bool noCoales = false);
113 
114  // Write callback that prevents coalescing
116  {
117  writeCallback(address, data, true, MachineType_NUM, Cycles(0),
118  Cycles(0), Cycles(0), true);
119  }
120 
121  void readCallback(Addr address,
122  DataBlock& data,
123  const bool externalHit = false,
124  const MachineType mach = MachineType_NUM,
125  const Cycles initialRequestTime = Cycles(0),
126  const Cycles forwardRequestTime = Cycles(0),
127  const Cycles firstResponseTime = Cycles(0));
128 
129  RequestStatus makeRequest(PacketPtr pkt) override;
130  virtual bool empty() const;
131  int outstandingCount() const override { return m_outstanding_count; }
132 
133  bool isDeadlockEventScheduled() const override
134  { return deadlockCheckEvent.scheduled(); }
135 
136  void descheduleDeadlockEvent() override
138 
139  virtual void print(std::ostream& out) const;
140 
141  void markRemoved();
142  void evictionCallback(Addr address);
143  int coreId() const { return m_coreId; }
144 
145  virtual int functionalWrite(Packet *func_pkt) override;
146 
147  void recordRequestType(SequencerRequestType requestType);
149 
152  { return *m_typeLatencyHist[t]; }
153 
156  { return *m_hitTypeLatencyHist[t]; }
157 
159  { return *m_hitMachLatencyHist[t]; }
160 
162  { return *m_hitTypeMachLatencyHist[r][t]; }
163 
165  { return m_missLatencyHist; }
167  { return *m_missTypeLatencyHist[t]; }
168 
170  { return *m_missMachLatencyHist[t]; }
171 
173  getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
174  { return *m_missTypeMachLatencyHist[r][t]; }
175 
177  { return *m_IssueToInitialDelayHist[t]; }
178 
180  getInitialToForwardDelayHist(const MachineType t) const
181  { return *m_InitialToForwardDelayHist[t]; }
182 
184  getForwardRequestToFirstResponseHist(const MachineType t) const
186 
188  getFirstResponseToCompletionDelayHist(const MachineType t) const
190 
191  statistics::Counter getIncompleteTimes(const MachineType t) const
192  { return m_IncompleteTimes[t]; }
193 
194  private:
195  void issueRequest(PacketPtr pkt, RubyRequestType type);
196 
197  void hitCallback(SequencerRequest* srequest, DataBlock& data,
198  bool llscSuccess,
199  const MachineType mach, const bool externalHit,
200  const Cycles initialRequestTime,
201  const Cycles forwardRequestTime,
202  const Cycles firstResponseTime,
203  const bool was_coalesced);
204 
205  void recordMissLatency(SequencerRequest* srequest, bool llscSuccess,
206  const MachineType respondingMach,
207  bool isExternalHit, Cycles initialRequestTime,
208  Cycles forwardRequestTime,
209  Cycles firstResponseTime);
210 
211  // Private copy constructor and assignment operator
212  Sequencer(const Sequencer& obj);
213  Sequencer& operator=(const Sequencer& obj);
214 
215  protected:
216  // RequestTable contains both read and write requests, handles aliasing
217  std::unordered_map<Addr, std::list<SequencerRequest>> m_RequestTable;
218 
220 
221  virtual RequestStatus insertRequest(PacketPtr pkt,
222  RubyRequestType primary_type,
223  RubyRequestType secondary_type);
224 
225  private:
227 
229 
230  // The cache access latency for top-level caches (L0/L1). These are
231  // currently assessed at the beginning of each memory access through the
232  // sequencer.
233  // TODO: Migrate these latencies into top-level cache controllers.
236 
237  // Global outstanding request count, across all request tables
240 
241  int m_coreId;
242 
244 
247 
251 
256 
261 
266 
272 
279 
281 
282  // support for LL/SC
283 
288  void llscLoadLinked(const Addr);
289 
294  void llscClearMonitor(const Addr);
295 
304  bool llscStoreConditional(const Addr);
305 
306  public:
313  bool llscCheckMonitor(const Addr);
314 
315 
320  void llscClearLocalMonitor();
321 };
322 
323 inline std::ostream&
324 operator<<(std::ostream& out, const Sequencer& obj)
325 {
326  obj.print(out);
327  out << std::flush;
328  return out;
329 }
330 
331 } // namespace ruby
332 } // namespace gem5
333 
334 #endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
gem5::ruby::Sequencer::m_FirstResponseToCompletionDelayHist
std::vector< statistics::Histogram * > m_FirstResponseToCompletionDelayHist
Definition: Sequencer.hh:277
gem5::ruby::Sequencer::~Sequencer
~Sequencer()
Definition: Sequencer.cc:144
gem5::ruby::Sequencer::m_RequestTable
std::unordered_map< Addr, std::list< SequencerRequest > > m_RequestTable
Definition: Sequencer.hh:217
gem5::ruby::Sequencer::m_hitMachLatencyHist
std::vector< statistics::Histogram * > m_hitMachLatencyHist
Histograms for profiling the latencies for requests that did not required external messages.
Definition: Sequencer.hh:259
gem5::ruby::Sequencer
Definition: Sequencer.hh:86
gem5::ruby::Sequencer::m_deadlock_threshold
Cycles m_deadlock_threshold
Definition: Sequencer.hh:219
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ruby::Sequencer::getTypeLatencyHist
statistics::Histogram & getTypeLatencyHist(uint32_t t)
Definition: Sequencer.hh:151
gem5::ruby::Sequencer::makeRequest
RequestStatus makeRequest(PacketPtr pkt) override
Definition: Sequencer.cc:657
gem5::ruby::Sequencer::writeCallbackScFail
void writeCallbackScFail(Addr address, DataBlock &data)
Proxy function to writeCallback that first invalidates the line address in the local monitor.
Definition: Sequencer.cc:401
gem5::ruby::Sequencer::issueRequest
void issueRequest(PacketPtr pkt, RubyRequestType type)
Definition: Sequencer.cc:773
gem5::ruby::Sequencer::m_inst_cache_hit_latency
Cycles m_inst_cache_hit_latency
Definition: Sequencer.hh:235
gem5::ruby::Sequencer::getOutstandReqHist
statistics::Histogram & getOutstandReqHist()
Definition: Sequencer.hh:148
gem5::ruby::Sequencer::m_dataCache_ptr
CacheMemory * m_dataCache_ptr
Definition: Sequencer.hh:228
gem5::ruby::Sequencer::m_outstandReqHist
statistics::Histogram m_outstandReqHist
Histogram for number of outstanding requests per cycle.
Definition: Sequencer.hh:246
gem5::ruby::operator<<
std::ostream & operator<<(std::ostream &os, const BoolVec &myvector)
Definition: BoolVec.cc:49
gem5::ruby::Sequencer::m_data_cache_hit_latency
Cycles m_data_cache_hit_latency
Definition: Sequencer.hh:234
gem5::ruby::Sequencer::getIssueToInitialDelayHist
statistics::Histogram & getIssueToInitialDelayHist(uint32_t t) const
Definition: Sequencer.hh:176
gem5::ruby::Sequencer::hitCallback
void hitCallback(SequencerRequest *srequest, DataBlock &data, bool llscSuccess, const MachineType mach, const bool externalHit, const Cycles initialRequestTime, const Cycles forwardRequestTime, const Cycles firstResponseTime, const bool was_coalesced)
Definition: Sequencer.cc:565
gem5::ruby::Sequencer::getHitMachLatencyHist
statistics::Histogram & getHitMachLatencyHist(uint32_t t)
Definition: Sequencer.hh:158
gem5::ruby::Sequencer::insertRequest
virtual RequestStatus insertRequest(PacketPtr pkt, RubyRequestType primary_type, RubyRequestType secondary_type)
Definition: Sequencer.cc:302
gem5::ruby::Sequencer::Params
RubySequencerParams Params
Definition: Sequencer.hh:89
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::ruby::Sequencer::getIncompleteTimes
statistics::Counter getIncompleteTimes(const MachineType t) const
Definition: Sequencer.hh:191
gem5::ruby::Sequencer::isDeadlockEventScheduled
bool isDeadlockEventScheduled() const override
Definition: Sequencer.hh:133
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ruby::Sequencer::m_missLatencyHist
statistics::Histogram m_missLatencyHist
Histogram for holding latency profile of all requests that miss in the controller connected to this s...
Definition: Sequencer.hh:264
gem5::ruby::SequencerRequest::SequencerRequest
SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, RubyRequestType _m_second_type, Cycles _issue_time)
Definition: Sequencer.hh:68
gem5::ruby::Sequencer::outstandingCount
int outstandingCount() const override
Definition: Sequencer.hh:131
gem5::ruby::Sequencer::getMissMachLatencyHist
statistics::Histogram & getMissMachLatencyHist(uint32_t t) const
Definition: Sequencer.hh:169
gem5::ruby::Sequencer::recordRequestType
void recordRequestType(SequencerRequestType requestType)
Definition: Sequencer.cc:841
gem5::ruby::Sequencer::coreId
int coreId() const
Definition: Sequencer.hh:143
gem5::ruby::Sequencer::getLatencyHist
statistics::Histogram & getLatencyHist()
Definition: Sequencer.hh:150
gem5::ruby::SequencerRequest::functionalWrite
bool functionalWrite(Packet *func_pkt) const
Definition: Sequencer.hh:74
gem5::ruby::Sequencer::getMissTypeMachLatencyHist
statistics::Histogram & getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
Definition: Sequencer.hh:173
gem5::ruby::Sequencer::m_outstanding_count
int m_outstanding_count
Definition: Sequencer.hh:238
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::ruby::Sequencer::m_missMachLatencyHist
std::vector< statistics::Histogram * > m_missMachLatencyHist
Histograms for profiling the latencies for requests that required external messages.
Definition: Sequencer.hh:269
gem5::ruby::Sequencer::m_missTypeMachLatencyHist
std::vector< std::vector< statistics::Histogram * > > m_missTypeMachLatencyHist
Definition: Sequencer.hh:271
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2123
gem5::ruby::Sequencer::getMissTypeLatencyHist
statistics::Histogram & getMissTypeLatencyHist(uint32_t t)
Definition: Sequencer.hh:166
gem5::ruby::Sequencer::evictionCallback
void evictionCallback(Addr address)
Definition: Sequencer.cc:847
gem5::ruby::Sequencer::operator=
Sequencer & operator=(const Sequencer &obj)
gem5::ruby::Sequencer::getHitTypeLatencyHist
statistics::Histogram & getHitTypeLatencyHist(uint32_t t)
Definition: Sequencer.hh:155
gem5::ruby::Sequencer::readCallback
void readCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))
Definition: Sequencer.cc:510
gem5::ruby::Sequencer::recordMissLatency
void recordMissLatency(SequencerRequest *srequest, bool llscSuccess, const MachineType respondingMach, bool isExternalHit, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime)
Definition: Sequencer.cc:335
CacheMemory.hh
gem5::ruby::Sequencer::m_ForwardToFirstResponseDelayHist
std::vector< statistics::Histogram * > m_ForwardToFirstResponseDelayHist
Definition: Sequencer.hh:276
gem5::ruby::Sequencer::llscStoreConditional
bool llscStoreConditional(const Addr)
Searches for cache line address in the global monitor tagged with this Sequencer object's version id.
Definition: Sequencer.cc:176
gem5::ruby::Sequencer::m_latencyHist
statistics::Histogram m_latencyHist
Histogram for holding latency profile of all requests.
Definition: Sequencer.hh:249
gem5::ruby::Sequencer::llscCheckMonitor
bool llscCheckMonitor(const Addr)
Searches for cache line address in the global monitor tagged with this Sequencer object's version id.
Definition: Sequencer.cc:199
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ruby::Sequencer::m_IssueToInitialDelayHist
std::vector< statistics::Histogram * > m_IssueToInitialDelayHist
Histograms for recording the breakdown of miss latency.
Definition: Sequencer.hh:274
gem5::ruby::SequencerRequest::m_second_type
RubyRequestType m_second_type
Definition: Sequencer.hh:66
gem5::ruby::Sequencer::llscClearLocalMonitor
void llscClearLocalMonitor()
Removes all addresses from the local monitor.
Definition: Sequencer.cc:215
gem5::ruby::SequencerRequest
Definition: Sequencer.hh:62
gem5::ruby::Sequencer::m_missTypeLatencyHist
std::vector< statistics::Histogram * > m_missTypeLatencyHist
Definition: Sequencer.hh:265
gem5::ruby::Sequencer::m_InitialToForwardDelayHist
std::vector< statistics::Histogram * > m_InitialToForwardDelayHist
Definition: Sequencer.hh:275
gem5::ruby::Sequencer::writeUniqueCallback
void writeUniqueCallback(Addr address, DataBlock &data)
Definition: Sequencer.hh:115
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::ruby::Sequencer::functionalWrite
virtual int functionalWrite(Packet *func_pkt) override
Definition: Sequencer.cc:256
gem5::ruby::Sequencer::m_hitTypeMachLatencyHist
std::vector< std::vector< statistics::Histogram * > > m_hitTypeMachLatencyHist
Definition: Sequencer.hh:260
gem5::ruby::Sequencer::getHitTypeMachLatencyHist
statistics::Histogram & getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
Definition: Sequencer.hh:161
gem5::ruby::Sequencer::resetStats
void resetStats() override
Callback to reset stats.
Definition: Sequencer.cc:270
gem5::ruby::Sequencer::descheduleDeadlockEvent
void descheduleDeadlockEvent() override
Definition: Sequencer.hh:136
gem5::ruby::Sequencer::m_hitLatencyHist
statistics::Histogram m_hitLatencyHist
Histogram for holding latency profile of all requests that hit in the controller connected to this se...
Definition: Sequencer.hh:254
gem5::ruby::Sequencer::m_hitTypeLatencyHist
std::vector< statistics::Histogram * > m_hitTypeLatencyHist
Definition: Sequencer.hh:255
gem5::ruby::Sequencer::Sequencer
Sequencer(const Params &)
Definition: Sequencer.cc:68
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
gem5::ruby::Sequencer::m_runningGarnetStandalone
bool m_runningGarnetStandalone
Definition: Sequencer.hh:243
gem5::ruby::Sequencer::empty
virtual bool empty() const
Definition: Sequencer.cc:651
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ruby::Sequencer::getInitialToForwardDelayHist
statistics::Histogram & getInitialToForwardDelayHist(const MachineType t) const
Definition: Sequencer.hh:180
gem5::EventManager::deschedule
void deschedule(Event &event)
Definition: eventq.hh:1028
gem5::ruby::Sequencer::m_max_outstanding_requests
int m_max_outstanding_requests
Definition: Sequencer.hh:226
gem5::ruby::Sequencer::print
virtual void print(std::ostream &out) const
Definition: Sequencer.cc:832
gem5::ruby::Sequencer::wakeup
virtual void wakeup()
Definition: Sequencer.cc:221
gem5::ruby::Sequencer::llscLoadLinked
void llscLoadLinked(const Addr)
Places the cache line address into the global monitor tagged with this Sequencer object's version id.
Definition: Sequencer.cc:149
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::ruby::Sequencer::markRemoved
void markRemoved()
Definition: Sequencer.cc:329
gem5::ruby::RubyPort::Params
RubyPortParams Params
Definition: RubyPort.hh:153
Address.hh
gem5::ruby::Sequencer::llscClearMonitor
void llscClearMonitor(const Addr)
Removes the cache line address from the global monitor.
Definition: Sequencer.cc:162
gem5::ruby::Sequencer::getForwardRequestToFirstResponseHist
statistics::Histogram & getForwardRequestToFirstResponseHist(const MachineType t) const
Definition: Sequencer.hh:184
gem5::ruby::Sequencer::getHitLatencyHist
statistics::Histogram & getHitLatencyHist()
Definition: Sequencer.hh:154
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::ruby::Sequencer::writeCallback
void writeCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0), const bool noCoales=false)
Definition: Sequencer.cc:408
gem5::ruby::SequencerRequest::m_type
RubyRequestType m_type
Definition: Sequencer.hh:65
gem5::ruby::SequencerRequest::issue_time
Cycles issue_time
Definition: Sequencer.hh:67
gem5::ruby::CacheMemory
Definition: CacheMemory.hh:69
gem5::Packet::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr other)
Check a functional request against a memory value stored in another packet (i.e.
Definition: packet.hh:1358
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::ruby::Sequencer::m_coreId
int m_coreId
Definition: Sequencer.hh:241
gem5::ruby::DataBlock
Definition: DataBlock.hh:60
gem5::ruby::Sequencer::deadlockCheckEvent
EventFunctionWrapper deadlockCheckEvent
Definition: Sequencer.hh:280
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
RubyPort.hh
gem5::ruby::Sequencer::m_deadlock_check_scheduled
bool m_deadlock_check_scheduled
Definition: Sequencer.hh:239
gem5::ruby::RubyPort
Definition: RubyPort.hh:64
gem5::ruby::Sequencer::getFirstResponseToCompletionDelayHist
statistics::Histogram & getFirstResponseToCompletionDelayHist(const MachineType t) const
Definition: Sequencer.hh:188
gem5::ruby::Sequencer::getMissLatencyHist
statistics::Histogram & getMissLatencyHist()
Definition: Sequencer.hh:164
gem5::ruby::Sequencer::m_IncompleteTimes
std::vector< statistics::Counter > m_IncompleteTimes
Definition: Sequencer.hh:278
gem5::ruby::Sequencer::m_typeLatencyHist
std::vector< statistics::Histogram * > m_typeLatencyHist
Definition: Sequencer.hh:250
gem5::ruby::Sequencer::collateStats
void collateStats()
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ruby::SequencerRequest::pkt
PacketPtr pkt
Definition: Sequencer.hh:64

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