35#include "debug/RubyNetwork.hh"
60 : m_nodes(MachineType_base_number(MachineType_NUM)),
61 m_number_of_switches(num_routers), m_vnets(num_vnets),
62 m_ext_link_vector(ext_links), m_int_link_vector(int_links)
76 i != ext_links.end(); ++
i) {
81 int machine_base_idx = MachineType_base_number(abs_cntrl->
getType());
82 int ext_idx1 = machine_base_idx + abs_cntrl->
getVersion();
83 int ext_idx2 = ext_idx1 +
m_nodes;
88 addLink(ext_idx1, int_idx, ext_link);
90 addLink(int_idx, ext_idx2, ext_link);
95 i != int_links.end(); ++
i) {
110 addLink(src, dst, int_link, src_outport, dst_inport);
119 for (LinkMap::const_iterator
i =
m_link_map.begin();
122 max_switch_id = std::max(max_switch_id, src_dest.first);
123 max_switch_id = std::max(max_switch_id, src_dest.second);
127 int num_switches = max_switch_id+1;
131 Matrix component_latencies(num_switches,
134 Matrix component_inter_switches(num_switches,
139 for (
int i = 0;
i < topology_weights[0].size();
i++) {
141 topology_weights[
v][
i][
i] = 0;
149 int src = src_dest.first;
150 int dst = src_dest.second;
154 for (
int l = 0;
l < link_entries.size();
l++) {
156 if (link->
mVnets.size() == 0) {
160 fatal_if(vnet_done[
v],
"Two links connecting same src"
161 " and destination cannot support same vnets");
163 component_latencies[src][dst][
v] = link->
m_latency;
164 topology_weights[
v][src][dst] = link->
m_weight;
168 for (
int v = 0;
v < link->
mVnets.size();
v++) {
171 "(setting latency and weight for vnet %d)", vnet);
174 fatal_if(vnet_done[vnet],
"Two links connecting same src"
175 " and destination cannot support same vnets");
177 component_latencies[src][dst][vnet] = link->
m_latency;
178 topology_weights[vnet][src][dst] = link->
m_weight;
179 vnet_done[vnet] =
true;
187 component_inter_switches);
189 for (
int i = 0;
i < topology_weights[0].size();
i++) {
190 for (
int j = 0; j < topology_weights[0][
i].size(); j++) {
197 bool realLink =
false;
200 int weight = topology_weights[
v][
i][j];
226 src_dest_pair.first = src;
227 src_dest_pair.second = dest;
230 link_entry.
link = link;
241 lit->second.push_back(link_entry);
244 links.push_back(link_entry);
261 src_dest.first = src;
262 src_dest.second = dest;
264 for (
int l = 0;
l < links.size();
l++) {
265 link_entry = links[
l];
269 if (link->
mVnets.size() == 0) {
271 routing_table_entry);
273 for (
int v = 0;
v< link->
mVnets.size();
v++) {
275 linkRoute[vnet] = routing_table_entry[vnet];
284 src_dest.first = src;
285 src_dest.second = dest;
287 for (
int l = 0;
l < links.size();
l++) {
288 link_entry = links[
l];
292 if (link->
mVnets.size() == 0) {
294 routing_table_entry);
296 for (
int v = 0;
v< link->
mVnets.size();
v++) {
298 linkRoute[vnet] = routing_table_entry[vnet];
306 src_dest.first = src;
307 src_dest.second = dest;
309 for (
int l = 0;
l < links.size();
l++) {
310 link_entry = links[
l];
314 if (link->
mVnets.size() == 0) {
316 dest - (2 *
m_nodes), link, routing_table_entry,
320 for (
int v = 0;
v< link->
mVnets.size();
v++) {
322 linkRoute[vnet] = routing_table_entry[vnet];
325 dest - (2 *
m_nodes), link, linkRoute,
339 int nodes = current_dist[0].size();
351 for (
int i = 0;
i < nodes;
i++) {
352 for (
int j = 0; j < nodes; j++) {
364 int minimum = current_dist[
v][
i][j];
365 int previous_minimum = minimum;
366 int intermediate_switch = -1;
367 for (
int k = 0;
k < nodes;
k++) {
368 minimum = std::min(minimum,
369 current_dist[
v][
i][
k] + current_dist[
v][
k][j]);
370 if (previous_minimum != minimum) {
371 intermediate_switch =
k;
372 inter_switches[
i][j][
v] =
373 inter_switches[
i][
k][
v] +
374 inter_switches[
k][j][
v] + 1;
376 previous_minimum = minimum;
378 if (current_dist[
v][
i][j] != minimum) {
380 current_dist[
v][
i][j] = minimum;
381 assert(intermediate_switch >= 0);
382 assert(intermediate_switch < latencies[
i].size());
384 latencies[
i][intermediate_switch][
v] +
385 latencies[intermediate_switch][j][
v];
407 return weights[vnet][src][next] +
dist[vnet][next][
final] ==
408 dist[vnet][src][
final];
421 machines = MachineType_NUM;
422 max_machines = MachineType_base_number(MachineType_NUM);
424 for (
int m = 0;
m < machines;
m++) {
425 for (
NodeID i = 0;
i < MachineType_base_count((MachineType)
m);
i++) {
432 weights,
dist, vnet)) {
440 DPRINTF(RubyNetwork,
"Returning shortest path\n"
441 "(src-(2*max_machines)): %d, (next-(2*max_machines)): %d, "
442 "src: %d, next: %d, vnet:%d result: %s\n",
443 (src-(2*max_machines)), (next-(2*max_machines)),
444 src, next, vnet, result);
MachineType getType() const
NodeID getVersion() const
std::vector< int > mVnets
void add(MachineID newElement)
virtual void makeInternalLink(SwitchID src, SwitchID dest, BasicLink *link, std::vector< NetDest > &routing_table_entry, PortDirection src_outport, PortDirection dst_inport)=0
virtual void makeExtOutLink(SwitchID src, NodeID dest, BasicLink *link, std::vector< NetDest > &routing_table_entry)=0
virtual void makeExtInLink(NodeID src, SwitchID dest, BasicLink *link, std::vector< NetDest > &routing_table_entry)=0
std::vector< BasicIntLink * > m_int_link_vector
void makeLink(Network *net, SwitchID src, SwitchID dest, std::vector< NetDest > &routing_table_entry)
void addLink(SwitchID src, SwitchID dest, BasicLink *link, PortDirection src_outport_dirn="", PortDirection dest_inport_dirn="")
const uint32_t m_number_of_switches
void createLinks(Network *net)
void extend_shortest_path(Matrix ¤t_dist, Matrix &latencies, Matrix &inter_switches)
Topology(uint32_t num_nodes, uint32_t num_routers, uint32_t num_vnets, const std::vector< BasicExtLink * > &ext_links, const std::vector< BasicIntLink * > &int_links)
bool link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, const Matrix &weights, const Matrix &dist, int vnet)
Matrix shortest_path(const Matrix &weights, Matrix &latencies, Matrix &inter_switches)
NetDest shortest_path_to_node(SwitchID src, SwitchID next, const Matrix &weights, const Matrix &dist, int vnet)
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
const Params & params() const
std::string PortDirection
const int INFINITE_LATENCY
const FlagsType dist
Print the distribution.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
PortDirection dst_inport_dirn
PortDirection src_outport_dirn