gem5  v22.0.0.2
AbstractController.hh
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40 
41 #ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
42 #define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
43 
44 #include <exception>
45 #include <iostream>
46 #include <string>
47 #include <unordered_map>
48 
49 #include "base/addr_range.hh"
50 #include "base/addr_range_map.hh"
51 #include "base/callback.hh"
52 #include "mem/packet.hh"
53 #include "mem/qport.hh"
60 #include "mem/ruby/protocol/AccessPermission.hh"
62 #include "params/RubyController.hh"
63 #include "sim/clocked_object.hh"
64 
65 namespace gem5
66 {
67 
68 namespace ruby
69 {
70 
71 class Network;
72 class GPUCoalescer;
73 class DMASequencer;
74 
75 // used to communicate that an in_port peeked the wrong message type
76 class RejectException: public std::exception
77 {
78  virtual const char* what() const throw()
79  { return "Port rejected message based on type"; }
80 };
81 
83 {
84  public:
85  PARAMS(RubyController);
86  AbstractController(const Params &p);
87  void init();
88 
89  NodeID getVersion() const { return m_machineID.getNum(); }
90  MachineType getType() const { return m_machineID.getType(); }
91 
92  void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
93 
94  // return instance name
96  bool isBlocked(Addr) const;
97  void unblock(Addr);
98  bool isBlocked(Addr);
99 
100  virtual MessageBuffer* getMandatoryQueue() const = 0;
101  virtual MessageBuffer* getMemReqQueue() const = 0;
102  virtual MessageBuffer* getMemRespQueue() const = 0;
103  virtual AccessPermission getAccessPermission(const Addr &addr) = 0;
104 
105  virtual void print(std::ostream & out) const = 0;
106  virtual void wakeup() = 0;
107  virtual void resetStats() = 0;
108  virtual void regStats();
109 
110  virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
111  virtual Sequencer* getCPUSequencer() const = 0;
112  virtual DMASequencer* getDMASequencer() const = 0;
113  virtual GPUCoalescer* getGPUCoalescer() const = 0;
114 
115  // This latency is used by the sequencer when enqueueing requests.
116  // Different latencies may be used depending on the request type.
117  // This is the hit latency unless the top-level cache controller
118  // introduces additional cycles in the response path.
119  virtual Cycles mandatoryQueueLatency(const RubyRequestType& param_type)
120  { return m_mandatory_queue_latency; }
121 
124  virtual bool functionalReadBuffers(PacketPtr&) = 0;
125  virtual void functionalRead(const Addr &addr, PacketPtr)
126  { panic("functionalRead(Addr,PacketPtr) not implemented"); }
127 
130  virtual bool functionalReadBuffers(PacketPtr&, WriteMask &mask) = 0;
131  virtual void functionalRead(const Addr &addr, PacketPtr pkt,
132  WriteMask &mask)
133  { panic("functionalRead(Addr,PacketPtr,WriteMask) not implemented"); }
134 
138  virtual int functionalWriteBuffers(PacketPtr&) = 0;
139  virtual int functionalWrite(const Addr &addr, PacketPtr) = 0;
141 
143  virtual void enqueuePrefetch(const Addr &, const RubyRequestType&)
144  { fatal("Prefetches not implemented!");}
145 
148  virtual void notifyCoalesced(const Addr& addr,
149  const RubyRequestType& type,
150  const RequestPtr& req,
151  const DataBlock& data_blk,
152  const bool& was_miss)
153  { }
154 
158  virtual void collateStats()
159  {fatal("collateStats() should be overridden!");}
160 
162  virtual void initNetQueues() = 0;
163 
165  Port &getPort(const std::string &if_name,
166  PortID idx=InvalidPortID);
167 
168  void recvTimingResp(PacketPtr pkt);
170 
171  const AddrRangeList &getAddrRanges() const { return addrRanges; }
172 
173  public:
174  MachineID getMachineID() const { return m_machineID; }
175  RequestorID getRequestorId() const { return m_id; }
176 
179  { return *(stats.delayVCHistogram[index]); }
180 
182  {
183  for (auto &range: addrRanges)
184  if (range.contains(addr)) return true;
185  return false;
186  }
187 
201  MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
202 
215  MachineType mtype = MachineType_NUM) const;
216 
219 
221  const NetDest& allUpstreamDest() const { return upstreamDestinations; }
222 
223  protected:
225  void profileRequest(const std::string &request);
227  void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
228 
229  // Tracks outstanding transactions for latency profiling
230  struct TransMapPair { unsigned transaction; unsigned state; Tick time; };
231  std::unordered_map<Addr, TransMapPair> m_inTransAddressed;
232  std::unordered_map<Addr, TransMapPair> m_outTransAddressed;
233 
234  std::unordered_map<Addr, TransMapPair> m_inTransUnaddressed;
235  std::unordered_map<Addr, TransMapPair> m_outTransUnaddressed;
236 
251  template<typename EventType, typename StateType>
253  EventType type, StateType initialState, bool retried,
254  bool isAddressed=true)
255  {
256  auto& m_inTrans =
258  assert(m_inTrans.find(addr) == m_inTrans.end());
259  m_inTrans[addr] = {type, initialState, curTick()};
260  if (retried)
262  }
263 
274  template<typename StateType>
275  void incomingTransactionEnd(Addr addr, StateType finalState,
276  bool isAddressed=true)
277  {
278  auto& m_inTrans =
280  auto iter = m_inTrans.find(addr);
281  assert(iter != m_inTrans.end());
282  stats.inTransLatHist[iter->second.transaction]
283  [iter->second.state]
284  [(unsigned)finalState]->sample(
285  ticksToCycles(curTick() - iter->second.time));
286  ++(*stats.inTransLatTotal[iter->second.transaction]);
287  m_inTrans.erase(iter);
288  }
289 
301  template<typename EventType>
303  bool isAddressed=true)
304  {
305  auto& m_outTrans =
307  assert(m_outTrans.find(addr) == m_outTrans.end());
308  m_outTrans[addr] = {type, 0, curTick()};
309  }
310 
321  void outgoingTransactionEnd(Addr addr, bool retried,
322  bool isAddressed=true)
323  {
324  auto& m_outTrans =
326  auto iter = m_outTrans.find(addr);
327  assert(iter != m_outTrans.end());
328  stats.outTransLatHist[iter->second.transaction]->sample(
329  ticksToCycles(curTick() - iter->second.time));
330  if (retried)
331  ++(*stats.outTransLatHistRetries[iter->second.transaction]);
332  m_outTrans.erase(iter);
333  }
334 
335  void stallBuffer(MessageBuffer* buf, Addr addr);
336  void wakeUpBuffer(MessageBuffer* buf, Addr addr);
337  void wakeUpBuffers(Addr addr);
338  void wakeUpAllBuffers(Addr addr);
339  void wakeUpAllBuffers();
340  bool serviceMemoryQueue();
341 
342  protected:
346 
347  // RequestorID used by some components of gem5.
349 
352  std::map<Addr, MessageBuffer*> m_block_map;
353 
355  typedef std::set<MessageBuffer*> MsgBufType;
356  typedef std::map<Addr, MsgVecType* > WaitingBufType;
358 
359  unsigned int m_in_ports;
360  unsigned int m_cur_in_port;
361  const int m_number_of_TBEs;
363  const unsigned int m_buffer_size;
367 
372  class MemoryPort : public RequestPort
373  {
374  private:
375  // Controller that operates this port.
377 
378  public:
379  MemoryPort(const std::string &_name, AbstractController *_controller,
380  PortID id = InvalidPortID);
381 
382  protected:
383  // Function for receiving a timing response from the peer port.
384  // Currently the pkt is handed to the coherence controller
385  // associated with this port.
386  bool recvTimingResp(PacketPtr pkt);
387 
388  void recvReqRetry();
389  };
390 
391  /* Request port to the memory controller. */
393 
394  // State that is stored in packets sent to the memory controller.
396  {
397  // Id of the machine from which the request originated.
399 
401  {}
402  };
403 
404  private:
407 
408  typedef std::unordered_map<MachineType, MachineID> AddrMapEntry;
409 
411 
414 
415  public:
417  {
419 
420  // Initialized by the SLICC compiler for all combinations of event and
421  // states. Only histograms with samples will appear in the stats
426 
427  // Initialized by the SLICC compiler for all events.
428  // Only histograms with samples will appear in the stats.
431 
435 
440  } stats;
441 
442 };
443 
444 } // namespace ruby
445 } // namespace gem5
446 
447 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
MachineID.hh
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::ruby::MachineID::getType
MachineType getType() const
Definition: MachineID.hh:66
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::ruby::AbstractController::MsgBufType
std::set< MessageBuffer * > MsgBufType
Definition: AbstractController.hh:355
gem5::ruby::AbstractController::getVersion
NodeID getVersion() const
Definition: AbstractController.hh:89
gem5::ruby::Sequencer
Definition: Sequencer.hh:86
gem5::ruby::AbstractController::outgoingTransactionEnd
void outgoingTransactionEnd(Addr addr, bool retried, bool isAddressed=true)
Profiles the end of an outgoing transaction.
Definition: AbstractController.hh:321
gem5::ruby::WriteMask
Definition: WriteMask.hh:59
gem5::ruby::AbstractController::ControllerStats::fullyBusyCycles
statistics::Scalar fullyBusyCycles
Counter for the number of cycles when the transitions carried out were equal to the maximum allowed.
Definition: AbstractController.hh:434
gem5::ruby::AbstractController::ControllerStats::outTransLatHist
std::vector< statistics::Histogram * > outTransLatHist
Definition: AbstractController.hh:429
gem5::ruby::AbstractController::m_number_of_TBEs
const int m_number_of_TBEs
Definition: AbstractController.hh:361
gem5::AddrRangeMap< AddrMapEntry, 3 >
gem5::ruby::AbstractController::getMemReqQueue
virtual MessageBuffer * getMemReqQueue() const =0
Histogram.hh
gem5::ruby::AbstractController::recordCacheTrace
virtual void recordCacheTrace(int cntrl, CacheRecorder *tr)=0
gem5::ruby::AbstractController::profileMsgDelay
void profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
Profiles the delay associated with messages.
Definition: AbstractController.cc:137
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ruby::AbstractController::getType
MachineType getType() const
Definition: AbstractController.hh:90
gem5::ruby::AbstractController::getMachineID
MachineID getMachineID() const
Definition: AbstractController.hh:174
gem5::ruby::AbstractController::profileRequest
void profileRequest(const std::string &request)
Profiles original cache requests including PUTs.
gem5::ruby::AbstractController::SenderState::SenderState
SenderState(MachineID _id)
Definition: AbstractController.hh:400
gem5::ruby::AbstractController::TransMapPair::state
unsigned state
Definition: AbstractController.hh:230
gem5::ruby::AbstractController::ControllerStats::inTransLatHist
std::vector< std::vector< std::vector< statistics::Histogram * > > > inTransLatHist
Definition: AbstractController.hh:423
gem5::ruby::AbstractController::getGPUCoalescer
virtual GPUCoalescer * getGPUCoalescer() const =0
gem5::ruby::AbstractController::serviceMemoryQueue
bool serviceMemoryQueue()
Definition: AbstractController.cc:261
gem5::ruby::Network
Definition: Network.hh:82
gem5::ruby::AbstractController::WaitingBufType
std::map< Addr, MsgVecType * > WaitingBufType
Definition: AbstractController.hh:356
gem5::ruby::AbstractController::getDelayHist
statistics::Histogram & getDelayHist()
Definition: AbstractController.hh:177
gem5::ruby::AbstractController::wakeUpBuffers
void wakeUpBuffers(Addr addr)
Definition: AbstractController.cc:181
gem5::ruby::AbstractController::resetStats
virtual void resetStats()=0
Callback to reset stats.
Definition: AbstractController.cc:121
gem5::ruby::AbstractController::MemoryPort
Port that forwards requests and receives responses from the memory controller.
Definition: AbstractController.hh:372
gem5::ruby::AbstractController::m_recycle_latency
Cycles m_recycle_latency
Definition: AbstractController.hh:364
gem5::ruby::AbstractController::mapAddressToDownstreamMachine
MachineID mapAddressToDownstreamMachine(Addr addr, MachineType mtype=MachineType_NUM) const
Maps an address to the correct dowstream MachineID (i.e.
Definition: AbstractController.cc:419
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ruby::AbstractController::m_block_map
std::map< Addr, MessageBuffer * > m_block_map
Definition: AbstractController.hh:352
gem5::ruby::AbstractController::m_inTransUnaddressed
std::unordered_map< Addr, TransMapPair > m_inTransUnaddressed
Definition: AbstractController.hh:234
gem5::ruby::AbstractController::isBlocked
bool isBlocked(Addr) const
Definition: AbstractController.cc:327
gem5::ruby::AbstractController::m_clusterID
const NodeID m_clusterID
Definition: AbstractController.hh:345
gem5::ruby::AbstractController::m_outTransAddressed
std::unordered_map< Addr, TransMapPair > m_outTransAddressed
Definition: AbstractController.hh:232
gem5::ruby::AbstractController::PARAMS
PARAMS(RubyController)
gem5::ruby::Consumer
Definition: Consumer.hh:61
gem5::ruby::AbstractController::wakeup
virtual void wakeup()=0
gem5::ruby::AbstractController::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
A function used to return the port associated with this bus object.
Definition: AbstractController.cc:348
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:246
gem5::ruby::AbstractController::MsgVecType
std::vector< MessageBuffer * > MsgVecType
Definition: AbstractController.hh:354
gem5::ruby::AbstractController::m_is_blocking
bool m_is_blocking
Definition: AbstractController.hh:351
gem5::ruby::AbstractController::allUpstreamDest
const NetDest & allUpstreamDest() const
List of upstream destinations (towards the CPU)
Definition: AbstractController.hh:221
gem5::ruby::AbstractController
Definition: AbstractController.hh:82
gem5::ruby::AbstractController::enqueuePrefetch
virtual void enqueuePrefetch(const Addr &, const RubyRequestType &)
Function for enqueuing a prefetch request.
Definition: AbstractController.hh:143
gem5::ruby::AbstractController::initNetQueues
virtual void initNetQueues()=0
Initialize the message buffers.
gem5::ruby::AbstractController::functionalRead
virtual void functionalRead(const Addr &addr, PacketPtr pkt, WriteMask &mask)
Definition: AbstractController.hh:131
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
packet.hh
gem5::ruby::AbstractController::ControllerStats::delayHistogram
statistics::Histogram delayHistogram
Histogram for profiling delay for the messages this controller cares for.
Definition: AbstractController.hh:438
gem5::ruby::AbstractController::m_waiting_mem_retry
bool m_waiting_mem_retry
Definition: AbstractController.hh:366
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::ruby::AbstractController::m_transitions_per_cycle
const int m_transitions_per_cycle
Definition: AbstractController.hh:362
gem5::ruby::DMASequencer
Definition: DMASequencer.hh:62
gem5::ruby::AbstractController::getDelayVCHist
statistics::Histogram & getDelayVCHist(uint32_t index)
Definition: AbstractController.hh:178
gem5::ruby::AbstractController::addrRanges
const AddrRangeList addrRanges
The address range to which the controller responds on the CPU side.
Definition: AbstractController.hh:406
gem5::ruby::AbstractController::ControllerStats::delayVCHistogram
std::vector< statistics::Histogram * > delayVCHistogram
Definition: AbstractController.hh:439
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2126
gem5::ruby::AbstractController::MemoryPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: AbstractController.cc:450
gem5::ruby::AbstractController::getAddrRanges
const AddrRangeList & getAddrRanges() const
Definition: AbstractController.hh:171
gem5::ruby::AbstractController::collateStats
virtual void collateStats()
Function for collating statistics from all the controllers of this particular type.
Definition: AbstractController.hh:158
gem5::ruby::AbstractController::outgoingTransactionStart
void outgoingTransactionStart(Addr addr, EventType type, bool isAddressed=true)
Profiles an event that initiates a transaction in a peer controller (e.g.
Definition: AbstractController.hh:302
gem5::ruby::AbstractController::functionalMemoryWrite
int functionalMemoryWrite(PacketPtr)
Definition: AbstractController.cc:363
gem5::ruby::AbstractController::incomingTransactionStart
void incomingTransactionStart(Addr addr, EventType type, StateType initialState, bool retried, bool isAddressed=true)
Profiles an event that initiates a protocol transactions for a specific line (e.g.
Definition: AbstractController.hh:252
gem5::ruby::AbstractController::initNetworkPtr
void initNetworkPtr(Network *net_ptr)
Definition: AbstractController.hh:92
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
addr_range_map.hh
gem5::ruby::RejectException
Definition: AbstractController.hh:76
gem5::ruby::AbstractController::ControllerStats::inTransLatTotal
std::vector< statistics::Scalar * > inTransLatTotal
Definition: AbstractController.hh:425
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
DataBlock.hh
gem5::ruby::AbstractController::mapAddressToMachine
MachineID mapAddressToMachine(Addr addr, MachineType mtype) const
Map an address to the correct MachineID.
Definition: AbstractController.cc:411
gem5::ruby::AbstractController::ControllerStats::outTransLatHistRetries
std::vector< statistics::Scalar * > outTransLatHistRetries
Definition: AbstractController.hh:430
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ruby::AbstractController::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: AbstractController.cc:405
gem5::ruby::AbstractController::m_buffer_size
const unsigned int m_buffer_size
Definition: AbstractController.hh:363
gem5::ruby::RejectException::what
virtual const char * what() const
Definition: AbstractController.hh:78
gem5::ruby::AbstractController::ControllerStats::ControllerStats
ControllerStats(statistics::Group *parent)
Definition: AbstractController.cc:464
gem5::ruby::AbstractController::m_cur_in_port
unsigned int m_cur_in_port
Definition: AbstractController.hh:360
gem5::ruby::AbstractController::downstreamDestinations
NetDest downstreamDestinations
Definition: AbstractController.hh:412
gem5::ruby::AbstractController::ControllerStats
Definition: AbstractController.hh:416
gem5::ruby::AbstractController::MemoryPort::MemoryPort
MemoryPort(const std::string &_name, AbstractController *_controller, PortID id=InvalidPortID)
Definition: AbstractController.cc:456
gem5::ruby::AbstractController::AbstractController
AbstractController(const Params &p)
Definition: AbstractController.cc:56
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:465
gem5::ruby::AbstractController::notifyCoalesced
virtual void notifyCoalesced(const Addr &addr, const RubyRequestType &type, const RequestPtr &req, const DataBlock &data_blk, const bool &was_miss)
Notifies controller of a request coalesced at the sequencer.
Definition: AbstractController.hh:148
gem5::ruby::MachineID::getNum
NodeID getNum() const
Definition: MachineID.hh:67
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ruby::AbstractController::SenderState::id
MachineID id
Definition: AbstractController.hh:398
gem5::ruby::AbstractController::incomingTransactionEnd
void incomingTransactionEnd(Addr addr, StateType finalState, bool isAddressed=true)
Profiles an event that ends a transaction.
Definition: AbstractController.hh:275
gem5::ruby::AbstractController::SenderState
Definition: AbstractController.hh:395
gem5::ruby::AbstractController::m_waiting_buffers
WaitingBufType m_waiting_buffers
Definition: AbstractController.hh:357
gem5::ruby::AbstractController::m_machineID
MachineID m_machineID
Definition: AbstractController.hh:344
gem5::ruby::AbstractController::m_version
const NodeID m_version
Definition: AbstractController.hh:343
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::ruby::AbstractController::init
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: AbstractController.cc:77
addr_range.hh
gem5::ruby::NetDest
Definition: NetDest.hh:45
gem5::ruby::AbstractController::unblock
void unblock(Addr)
Definition: AbstractController.cc:333
gem5::ruby::AbstractController::stats
gem5::ruby::AbstractController::ControllerStats stats
gem5::ruby::AbstractController::mandatoryQueueLatency
virtual Cycles mandatoryQueueLatency(const RubyRequestType &param_type)
Definition: AbstractController.hh:119
gem5::ruby::AbstractController::m_outTransUnaddressed
std::unordered_map< Addr, TransMapPair > m_outTransUnaddressed
Definition: AbstractController.hh:235
gem5::ruby::AbstractController::TransMapPair
Definition: AbstractController.hh:230
MessageBuffer.hh
gem5::ruby::AbstractController::getRequestorId
RequestorID getRequestorId() const
Definition: AbstractController.hh:175
gem5::ruby::AbstractController::wakeUpAllBuffers
void wakeUpAllBuffers()
Definition: AbstractController.cc:222
gem5::ruby::AbstractController::functionalReadBuffers
virtual bool functionalReadBuffers(PacketPtr &)=0
These functions are used by ruby system to read/write the data blocks that exist with in the controll...
gem5::ruby::AbstractController::functionalWriteBuffers
virtual int functionalWriteBuffers(PacketPtr &)=0
The return value indicates the number of messages written with the data from the packet.
gem5::ruby::AbstractController::TransMapPair::transaction
unsigned transaction
Definition: AbstractController.hh:230
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ruby::AbstractController::m_in_ports
unsigned int m_in_ports
Definition: AbstractController.hh:359
gem5::ruby::AbstractController::MemoryPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: AbstractController.cc:443
Consumer.hh
Address.hh
gem5::ruby::AbstractController::m_net_ptr
Network * m_net_ptr
Definition: AbstractController.hh:350
gem5::ruby::AbstractController::functionalMemoryRead
void functionalMemoryRead(PacketPtr)
Definition: AbstractController.cc:354
qport.hh
gem5::ruby::AbstractController::getDMASequencer
virtual DMASequencer * getDMASequencer() const =0
clocked_object.hh
gem5::ruby::AbstractController::ControllerStats::inTransLatRetries
std::vector< statistics::Scalar * > inTransLatRetries
Definition: AbstractController.hh:424
gem5::ruby::AbstractController::upstreamDestinations
NetDest upstreamDestinations
Definition: AbstractController.hh:413
gem5::ruby::AbstractController::m_mandatory_queue_latency
const Cycles m_mandatory_queue_latency
Definition: AbstractController.hh:365
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ruby::AbstractController::m_id
const RequestorID m_id
Definition: AbstractController.hh:348
gem5::ruby::NodeID
unsigned int NodeID
Definition: TypeDefines.hh:42
gem5::ruby::AbstractController::AddrMapEntry
std::unordered_map< MachineType, MachineID > AddrMapEntry
Definition: AbstractController.hh:408
gem5::ruby::AbstractController::print
virtual void print(std::ostream &out) const =0
gem5::ruby::AbstractController::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: AbstractController.cc:131
gem5::ruby::AbstractController::MemoryPort::controller
AbstractController * controller
Definition: AbstractController.hh:376
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uint16_t RequestorID
Definition: request.hh:95
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ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::ruby::AbstractController::functionalWrite
virtual int functionalWrite(const Addr &addr, PacketPtr)=0
gem5::ruby::AbstractController::downstreamAddrMap
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Definition: AbstractController.hh:410
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Cycles ticksToCycles(Tick t) const
Definition: clocked_object.hh:222
gem5::ruby::AbstractController::getAccessPermission
virtual AccessPermission getAccessPermission(const Addr &addr)=0
gem5::ruby::AbstractController::memoryPort
MemoryPort memoryPort
Definition: AbstractController.hh:392
gem5::ruby::AbstractController::getMandatoryQueue
virtual MessageBuffer * getMandatoryQueue() const =0
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Definition: DataBlock.hh:60
gem5::ruby::MessageBuffer
Definition: MessageBuffer.hh:74
std::list< AddrRange >
CacheRecorder.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ruby::AbstractController::getMemRespQueue
virtual MessageBuffer * getMemRespQueue() const =0
gem5::ruby::AbstractController::TransMapPair::time
Tick time
Definition: AbstractController.hh:230
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Definition: MachineID.hh:56
gem5::ruby::AbstractController::m_inTransAddressed
std::unordered_map< Addr, TransMapPair > m_inTransAddressed
Definition: AbstractController.hh:231
gem5::ruby::AbstractController::blockOnQueue
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Definition: AbstractController.cc:320
gem5::ruby::AbstractController::recvTimingResp
void recvTimingResp(PacketPtr pkt)
Definition: AbstractController.cc:373
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Definition: CacheRecorder.hh:73
gem5::ruby::AbstractController::functionalRead
virtual void functionalRead(const Addr &addr, PacketPtr)
Definition: AbstractController.hh:125
callback.hh
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Definition: GPUCoalescer.hh:213
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const std::string _name
Definition: named.hh:41
gem5::ruby::AbstractController::respondsTo
bool respondsTo(Addr addr)
Definition: AbstractController.hh:181
gem5::ruby::AbstractController::wakeUpBuffer
void wakeUpBuffer(MessageBuffer *buf, Addr addr)
Definition: AbstractController.cc:159
gem5::ruby::AbstractController::allDownstreamDest
const NetDest & allDownstreamDest() const
List of downstream destinations (towards memory)
Definition: AbstractController.hh:218
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#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
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Definition: types.hh:84
gem5::ruby::AbstractController::stallBuffer
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Definition: AbstractController.cc:145
gem5::ruby::AbstractController::getCPUSequencer
virtual Sequencer * getCPUSequencer() const =0

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