gem5 v24.1.0.1
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AbstractController.hh
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1/*
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14 * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
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40
41#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
42#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
43
44#include <exception>
45#include <iostream>
46#include <string>
47#include <unordered_map>
48
49#include "base/addr_range.hh"
51#include "base/callback.hh"
52#include "mem/packet.hh"
53#include "mem/qport.hh"
60#include "mem/ruby/protocol/AccessPermission.hh"
62#include "params/RubyController.hh"
63#include "sim/clocked_object.hh"
64#include "sim/eventq.hh"
65
66namespace gem5
67{
68
69namespace ruby
70{
71
72class Network;
73class GPUCoalescer;
74class DMASequencer;
75class RubySystem;
76
77// used to communicate that an in_port peeked the wrong message type
78class RejectException: public std::exception
79{
80 virtual const char* what() const throw()
81 { return "Port rejected message based on type"; }
82};
83
85{
86 public:
87 PARAMS(RubyController);
89 void init();
90
91 NodeID getVersion() const { return m_machineID.getNum(); }
92 MachineType getType() const { return m_machineID.getType(); }
93
94 void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
95
96 // return instance name
98 bool isBlocked(Addr) const;
99 void unblock(Addr);
100 bool isBlocked(Addr);
101
102 virtual MessageBuffer* getMandatoryQueue() const = 0;
103 virtual MessageBuffer* getMemReqQueue() const = 0;
104 virtual MessageBuffer* getMemRespQueue() const = 0;
105
106 // That function must be called by controller when dequeuing mem resp queue
107 // for memory controller to receive the retry request in time
109 // Or that function can be called to perform both dequeue and notification
110 // at once.
111 void dequeueMemRespQueue();
112
113 virtual AccessPermission getAccessPermission(const Addr &addr) = 0;
114
115 virtual void print(std::ostream & out) const = 0;
116 virtual void wakeup() = 0;
117 virtual void resetStats() = 0;
118 virtual void regStats();
119
120 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
121 virtual Sequencer* getCPUSequencer() const = 0;
122 virtual DMASequencer* getDMASequencer() const = 0;
123 virtual GPUCoalescer* getGPUCoalescer() const = 0;
124
125 // This latency is used by the sequencer when enqueueing requests.
126 // Different latencies may be used depending on the request type.
127 // This is the hit latency unless the top-level cache controller
128 // introduces additional cycles in the response path.
129 virtual Cycles mandatoryQueueLatency(const RubyRequestType& param_type)
130 { return m_mandatory_queue_latency; }
131
135 virtual void functionalRead(const Addr &addr, PacketPtr)
136 { panic("functionalRead(Addr,PacketPtr) not implemented"); }
144 virtual int functionalReadPriority() { return -1; }
145
149 virtual void functionalRead(const Addr &addr, PacketPtr pkt,
151 { panic("functionalRead(Addr,PacketPtr,WriteMask) not implemented"); }
152
157 virtual int functionalWrite(const Addr &addr, PacketPtr) = 0;
159
161 virtual void enqueuePrefetch(const Addr &, const RubyRequestType&)
162 { fatal("Prefetches not implemented!");}
163
166 virtual void notifyCoalesced(const Addr& addr,
167 const RubyRequestType& type,
168 const RequestPtr& req,
169 const DataBlock& data_blk,
170 const bool& was_miss)
171 { }
172
176 virtual void collateStats()
177 {fatal("collateStats() should be overridden!");}
178
180 virtual void initNetQueues() = 0;
181
183 Port &getPort(const std::string &if_name,
185
186 bool recvTimingResp(PacketPtr pkt);
188
189 const AddrRangeList &getAddrRanges() const { return addrRanges; }
190
191 public:
193 RequestorID getRequestorId() const { return m_id; }
194
198
200 {
201 for (auto &range: addrRanges)
202 if (range.contains(addr)) return true;
203 return false;
204 }
205
219 MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
220
233 MachineType mtype = MachineType_NUM) const;
234
237
240
241 // Helper methods for commonly used functions called in common/address.hh
242 Addr getOffset(Addr addr) const;
244 std::string printAddress(Addr addr) const;
245
246 protected:
248 void profileRequest(const std::string &request);
250 void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
251
252 // Tracks outstanding transactions for latency profiling
253 struct TransMapPair { unsigned transaction; unsigned state; Tick time; };
254 std::unordered_map<Addr, TransMapPair> m_inTransAddressed;
255 std::unordered_map<Addr, TransMapPair> m_outTransAddressed;
256
257 std::unordered_map<Addr, TransMapPair> m_inTransUnaddressed;
258 std::unordered_map<Addr, TransMapPair> m_outTransUnaddressed;
259
274 template<typename EventType, typename StateType>
276 EventType type, StateType initialState, bool retried,
277 bool isAddressed=true)
278 {
279 auto& m_inTrans =
281 assert(m_inTrans.find(addr) == m_inTrans.end());
282 m_inTrans[addr] = {type, initialState, curTick()};
283 if (retried)
285 }
286
297 template<typename StateType>
298 void incomingTransactionEnd(Addr addr, StateType finalState,
299 bool isAddressed=true)
300 {
301 auto& m_inTrans =
303 auto iter = m_inTrans.find(addr);
304 assert(iter != m_inTrans.end());
305 auto &trans = iter->second;
306
307 auto stat_iter_ev = stats.inTransStateChanges.find(trans.transaction);
308 gem5_assert(stat_iter_ev != stats.inTransStateChanges.end(),
309 "%s: event type=%d not marked as in_trans in SLICC",
310 name(), trans.transaction);
311
312 auto stat_iter_state = stat_iter_ev->second.find(trans.state);
313 gem5_assert(stat_iter_state != stat_iter_ev->second.end(),
314 "%s: event type=%d has no transition from state=%d",
315 name(), trans.transaction, trans.state);
316
317 ++(*stat_iter_state->second[(unsigned)finalState]);
318
319 stats.inTransLatHist[iter->second.transaction]->sample(
320 ticksToCycles(curTick() - trans.time));
321
322 m_inTrans.erase(iter);
323 }
324
336 template<typename EventType>
338 bool isAddressed=true)
339 {
340 auto& m_outTrans =
342 assert(m_outTrans.find(addr) == m_outTrans.end());
343 m_outTrans[addr] = {type, 0, curTick()};
344 }
345
356 void outgoingTransactionEnd(Addr addr, bool retried,
357 bool isAddressed=true)
358 {
359 auto& m_outTrans =
361 auto iter = m_outTrans.find(addr);
362 assert(iter != m_outTrans.end());
363 auto &trans = iter->second;
364
365 auto stat_iter = stats.outTransLatHist.find(trans.transaction);
366 gem5_assert(stat_iter != stats.outTransLatHist.end(),
367 "%s: event type=%d not marked as out_trans in SLICC",
368 name(), trans.transaction);
369
370 stat_iter->second->sample(
371 ticksToCycles(curTick() - trans.time));
372 if (retried)
373 ++(*stats.outTransRetryCnt[trans.transaction]);
374 m_outTrans.erase(iter);
375 }
376
379 void wakeUpBuffers(Addr addr);
381 void wakeUpAllBuffers();
382 bool serviceMemoryQueue();
383
388 virtual bool inCache(const Addr &addr, const bool &is_secure)
389 { fatal("inCache: prefetching not supported"); return false; }
390
391 virtual bool hasBeenPrefetched(const Addr &addr, const bool &is_secure)
392 { fatal("hasBeenPrefetched: prefetching not supported"); return false; }
393
394 virtual bool hasBeenPrefetched(const Addr &addr, const bool &is_secure,
395 const RequestorID &requestor)
396 { fatal("hasBeenPrefetched: prefetching not supported"); return false; }
397
398 virtual bool inMissQueue(const Addr &addr, const bool &is_secure)
399 { fatal("inMissQueue: prefetching not supported"); return false; }
400
401 virtual bool coalesce()
402 { fatal("coalesce: prefetching not supported"); return false; }
403
405
406 protected:
410
411 // RequestorID used by some components of gem5.
413
416 std::map<Addr, MessageBuffer*> m_block_map;
417
419 typedef std::set<MessageBuffer*> MsgBufType;
420 typedef std::map<Addr, MsgVecType* > WaitingBufType;
422
423 unsigned int m_in_ports;
424 unsigned int m_cur_in_port;
427 const unsigned int m_buffer_size;
432
437 class MemoryPort : public RequestPort
438 {
439 private:
440 // Controller that operates this port.
442
443 public:
444 MemoryPort(const std::string &_name, AbstractController *_controller,
445 PortID id = InvalidPortID);
446
447 protected:
448 // Function for receiving a timing response from the peer port.
449 // Currently the pkt is handed to the coherence controller
450 // associated with this port.
451 bool recvTimingResp(PacketPtr pkt);
452
453 void recvReqRetry();
454 };
455
456 /* Request port to the memory controller. */
458
459 // State that is stored in packets sent to the memory controller.
461 {
462 // Id of the machine from which the request originated.
464
466 {}
467 };
468
470
471 // Formerly in RubySlicc_ComponentMapping.hh. Moved here to access
472 // RubySystem pointer.
473 NetDest broadcast(MachineType type);
474 int machineCount(MachineType machType);
475
476 private:
479
480 std::unordered_map<MachineType, AddrRangeMap<MachineID, 3>>
482
485
486 void sendRetryRespToMem();
488
489 public:
491 {
493
494 // Initialized by the SLICC compiler for all events with the
495 // "in_trans" property.
496 // Only histograms with samples will appear in the stats
497 std::unordered_map<unsigned, statistics::Histogram*> inTransLatHist;
498 std::unordered_map<unsigned, statistics::Scalar*> inTransRetryCnt;
499 // Initialized by the SLICC compiler for all combinations of events
500 // with the "in_trans" property, potential initial states, and
501 // potential final states. Potential initial states are states that
502 // appear in transitions triggered by that event. Currently all states
503 // are considered as potential final states.
504 std::unordered_map<unsigned, std::unordered_map<unsigned,
506
507 // Initialized by the SLICC compiler for all events with the
508 // "out_trans" property.
509 // Only histograms with samples will appear in the stats.
510 std::unordered_map<unsigned, statistics::Histogram*> outTransLatHist;
511 std::unordered_map<unsigned, statistics::Scalar*>
513
517
523
524};
525
526} // namespace ruby
527} // namespace gem5
528
529#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
ClockedObjectParams Params
Parameters of ClockedObject.
Cycles ticksToCycles(Tick t) const
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
Wrap a member function inside MemberEventWrapper to use it as an event callback.
Definition eventq.hh:1092
const std::string _name
Definition named.hh:41
virtual std::string name() const
Definition named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Ports are used to interface objects to each other.
Definition port.hh:62
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition port.hh:136
Port that forwards requests and receives responses from the memory controller.
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
void initNetworkPtr(Network *net_ptr)
std::vector< MessageBuffer * > MsgVecType
void profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
Profiles the delay associated with messages.
std::map< Addr, MsgVecType * > WaitingBufType
virtual void initNetQueues()=0
Initialize the message buffers.
virtual void notifyCoalesced(const Addr &addr, const RubyRequestType &type, const RequestPtr &req, const DataBlock &data_blk, const bool &was_miss)
Notifies controller of a request coalesced at the sequencer.
void wakeUpBuffer(MessageBuffer *buf, Addr addr)
statistics::Histogram & getDelayVCHist(uint32_t index)
virtual void regStats()
Callback to set stat parameters.
virtual void print(std::ostream &out) const =0
const NetDest & allUpstreamDest() const
List of upstream destinations (towards the CPU)
std::unordered_map< Addr, TransMapPair > m_outTransAddressed
void incomingTransactionStart(Addr addr, EventType type, StateType initialState, bool retried, bool isAddressed=true)
Profiles an event that initiates a protocol transactions for a specific line (e.g.
virtual Cycles mandatoryQueueLatency(const RubyRequestType &param_type)
const AddrRangeList addrRanges
The address range to which the controller responds on the CPU side.
std::unordered_map< MachineType, AddrRangeMap< MachineID, 3 > > downstreamAddrMap
virtual AccessPermission getAccessPermission(const Addr &addr)=0
const AddrRangeList & getAddrRanges() const
virtual MessageBuffer * getMemReqQueue() const =0
std::set< MessageBuffer * > MsgBufType
virtual DMASequencer * getDMASequencer() const =0
virtual int functionalWrite(const Addr &addr, PacketPtr)=0
virtual void recordCacheTrace(int cntrl, CacheRecorder *tr)=0
virtual bool functionalReadBuffers(PacketPtr &)=0
These functions are used by ruby system to read/write the data blocks that exist with in the controll...
const NetDest & allDownstreamDest() const
List of downstream destinations (towards memory)
virtual bool hasBeenPrefetched(const Addr &addr, const bool &is_secure, const RequestorID &requestor)
void outgoingTransactionStart(Addr addr, EventType type, bool isAddressed=true)
Profiles an event that initiates a transaction in a peer controller (e.g.
MachineID mapAddressToDownstreamMachine(Addr addr, MachineType mtype=MachineType_NUM) const
Maps an address to the correct dowstream MachineID (i.e.
virtual void enqueuePrefetch(const Addr &, const RubyRequestType &)
Function for enqueuing a prefetch request.
virtual void collateStats()
Function for collating statistics from all the controllers of this particular type.
NetDest broadcast(MachineType type)
virtual MessageBuffer * getMemRespQueue() const =0
virtual int functionalReadPriority()
Returns the priority used by functional reads when deciding from which controller to read a Maybe_Sta...
virtual bool functionalReadBuffers(PacketPtr &, WriteMask &mask)=0
Functional read that reads only blocks not present in the mask.
virtual void functionalRead(const Addr &addr, PacketPtr)
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
MemberEventWrapper<&AbstractController::sendRetryRespToMem > mRetryRespEvent
std::unordered_map< Addr, TransMapPair > m_inTransAddressed
virtual Sequencer * getCPUSequencer() const =0
std::unordered_map< Addr, TransMapPair > m_inTransUnaddressed
virtual void resetStats()=0
Callback to reset stats.
virtual void functionalRead(const Addr &addr, PacketPtr pkt, WriteMask &mask)
void blockOnQueue(Addr, MessageBuffer *)
MachineID mapAddressToMachine(Addr addr, MachineType mtype) const
Map an address to the correct MachineID.
virtual bool inCache(const Addr &addr, const bool &is_secure)
Functions needed by CacheAccessor.
virtual MessageBuffer * getMandatoryQueue() const =0
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
A function used to return the port associated with this bus object.
virtual bool inMissQueue(const Addr &addr, const bool &is_secure)
void outgoingTransactionEnd(Addr addr, bool retried, bool isAddressed=true)
Profiles the end of an outgoing transaction.
gem5::ruby::AbstractController::ControllerStats stats
virtual GPUCoalescer * getGPUCoalescer() const =0
void profileRequest(const std::string &request)
Profiles original cache requests including PUTs.
void incomingTransactionEnd(Addr addr, StateType finalState, bool isAddressed=true)
Profiles an event that ends a transaction.
std::unordered_map< Addr, TransMapPair > m_outTransUnaddressed
std::map< Addr, MessageBuffer * > m_block_map
Addr makeLineAddress(Addr addr) const
statistics::Histogram & getDelayHist()
int machineCount(MachineType machType)
virtual bool hasBeenPrefetched(const Addr &addr, const bool &is_secure)
void stallBuffer(MessageBuffer *buf, Addr addr)
virtual int functionalWriteBuffers(PacketPtr &)=0
The return value indicates the number of messages written with the data from the packet.
std::string printAddress(Addr addr) const
virtual const char * what() const
This is a proxy for prefetcher class in classic memory.
Statistics container.
Definition group.hh:93
A simple histogram stat.
This is a simple scalar statistic, like a counter.
STL vector class.
Definition stl.hh:37
ClockedObject declaration and implementation.
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
#define gem5_assert(cond,...)
The assert macro will function like a normal assert, but will use panic instead of straight abort().
Definition logging.hh:317
#define fatal(...)
This implements a cprintf based fatal() function.
Definition logging.hh:200
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
Bitfield< 30, 0 > index
Bitfield< 0 > p
Bitfield< 3 > addr
Definition types.hh:84
unsigned int NodeID
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
std::shared_ptr< Request > RequestPtr
Definition request.hh:94
const PortID InvalidPortID
Definition types.hh:246
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
uint64_t Tick
Tick count type.
Definition types.hh:58
uint16_t RequestorID
Definition request.hh:95
Declaration of the Packet class.
Declaration of the queued port.
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition packet.hh:469
std::unordered_map< unsigned, statistics::Histogram * > outTransLatHist
statistics::Scalar fullyBusyCycles
Counter for the number of cycles when the transitions carried out were equal to the maximum allowed.
std::unordered_map< unsigned, statistics::Scalar * > outTransRetryCnt
std::unordered_map< unsigned, std::unordered_map< unsigned, std::vector< statistics::Scalar * > > > inTransStateChanges
statistics::Histogram delayHistogram
Histogram for profiling delay for the messages this controller cares for.
std::unordered_map< unsigned, statistics::Scalar * > inTransRetryCnt
std::vector< statistics::Histogram * > delayVCHistogram
std::unordered_map< unsigned, statistics::Histogram * > inTransLatHist
MachineType getType() const
Definition MachineID.hh:66
NodeID getNum() const
Definition MachineID.hh:67

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