gem5  v22.0.0.1
Namespaces | Functions | Variables
misc.cc File Reference
#include "arch/arm/regs/misc.hh"
#include <tuple>
#include "arch/arm/isa.hh"
#include "base/logging.hh"
#include "cpu/thread_context.hh"
#include "sim/full_system.hh"

Go to the source code of this file.

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 
 gem5::ArmISA
 

Functions

MiscRegIndex gem5::ArmISA::decodeCP14Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex gem5::ArmISA::decodeCP15Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex gem5::ArmISA::decodeCP15Reg64 (unsigned crm, unsigned opc1)
 
std::tuple< bool, bool > gem5::ArmISA::canReadCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 Check for permission to read coprocessor registers. More...
 
std::tuple< bool, bool > gem5::ArmISA::canWriteCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 Check for permission to write coprocessor registers. More...
 
bool gem5::ArmISA::AArch32isUndefinedGenericTimer (MiscRegIndex reg, ThreadContext *tc)
 
int gem5::ArmISA::snsBankedIndex (MiscRegIndex reg, ThreadContext *tc)
 
int gem5::ArmISA::snsBankedIndex (MiscRegIndex reg, ThreadContext *tc, bool ns)
 
int gem5::ArmISA::snsBankedIndex64 (MiscRegIndex reg, ThreadContext *tc)
 
void gem5::ArmISA::preUnflattenMiscReg ()
 
int gem5::ArmISA::unflattenMiscReg (int reg)
 
bool gem5::ArmISA::canReadAArch64SysReg (MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
 
bool gem5::ArmISA::canWriteAArch64SysReg (MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
 
MiscRegIndex gem5::ArmISA::decodeAArch64SysReg (unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
 
MiscRegNum64 gem5::ArmISA::encodeAArch64SysReg (MiscRegIndex misc_reg)
 

Variables

int gem5::ArmISA::unflattenResultMiscReg [NUM_MISCREGS]
 If the reg is a child reg of a banked set, then the parent is the last banked one in the list. More...
 
std::bitset< NUM_MISCREG_INFOS > gem5::ArmISA::miscRegInfo [NUM_MISCREGS]
 

Generated on Sat Jun 18 2022 08:12:43 for gem5 by doxygen 1.8.17