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| MiscRegIndex | gem5::ArmISA::decodeCP14Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) |
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| MiscRegIndex | gem5::ArmISA::decodeCP15Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) |
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| MiscRegIndex | gem5::ArmISA::decodeCP15Reg64 (unsigned crm, unsigned opc1) |
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| std::tuple< bool, bool > | gem5::ArmISA::canReadCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) |
| | Check for permission to read coprocessor registers.
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| std::tuple< bool, bool > | gem5::ArmISA::canWriteCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) |
| | Check for permission to write coprocessor registers.
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| bool | gem5::ArmISA::AArch32isUndefinedGenericTimer (MiscRegIndex reg, ThreadContext *tc) |
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| int | gem5::ArmISA::snsBankedIndex (MiscRegIndex reg, ThreadContext *tc) |
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| int | gem5::ArmISA::snsBankedIndex (MiscRegIndex reg, ThreadContext *tc, bool ns) |
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| int | gem5::ArmISA::snsBankedIndex64 (MiscRegIndex reg, ThreadContext *tc) |
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| void | gem5::ArmISA::preUnflattenMiscReg () |
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| int | gem5::ArmISA::unflattenMiscReg (int reg) |
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| Fault | gem5::ArmISA::checkFaultAccessAArch64SysReg (MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst) |
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| MiscRegIndex | gem5::ArmISA::decodeAArch64SysReg (unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2) |
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| MiscRegIndex | gem5::ArmISA::decodeAArch64SysReg (const MiscRegNum64 &sys_reg) |
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| std::optional< MiscRegNum64 > | gem5::ArmISA::encodeAArch64SysReg (MiscRegIndex misc_reg) |
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| static Fault | gem5::ArmISA::defaultFaultE2H_EL2 (const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst) |
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| static Fault | gem5::ArmISA::defaultFaultE2H_EL3 (const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst) |
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| static CPSR | gem5::ArmISA::resetCPSR (ArmSystem *system) |
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