misc.cc File Reference

#include "arch/arm/regs/misc.hh"
#include <tuple>
#include "arch/arm/insts/misc64.hh"
#include "arch/arm/isa.hh"
#include "base/logging.hh"
#include "cpu/thread_context.hh"
#include "dev/arm/gic_v3_cpu_interface.hh"
#include "sim/full_system.hh"

Go to the source code of this file.

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::ArmISA

Macros
#define	HCR_TRAP(bitfield)

Functions
MiscRegIndex	gem5::ArmISA::decodeCP14Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
MiscRegIndex	gem5::ArmISA::decodeCP15Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
MiscRegIndex	gem5::ArmISA::decodeCP15Reg64 (unsigned crm, unsigned opc1)
std::tuple< bool, bool >	gem5::ArmISA::canReadCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
	Check for permission to read coprocessor registers. More...
std::tuple< bool, bool >	gem5::ArmISA::canWriteCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
	Check for permission to write coprocessor registers. More...
bool	gem5::ArmISA::AArch32isUndefinedGenericTimer (MiscRegIndex reg, ThreadContext *tc)
int	gem5::ArmISA::snsBankedIndex (MiscRegIndex reg, ThreadContext *tc)
int	gem5::ArmISA::snsBankedIndex (MiscRegIndex reg, ThreadContext *tc, bool ns)
int	gem5::ArmISA::snsBankedIndex64 (MiscRegIndex reg, ThreadContext *tc)
void	gem5::ArmISA::preUnflattenMiscReg ()
int	gem5::ArmISA::unflattenMiscReg (int reg)
Fault	gem5::ArmISA::checkFaultAccessAArch64SysReg (MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
MiscRegIndex	gem5::ArmISA::decodeAArch64SysReg (unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
MiscRegIndex	gem5::ArmISA::decodeAArch64SysReg (const MiscRegNum64 &sys_reg)
MiscRegNum64	gem5::ArmISA::encodeAArch64SysReg (MiscRegIndex misc_reg)
static Fault	gem5::ArmISA::defaultFaultE2H_EL2 (const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
static Fault	gem5::ArmISA::defaultFaultE2H_EL3 (const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)

Variables
int	gem5::ArmISA::unflattenResultMiscReg [NUM_MISCREGS]
	If the reg is a child reg of a banked set, then the parent is the last banked one in the list. More...
std::vector< struct MiscRegLUTEntry >	gem5::ArmISA::lookUpMiscReg (NUM_MISCREGS)

Macro Definition Documentation

HCR_TRAP

#define HCR_TRAP

(

bitfield

)

Value:

    [] (const MiscRegLUTEntry &entry, \
    ThreadContext *tc, const MiscRegOp64 &inst) -> Fault     \
{                                                            \
    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);        \
    if (EL2Enabled(tc) && hcr.bitfield) {                    \
        return inst.generateTrap(EL2);                       \
    } else {                                                 \
        return NoFault;                                      \
    }                                                        \
}

Definition at line 1709 of file misc.cc.