gem5  v22.0.0.2
gic_v3_cpu_interface.hh
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40 
41 #ifndef __DEV_ARM_GICV3_CPU_INTERFACE_H__
42 #define __DEV_ARM_GICV3_CPU_INTERFACE_H__
43 
44 #include "arch/arm/isa_device.hh"
45 #include "dev/arm/gic_v3.hh"
46 
47 namespace gem5
48 {
49 
50 class Gicv3Distributor;
51 class Gicv3Redistributor;
52 
53 namespace ArmISA
54 {
55 class ISA;
56 }
57 
59 {
60  private:
61 
62  friend class Gicv3Distributor;
63  friend class Gicv3Redistributor;
64  friend class ArmISA::ISA;
65 
66  protected:
67 
71  uint32_t cpuId;
72 
74 
75  BitUnion64(ICC_CTLR_EL1)
76  Bitfield<63, 20> res0_3;
77  Bitfield<19> ExtRange;
78  Bitfield<18> RSS;
79  Bitfield<17, 16> res0_2;
80  Bitfield<15> A3V;
81  Bitfield<14> SEIS;
82  Bitfield<13, 11> IDbits;
83  Bitfield<10, 8> PRIbits;
84  Bitfield<7> res0_1;
85  Bitfield<6> PMHE;
86  Bitfield<5, 2> res0_0;
87  Bitfield<1> EOImode;
88  Bitfield<0> CBPR;
89  EndBitUnion(ICC_CTLR_EL1)
90 
91  BitUnion64(ICC_CTLR_EL3)
92  Bitfield<63, 20> res0_2;
93  Bitfield<19> ExtRange;
94  Bitfield<18> RSS;
95  Bitfield<17> nDS;
96  Bitfield<16> res0_1;
97  Bitfield<15> A3V;
98  Bitfield<14> SEIS;
99  Bitfield<13, 11> IDbits;
100  Bitfield<10, 8> PRIbits;
101  Bitfield<7> res0_0;
102  Bitfield<6> PMHE;
103  Bitfield<5> RM;
104  Bitfield<4> EOImode_EL1NS;
105  Bitfield<3> EOImode_EL1S;
106  Bitfield<2> EOImode_EL3;
107  Bitfield<1> CBPR_EL1NS;
108  Bitfield<0> CBPR_EL1S;
109  EndBitUnion(ICC_CTLR_EL3)
110 
111  BitUnion64(ICC_IGRPEN0_EL1)
112  Bitfield<63, 1> res0;
113  Bitfield<0> Enable;
114  EndBitUnion(ICC_IGRPEN0_EL1)
115 
116  BitUnion64(ICC_IGRPEN1_EL1)
117  Bitfield<63, 1> res0;
118  Bitfield<0> Enable;
119  EndBitUnion(ICC_IGRPEN1_EL1)
120 
121  BitUnion64(ICC_IGRPEN1_EL3)
122  Bitfield<63, 2> res0;
123  Bitfield<1> EnableGrp1S;
124  Bitfield<0> EnableGrp1NS;
125  EndBitUnion(ICC_IGRPEN1_EL3)
126 
127  BitUnion64(ICC_SRE_EL1)
128  Bitfield<63, 3> res0;
129  Bitfield<2> DIB;
130  Bitfield<1> DFB;
131  Bitfield<0> SRE;
132  EndBitUnion(ICC_SRE_EL1)
133 
134  BitUnion64(ICC_SRE_EL2)
135  Bitfield<63, 4> res0;
136  Bitfield<3> Enable;
137  Bitfield<2> DIB;
138  Bitfield<1> DFB;
139  Bitfield<0> SRE;
140  EndBitUnion(ICC_SRE_EL2)
141 
142  BitUnion64(ICC_SRE_EL3)
143  Bitfield<63, 4> res0;
144  Bitfield<3> Enable;
145  Bitfield<2> DIB;
146  Bitfield<1> DFB;
147  Bitfield<0> SRE;
148  EndBitUnion(ICC_SRE_EL3)
149 
150  static const uint8_t PRIORITY_BITS = 5;
151 
152  // Minimum BPR for Secure, or when security not enabled
153  static const uint8_t GIC_MIN_BPR = 2;
154  // Minimum BPR for Nonsecure when security is enabled
155  static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1;
156 
157  static const uint8_t VIRTUAL_PRIORITY_BITS = 5;
158  static const uint8_t VIRTUAL_PREEMPTION_BITS = 5;
159  static const uint8_t VIRTUAL_NUM_LIST_REGS = 16;
160 
161  static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS;
162 
163  struct hppi_t
164  {
165  uint32_t intid;
166  uint8_t prio;
168  };
169 
171 
172  // GIC CPU interface memory mapped control registers (legacy)
173  enum
174  {
175  GICC_CTLR = 0x0000,
176  GICC_PMR = 0x0004,
177  GICC_BPR = 0x0008,
178  GICC_IAR = 0x000C,
179  GICC_EOIR = 0x0010,
180  GICC_RPR = 0x0014,
181  GICC_HPPI = 0x0018,
182  GICC_ABPR = 0x001C,
183  GICC_AIAR = 0x0020,
184  GICC_AEOIR = 0x0024,
185  GICC_AHPPIR = 0x0028,
186  GICC_STATUSR = 0x002C,
187  GICC_IIDR = 0x00FC,
188  };
189 
190  static const AddrRange GICC_APR;
191  static const AddrRange GICC_NSAPR;
192 
193  // GIC CPU virtual interface memory mapped control registers (legacy)
194  enum
195  {
196  GICH_HCR = 0x0000,
197  GICH_VTR = 0x0004,
198  GICH_VMCR = 0x0008,
199  GICH_MISR = 0x0010,
200  GICH_EISR = 0x0020,
201  GICH_ELRSR = 0x0030,
202  };
203 
204  static const AddrRange GICH_APR;
205  static const AddrRange GICH_LR;
206 
207  BitUnion64(ICH_HCR_EL2)
208  Bitfield<63, 32> res0_2;
209  Bitfield<31, 27> EOIcount;
210  Bitfield<26, 15> res0_1;
211  Bitfield<14> TDIR;
212  Bitfield<13> TSEI;
213  Bitfield<12> TALL1;
214  Bitfield<11> TALL0;
215  Bitfield<10> TC;
216  Bitfield<9, 8> res0_0;
217  Bitfield<7> VGrp1DIE;
218  Bitfield<6> VGrp1EIE;
219  Bitfield<5> VGrp0DIE;
220  Bitfield<4> VGrp0EIE;
221  Bitfield<3> NPIE;
222  Bitfield<2> LRENPIE;
223  Bitfield<1> UIE;
224  Bitfield<0> En;
225  EndBitUnion(ICH_HCR_EL2)
226 
227  BitUnion64(ICH_LR_EL2)
228  Bitfield<63, 62> State;
229  Bitfield<61> HW;
230  Bitfield<60> Group;
231  Bitfield<59, 56> res0_1;
232  Bitfield<55, 48> Priority;
233  Bitfield<47, 45> res0_0;
234  Bitfield<44, 32> pINTID;
235  Bitfield<41> EOI;
236  Bitfield<31, 0> vINTID;
237  EndBitUnion(ICH_LR_EL2)
238 
239  static const uint64_t ICH_LR_EL2_STATE_INVALID = 0;
240  static const uint64_t ICH_LR_EL2_STATE_PENDING = 1;
241  static const uint64_t ICH_LR_EL2_STATE_ACTIVE = 2;
242  static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3;
243 
244  BitUnion32(ICH_LRC)
245  Bitfield<31, 30> State;
246  Bitfield<29> HW;
247  Bitfield<28> Group;
248  Bitfield<27, 24> res0_1;
249  Bitfield<23, 16> Priority;
250  Bitfield<15, 13> res0_0;
251  Bitfield<12, 0> pINTID;
252  Bitfield<9> EOI;
253  EndBitUnion(ICH_LRC)
254 
255  BitUnion64(ICH_MISR_EL2)
256  Bitfield<63, 8> res0;
257  Bitfield<7> VGrp1D;
258  Bitfield<6> VGrp1E;
259  Bitfield<5> VGrp0D;
260  Bitfield<4> VGrp0E;
261  Bitfield<3> NP;
262  Bitfield<2> LRENP;
263  Bitfield<1> U;
264  Bitfield<0> EOI;
265  EndBitUnion(ICH_MISR_EL2)
266 
267  BitUnion64(ICH_VMCR_EL2)
268  Bitfield<63, 32> res0_2;
269  Bitfield<31, 24> VPMR;
270  Bitfield<23, 21> VBPR0;
271  Bitfield<20, 18> VBPR1;
272  Bitfield<17, 10> res0_1;
273  Bitfield<9> VEOIM;
274  Bitfield<8, 5> res0_0;
275  Bitfield<4> VCBPR;
276  Bitfield<3> VFIQEn;
277  Bitfield<2> VAckCtl;
278  Bitfield<1> VENG1;
279  Bitfield<0> VENG0;
280  EndBitUnion(ICH_VMCR_EL2)
281 
282  BitUnion64(ICH_VTR_EL2)
283  Bitfield<63, 32> res0_1;
284  Bitfield<31, 29> PRIbits;
285  Bitfield<28, 26> PREbits;
286  Bitfield<25, 23> IDbits;
287  Bitfield<22> SEIS;
288  Bitfield<21> A3V;
289  Bitfield<20> res1;
290  Bitfield<19> TDS;
291  Bitfield<18, 5> res0_0;
292  Bitfield<4, 0> ListRegs;
293  EndBitUnion(ICH_VTR_EL2)
294 
295  BitUnion64(ICV_CTLR_EL1)
296  Bitfield<63, 19> res0_2;
297  Bitfield<18> RSS;
298  Bitfield<17, 16> res0_1;
299  Bitfield<15> A3V;
300  Bitfield<14> SEIS;
301  Bitfield<13, 11> IDbits;
302  Bitfield<10, 8> PRIbits;
303  Bitfield<7, 2> res0_0;
304  Bitfield<1> EOImode;
305  Bitfield<0> CBPR;
306  EndBitUnion(ICV_CTLR_EL1)
307 
308  protected:
309 
310  void activateIRQ(uint32_t intid, Gicv3::GroupId group);
311  void generateSGI(RegVal val, Gicv3::GroupId group);
312  ArmISA::ExceptionLevel currEL() const;
313  void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
314  void dropPriority(Gicv3::GroupId group);
315  uint64_t eoiMaintenanceInterruptStatus() const;
316  bool getHCREL2FMO() const;
317  bool getHCREL2IMO() const;
318  uint32_t getHPPIR0() const;
319  uint32_t getHPPIR1() const;
320  int getHPPVILR() const;
321  bool groupEnabled(Gicv3::GroupId group) const;
322  uint32_t groupPriorityMask(Gicv3::GroupId group);
323  bool haveEL(ArmISA::ExceptionLevel el) const;
324  int highestActiveGroup() const;
325  uint8_t highestActivePriority() const;
326  bool hppiCanPreempt();
327  bool hppviCanPreempt(int lrIdx) const;
328  bool inSecureState() const;
329  ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
330  bool isAA64() const;
331  bool isEL3OrMon() const;
332  bool isEOISplitMode() const;
333  bool isSecureBelowEL3() const;
334  ICH_MISR_EL2 maintenanceInterruptStatus() const;
335  void resetHppi(uint32_t intid);
336  void serialize(CheckpointOut & cp) const override;
337  void unserialize(CheckpointIn & cp) override;
338  void update();
339  void updateDistributor();
340  void virtualActivateIRQ(uint32_t lrIdx);
341  void virtualDeactivateIRQ(int lrIdx);
342  uint8_t virtualDropPriority();
343  int virtualFindActive(uint32_t intid) const;
344  uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
345  uint8_t virtualHighestActivePriority() const;
347  bool virtualIsEOISplitMode() const;
348  void virtualUpdate();
349  RegVal bpr1(Gicv3::GroupId group);
350  bool havePendingInterrupts(void) const;
351  void clearPendingInterrupts(void);
352  void assertWakeRequest(void);
353  void deassertWakeRequest(void);
354 
355  RegVal readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) const;
356  void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
357  public:
358 
359  Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
360 
361  void init();
362 
363  public:
364  void copy(Gicv3Registers *from, Gicv3Registers *to);
365 
366  public: // BaseISADevice
367  RegVal readMiscReg(int misc_reg) override;
368  void setMiscReg(int misc_reg, RegVal val) override;
369  void setThreadContext(ThreadContext *tc) override;
370 };
371 
372 } // namespace gem5
373 
374 #endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__
isa_device.hh
gem5::Gicv3::GroupId
GroupId
Definition: gic_v3.hh:133
gem5::Gicv3CPUInterface::ExtRange
Bitfield< 19 > ExtRange
Definition: gic_v3_cpu_interface.hh:77
gem5::Gicv3CPUInterface::groupEnabled
bool groupEnabled(Gicv3::GroupId group) const
Definition: gic_v3_cpu_interface.cc:2313
gem5::Gicv3CPUInterface::highestActivePriority
uint8_t highestActivePriority() const
Definition: gic_v3_cpu_interface.cc:2298
gem5::Gicv3CPUInterface::res0_1
Bitfield< 26, 15 > res0_1
Definition: gic_v3_cpu_interface.hh:210
gem5::Gicv3CPUInterface::setThreadContext
void setThreadContext(ThreadContext *tc) override
Definition: gic_v3_cpu_interface.cc:84
gem5::Gicv3CPUInterface::virtualHighestActivePriority
uint8_t virtualHighestActivePriority() const
Definition: gic_v3_cpu_interface.cc:2202
gem5::Gicv3CPUInterface::VGrp0E
Bitfield< 4 > VGrp0E
Definition: gic_v3_cpu_interface.hh:260
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::Gicv3CPUInterface::res0_1
Bitfield< 7 > res0_1
Definition: gic_v3_cpu_interface.hh:84
gem5::Gicv3CPUInterface::maintenanceInterrupt
ArmInterruptPin * maintenanceInterrupt
Definition: gic_v3_cpu_interface.hh:73
gem5::Gicv3Registers
Definition: gic_v3.hh:57
gem5::Gicv3CPUInterface::TC
Bitfield< 10 > TC
Definition: gic_v3_cpu_interface.hh:215
gem5::Gicv3CPUInterface::EOImode_EL1NS
Bitfield< 4 > EOImode_EL1NS
Definition: gic_v3_cpu_interface.hh:104
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::Gicv3CPUInterface::GICH_HCR
@ GICH_HCR
Definition: gic_v3_cpu_interface.hh:196
gem5::Gicv3CPUInterface::currEL
ArmISA::ExceptionLevel currEL() const
Definition: gic_v3_cpu_interface.cc:2346
gem5::Gicv3CPUInterface::distributor
Gicv3Distributor * distributor
Definition: gic_v3_cpu_interface.hh:70
gem5::Gicv3CPUInterface::res0
res0
Definition: gic_v3_cpu_interface.hh:112
gem5::Gicv3CPUInterface::VGrp1D
Bitfield< 7 > VGrp1D
Definition: gic_v3_cpu_interface.hh:257
gem5::Gicv3CPUInterface::GICH_VMCR
@ GICH_VMCR
Definition: gic_v3_cpu_interface.hh:198
gem5::Gicv3CPUInterface::EOI
Bitfield< 41 > EOI
Definition: gic_v3_cpu_interface.hh:235
gem5::Gicv3CPUInterface::GICC_CTLR
@ GICC_CTLR
Definition: gic_v3_cpu_interface.hh:175
gem5::Gicv3CPUInterface::isAA64
bool isAA64() const
Definition: gic_v3_cpu_interface.cc:2379
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::Gicv3CPUInterface::pINTID
Bitfield< 44, 32 > pINTID
Definition: gic_v3_cpu_interface.hh:234
gem5::Gicv3CPUInterface::redistributor
Gicv3Redistributor * redistributor
Definition: gic_v3_cpu_interface.hh:69
gem5::Gicv3Redistributor
Definition: gic_v3_redistributor.hh:55
gem5::Gicv3CPUInterface::deassertWakeRequest
void deassertWakeRequest(void)
Definition: gic_v3_cpu_interface.cc:2589
gem5::Gicv3CPUInterface::GIC_MIN_VBPR
static const uint8_t GIC_MIN_VBPR
Definition: gic_v3_cpu_interface.hh:161
gem5::Gicv3CPUInterface::VPMR
Bitfield< 31, 24 > VPMR
Definition: gic_v3_cpu_interface.hh:269
gem5::Gicv3CPUInterface::State
State
Definition: gic_v3_cpu_interface.hh:228
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Gicv3CPUInterface::RSS
Bitfield< 18 > RSS
Definition: gic_v3_cpu_interface.hh:78
gem5::Gicv3CPUInterface::readBankedMiscReg
RegVal readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) const
Definition: gic_v3_cpu_interface.cc:1623
gem5::Gicv3CPUInterface::GICC_HPPI
@ GICC_HPPI
Definition: gic_v3_cpu_interface.hh:181
gem5::Gicv3CPUInterface::virtualGroupPriorityMask
uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const
Definition: gic_v3_cpu_interface.cc:1955
gem5::Gicv3CPUInterface::VGrp1DIE
Bitfield< 7 > VGrp1DIE
Definition: gic_v3_cpu_interface.hh:217
gem5::Gicv3CPUInterface::dropPriority
void dropPriority(Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:1715
gem5::Gicv3CPUInterface::EnableGrp1NS
Bitfield< 0 > EnableGrp1NS
Definition: gic_v3_cpu_interface.hh:124
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::Gicv3CPUInterface::getHPPVILR
int getHPPVILR() const
Definition: gic_v3_cpu_interface.cc:2122
gem5::Gicv3CPUInterface::CBPR_EL1S
Bitfield< 0 > CBPR_EL1S
Definition: gic_v3_cpu_interface.hh:108
gem5::Gicv3CPUInterface::TDS
Bitfield< 19 > TDS
Definition: gic_v3_cpu_interface.hh:290
gem5::Gicv3CPUInterface::VGrp1E
Bitfield< 6 > VGrp1E
Definition: gic_v3_cpu_interface.hh:258
gem5::Gicv3CPUInterface::EOImode
Bitfield< 1 > EOImode
Definition: gic_v3_cpu_interface.hh:87
gem5::Gicv3CPUInterface::GICC_BPR
@ GICC_BPR
Definition: gic_v3_cpu_interface.hh:177
gem5::Gicv3CPUInterface::clearPendingInterrupts
void clearPendingInterrupts(void)
Definition: gic_v3_cpu_interface.cc:2572
gem5::Gicv3CPUInterface::update
void update()
Definition: gic_v3_cpu_interface.cc:2033
gem5::Gicv3CPUInterface::hppiCanPreempt
bool hppiCanPreempt()
Definition: gic_v3_cpu_interface.cc:2265
gem5::Gicv3CPUInterface::NPIE
Bitfield< 3 > NPIE
Definition: gic_v3_cpu_interface.hh:221
gem5::Gicv3CPUInterface::EOIcount
Bitfield< 31, 27 > EOIcount
Definition: gic_v3_cpu_interface.hh:209
gem5::Gicv3CPUInterface::nDS
Bitfield< 17 > nDS
Definition: gic_v3_cpu_interface.hh:95
gem5::Gicv3CPUInterface::resetHppi
void resetHppi(uint32_t intid)
Definition: gic_v3_cpu_interface.cc:77
gem5::Gicv3CPUInterface::VIRTUAL_NUM_LIST_REGS
static const uint8_t VIRTUAL_NUM_LIST_REGS
Definition: gic_v3_cpu_interface.hh:159
gem5::Gicv3CPUInterface::DIB
Bitfield< 2 > DIB
Definition: gic_v3_cpu_interface.hh:129
gem5::Gicv3CPUInterface::res0_0
Bitfield< 5, 2 > res0_0
Definition: gic_v3_cpu_interface.hh:86
gem5::Gicv3CPUInterface::VEOIM
Bitfield< 9 > VEOIM
Definition: gic_v3_cpu_interface.hh:273
gem5::Gicv3CPUInterface::init
void init()
Definition: gic_v3_cpu_interface.cc:70
gem5::Gicv3CPUInterface::eoiMaintenanceInterruptStatus
uint64_t eoiMaintenanceInterruptStatus() const
Definition: gic_v3_cpu_interface.cc:2404
gem5::Gicv3CPUInterface::TALL0
Bitfield< 11 > TALL0
Definition: gic_v3_cpu_interface.hh:214
gem5::Gicv3CPUInterface::havePendingInterrupts
bool havePendingInterrupts(void) const
Definition: gic_v3_cpu_interface.cc:2566
gem5::Gicv3CPUInterface::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v3_cpu_interface.cc:2627
gem5::Gicv3CPUInterface::res0_3
res0_3
Definition: gic_v3_cpu_interface.hh:76
gem5::PowerISA::to
Bitfield< 25, 21 > to
Definition: types.hh:96
gem5::Gicv3CPUInterface::isEL3OrMon
bool isEL3OrMon() const
Definition: gic_v3_cpu_interface.cc:2386
gem5::Gicv3CPUInterface::isEOISplitMode
bool isEOISplitMode() const
Definition: gic_v3_cpu_interface.cc:1981
gem5::Gicv3CPUInterface::PREbits
Bitfield< 28, 26 > PREbits
Definition: gic_v3_cpu_interface.hh:285
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::Gicv3CPUInterface::generateSGI
EndBitUnion(ICV_CTLR_EL1) protected void generateSGI(RegVal val, Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:1774
gem5::Gicv3CPUInterface::virtualUpdate
void virtualUpdate()
Definition: gic_v3_cpu_interface.cc:2070
gem5::Gicv3CPUInterface::GICC_IIDR
@ GICC_IIDR
Definition: gic_v3_cpu_interface.hh:187
gem5::Gicv3CPUInterface::gic
Gicv3 * gic
Definition: gic_v3_cpu_interface.hh:68
gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_PENDING
static const uint64_t ICH_LR_EL2_STATE_PENDING
Definition: gic_v3_cpu_interface.hh:240
gem5::Gicv3CPUInterface::highestActiveGroup
int highestActiveGroup() const
Definition: gic_v3_cpu_interface.cc:2005
gem5::Gicv3CPUInterface::vINTID
Bitfield< 31, 0 > vINTID
Definition: gic_v3_cpu_interface.hh:236
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Gicv3CPUInterface::EndBitUnion
EndBitUnion(ICC_CTLR_EL1) BitUnion64(ICC_CTLR_EL3) Bitfield< 63
gem5::Gicv3CPUInterface::hppviCanPreempt
bool hppviCanPreempt(int lrIdx) const
Definition: gic_v3_cpu_interface.cc:2166
gem5::Gicv3CPUInterface::SRE
Bitfield< 0 > SRE
Definition: gic_v3_cpu_interface.hh:131
gem5::Gicv3CPUInterface::GIC_MIN_BPR_NS
static const uint8_t GIC_MIN_BPR_NS
Definition: gic_v3_cpu_interface.hh:155
gem5::Gicv3CPUInterface::res0_0
Bitfield< 9, 8 > res0_0
Definition: gic_v3_cpu_interface.hh:216
gem5::Gicv3CPUInterface::intSignalType
ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const
Definition: gic_v3_cpu_interface.cc:2235
gem5::Gicv3CPUInterface::hppi_t::intid
uint32_t intid
Definition: gic_v3_cpu_interface.hh:165
gem5::Gicv3CPUInterface::HW
Bitfield< 61 > HW
Definition: gic_v3_cpu_interface.hh:229
gem5::Gicv3CPUInterface::isSecureBelowEL3
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Definition: gic_v3_cpu_interface.cc:2372
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Definition: gic_v3_cpu_interface.hh:80
gem5::Gicv3CPUInterface::TDIR
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Definition: gic_v3_cpu_interface.hh:211
gem5::Gicv3CPUInterface::res1
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Definition: gic_v3_cpu_interface.hh:289
gem5::Gicv3CPUInterface::BitUnion64
BitUnion64(ICC_CTLR_EL1) Bitfield< 63
gem5::Gicv3CPUInterface::VGrp0DIE
Bitfield< 5 > VGrp0DIE
Definition: gic_v3_cpu_interface.hh:219
gem5::Gicv3CPUInterface::BitUnion32
BitUnion32(ICH_LRC) Bitfield< 31
gem5::Gicv3CPUInterface::GICC_ABPR
@ GICC_ABPR
Definition: gic_v3_cpu_interface.hh:182
gem5::Gicv3CPUInterface::copy
void copy(Gicv3Registers *from, Gicv3Registers *to)
Definition: gic_v3_cpu_interface.cc:2596
gem5::Gicv3CPUInterface::virtualDeactivateIRQ
void virtualDeactivateIRQ(int lrIdx)
Definition: gic_v3_cpu_interface.cc:1899
gem5::Gicv3CPUInterface::NP
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Definition: gic_v3_cpu_interface.hh:261
gem5::Gicv3CPUInterface::VGrp0D
Bitfield< 5 > VGrp0D
Definition: gic_v3_cpu_interface.hh:259
gem5::Gicv3CPUInterface::EOImode_EL1S
Bitfield< 3 > EOImode_EL1S
Definition: gic_v3_cpu_interface.hh:105
gem5::ArmISA::InterruptTypes
InterruptTypes
Definition: interrupts.hh:59
gem5::Gicv3CPUInterface::getHCREL2FMO
bool getHCREL2FMO() const
Definition: gic_v3_cpu_interface.cc:92
gem5::Gicv3CPUInterface::getHCREL2IMO
bool getHCREL2IMO() const
Definition: gic_v3_cpu_interface.cc:106
gem5::Gicv3CPUInterface::TSEI
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Definition: gic_v3_cpu_interface.hh:212
gem5::Gicv3CPUInterface::hppi
hppi_t hppi
Definition: gic_v3_cpu_interface.hh:170
gem5::Gicv3CPUInterface::VBPR0
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Definition: gic_v3_cpu_interface.hh:270
gem5::Gicv3CPUInterface::DFB
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Definition: gic_v3_cpu_interface.hh:130
gem5::Gicv3CPUInterface::GICH_EISR
@ GICH_EISR
Definition: gic_v3_cpu_interface.hh:200
gem5::Gicv3CPUInterface::GICC_IAR
@ GICC_IAR
Definition: gic_v3_cpu_interface.hh:178
gem5::Gicv3CPUInterface::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v3_cpu_interface.cc:2619
gem5::Gicv3CPUInterface::updateDistributor
void updateDistributor()
Definition: gic_v3_cpu_interface.cc:2027
gem5::Gicv3CPUInterface::GICH_APR
static const AddrRange GICH_APR
Definition: gic_v3_cpu_interface.hh:204
gem5::Gicv3CPUInterface::GICC_NSAPR
static const AddrRange GICC_NSAPR
Definition: gic_v3_cpu_interface.hh:191
gem5::Gicv3CPUInterface::GICH_VTR
@ GICH_VTR
Definition: gic_v3_cpu_interface.hh:197
gem5::Gicv3CPUInterface::VIRTUAL_PREEMPTION_BITS
static const uint8_t VIRTUAL_PREEMPTION_BITS
Definition: gic_v3_cpu_interface.hh:158
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::Gicv3CPUInterface::GICH_ELRSR
@ GICH_ELRSR
Definition: gic_v3_cpu_interface.hh:201
gem5::Gicv3CPUInterface::UIE
Bitfield< 1 > UIE
Definition: gic_v3_cpu_interface.hh:223
gem5::Gicv3CPUInterface::LRENP
Bitfield< 2 > LRENP
Definition: gic_v3_cpu_interface.hh:262
gem5::Gicv3CPUInterface::VBPR1
Bitfield< 20, 18 > VBPR1
Definition: gic_v3_cpu_interface.hh:271
gem5::Gicv3CPUInterface::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Write to a system register belonging to this device.
Definition: gic_v3_cpu_interface.cc:740
gem5::Gicv3CPUInterface::GICC_PMR
@ GICC_PMR
Definition: gic_v3_cpu_interface.hh:176
gem5::Gicv3CPUInterface::cpuId
uint32_t cpuId
Definition: gic_v3_cpu_interface.hh:71
gem5::Gicv3CPUInterface::GICC_AHPPIR
@ GICC_AHPPIR
Definition: gic_v3_cpu_interface.hh:185
gem5::Gicv3CPUInterface::GICH_MISR
@ GICH_MISR
Definition: gic_v3_cpu_interface.hh:199
gem5::Gicv3CPUInterface::virtualIncrementEOICount
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Definition: gic_v3_cpu_interface.cc:2223
gem5::Gicv3CPUInterface::deactivateIRQ
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Definition: gic_v3_cpu_interface.cc:1885
gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_ACTIVE_PENDING
static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING
Definition: gic_v3_cpu_interface.hh:242
gem5::Gicv3
Definition: gic_v3.hh:95
gem5::Gicv3CPUInterface::EOImode_EL3
Bitfield< 2 > EOImode_EL3
Definition: gic_v3_cpu_interface.hh:106
gem5::Gicv3Distributor
Definition: gic_v3_distributor.hh:51
gem5::Gicv3CPUInterface::GICC_EOIR
@ GICC_EOIR
Definition: gic_v3_cpu_interface.hh:179
gem5::Gicv3CPUInterface::virtualDropPriority
uint8_t virtualDropPriority()
Definition: gic_v3_cpu_interface.cc:1744
gem5::Gicv3CPUInterface::ListRegs
Bitfield< 4, 0 > ListRegs
Definition: gic_v3_cpu_interface.hh:292
gem5::Gicv3CPUInterface::GICC_STATUSR
@ GICC_STATUSR
Definition: gic_v3_cpu_interface.hh:186
gem5::Gicv3CPUInterface
Definition: gic_v3_cpu_interface.hh:58
gem5::Gicv3CPUInterface::TALL1
Bitfield< 12 > TALL1
Definition: gic_v3_cpu_interface.hh:213
gem5::Gicv3CPUInterface::VENG0
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Definition: gic_v3_cpu_interface.hh:279
gem5::Gicv3CPUInterface::IDbits
Bitfield< 13, 11 > IDbits
Definition: gic_v3_cpu_interface.hh:82
gem5::Gicv3CPUInterface::hppi_t::group
Gicv3::GroupId group
Definition: gic_v3_cpu_interface.hh:167
gem5::Gicv3CPUInterface::VAckCtl
Bitfield< 2 > VAckCtl
Definition: gic_v3_cpu_interface.hh:277
gem5::Gicv3CPUInterface::SEIS
Bitfield< 14 > SEIS
Definition: gic_v3_cpu_interface.hh:81
gem5::Gicv3CPUInterface::PRIbits
Bitfield< 10, 8 > PRIbits
Definition: gic_v3_cpu_interface.hh:83
gem5::Gicv3CPUInterface::CBPR_EL1NS
Bitfield< 1 > CBPR_EL1NS
Definition: gic_v3_cpu_interface.hh:107
gem5::Gicv3CPUInterface::Enable
Bitfield< 0 > Enable
Definition: gic_v3_cpu_interface.hh:113
gem5::Gicv3CPUInterface::LRENPIE
Bitfield< 2 > LRENPIE
Definition: gic_v3_cpu_interface.hh:222
gem5::Gicv3CPUInterface::VFIQEn
Bitfield< 3 > VFIQEn
Definition: gic_v3_cpu_interface.hh:276
gem5::Gicv3CPUInterface::hppi_t
Definition: gic_v3_cpu_interface.hh:163
gem5::Gicv3CPUInterface::inSecureState
bool inSecureState() const
Definition: gic_v3_cpu_interface.cc:2340
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::Gicv3CPUInterface::groupPriorityMask
uint32_t groupPriorityMask(Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:1924
gem5::Gicv3CPUInterface::GICH_LR
static const AddrRange GICH_LR
Definition: gic_v3_cpu_interface.hh:205
gem5::Gicv3CPUInterface::VCBPR
Bitfield< 4 > VCBPR
Definition: gic_v3_cpu_interface.hh:275
gem5::Gicv3CPUInterface::maintenanceInterruptStatus
ICH_MISR_EL2 maintenanceInterruptStatus() const
Definition: gic_v3_cpu_interface.cc:2437
gem5::Gicv3CPUInterface::RM
Bitfield< 5 > RM
Definition: gic_v3_cpu_interface.hh:103
gem5::ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:199
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Gicv3CPUInterface::GICC_APR
static const AddrRange GICC_APR
Definition: gic_v3_cpu_interface.hh:190
gem5::Gicv3CPUInterface::CBPR
Bitfield< 0 > CBPR
Definition: gic_v3_cpu_interface.hh:88
gem5::Gicv3CPUInterface::assertWakeRequest
void assertWakeRequest(void)
Definition: gic_v3_cpu_interface.cc:2579
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
gem5::Gicv3CPUInterface::VGrp0EIE
Bitfield< 4 > VGrp0EIE
Definition: gic_v3_cpu_interface.hh:220
gem5::Gicv3CPUInterface::GICC_AEOIR
@ GICC_AEOIR
Definition: gic_v3_cpu_interface.hh:184
gem5::Gicv3CPUInterface::GICC_AIAR
@ GICC_AIAR
Definition: gic_v3_cpu_interface.hh:183
gem5::Gicv3CPUInterface::PMHE
Bitfield< 6 > PMHE
Definition: gic_v3_cpu_interface.hh:85
gem5::Gicv3CPUInterface::setBankedMiscReg
void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const
Definition: gic_v3_cpu_interface.cc:1630
gem5::Gicv3CPUInterface::virtualFindActive
int virtualFindActive(uint32_t intid) const
Definition: gic_v3_cpu_interface.cc:1637
gem5::Gicv3CPUInterface::readMiscReg
RegVal readMiscReg(int misc_reg) override
Read a system register belonging to this device.
Definition: gic_v3_cpu_interface.cc:120
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Gicv3CPUInterface::U
Bitfield< 1 > U
Definition: gic_v3_cpu_interface.hh:263
gem5::Gicv3CPUInterface::GICC_RPR
@ GICC_RPR
Definition: gic_v3_cpu_interface.hh:180
gem5::Gicv3CPUInterface::GIC_MIN_BPR
static const uint8_t GIC_MIN_BPR
Definition: gic_v3_cpu_interface.hh:153
gem5::Gicv3CPUInterface::bpr1
RegVal bpr1(Gicv3::GroupId group)
Definition: gic_v3_cpu_interface.cc:2525
gem5::Gicv3CPUInterface::getHPPIR0
uint32_t getHPPIR0() const
Definition: gic_v3_cpu_interface.cc:1654
gem5::Gicv3CPUInterface::En
Bitfield< 0 > En
Definition: gic_v3_cpu_interface.hh:224
gem5::Gicv3CPUInterface::EnableGrp1S
Bitfield< 1 > EnableGrp1S
Definition: gic_v3_cpu_interface.hh:123
gic_v3.hh
gem5::Gicv3CPUInterface::VGrp1EIE
Bitfield< 6 > VGrp1EIE
Definition: gic_v3_cpu_interface.hh:218
gem5::Gicv3CPUInterface::virtualActivateIRQ
void virtualActivateIRQ(uint32_t lrIdx)
Definition: gic_v3_cpu_interface.cc:1864
gem5::Gicv3CPUInterface::virtualIsEOISplitMode
bool virtualIsEOISplitMode() const
Definition: gic_v3_cpu_interface.cc:1998
gem5::Gicv3CPUInterface::hppi_t::prio
uint8_t prio
Definition: gic_v3_cpu_interface.hh:166
gem5::Gicv3CPUInterface::VENG1
Bitfield< 1 > VENG1
Definition: gic_v3_cpu_interface.hh:278
gem5::Gicv3CPUInterface::getHPPIR1
uint32_t getHPPIR1() const
Definition: gic_v3_cpu_interface.cc:1680
gem5::Gicv3CPUInterface::haveEL
bool haveEL(ArmISA::ExceptionLevel el) const
Definition: gic_v3_cpu_interface.cc:2352
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
gem5::Gicv3CPUInterface::res0_2
Bitfield< 17, 16 > res0_2
Definition: gic_v3_cpu_interface.hh:79
gem5::Gicv3CPUInterface::ICH_LR_EL2_STATE_ACTIVE
static const uint64_t ICH_LR_EL2_STATE_ACTIVE
Definition: gic_v3_cpu_interface.hh:241
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61
gem5::Gicv3CPUInterface::Priority
Bitfield< 55, 48 > Priority
Definition: gic_v3_cpu_interface.hh:232
gem5::Gicv3CPUInterface::VIRTUAL_PRIORITY_BITS
static const uint8_t VIRTUAL_PRIORITY_BITS
Definition: gic_v3_cpu_interface.hh:157

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