gem5  v22.1.0.0
gic_v3_cpu_interface.hh
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40 
41 #ifndef __DEV_ARM_GICV3_CPU_INTERFACE_H__
42 #define __DEV_ARM_GICV3_CPU_INTERFACE_H__
43 
44 #include "arch/arm/isa_device.hh"
45 #include "dev/arm/gic_v3.hh"
46 
47 namespace gem5
48 {
49 
50 class Gicv3Distributor;
51 class Gicv3Redistributor;
52 
53 namespace ArmISA
54 {
55 class ISA;
56 }
57 
59 {
60  private:
61 
62  friend class Gicv3Distributor;
63  friend class Gicv3Redistributor;
64  friend class ArmISA::ISA;
65 
66  protected:
67 
71 
74  uint32_t cpuId;
75 
76  BitUnion64(ICC_CTLR_EL1)
77  Bitfield<63, 20> res0_3;
78  Bitfield<19> ExtRange;
79  Bitfield<18> RSS;
80  Bitfield<17, 16> res0_2;
81  Bitfield<15> A3V;
82  Bitfield<14> SEIS;
83  Bitfield<13, 11> IDbits;
84  Bitfield<10, 8> PRIbits;
85  Bitfield<7> res0_1;
86  Bitfield<6> PMHE;
87  Bitfield<5, 2> res0_0;
88  Bitfield<1> EOImode;
89  Bitfield<0> CBPR;
90  EndBitUnion(ICC_CTLR_EL1)
91 
92  BitUnion64(ICC_CTLR_EL3)
93  Bitfield<63, 20> res0_2;
94  Bitfield<19> ExtRange;
95  Bitfield<18> RSS;
96  Bitfield<17> nDS;
97  Bitfield<16> res0_1;
98  Bitfield<15> A3V;
99  Bitfield<14> SEIS;
100  Bitfield<13, 11> IDbits;
101  Bitfield<10, 8> PRIbits;
102  Bitfield<7> res0_0;
103  Bitfield<6> PMHE;
104  Bitfield<5> RM;
105  Bitfield<4> EOImode_EL1NS;
106  Bitfield<3> EOImode_EL1S;
107  Bitfield<2> EOImode_EL3;
108  Bitfield<1> CBPR_EL1NS;
109  Bitfield<0> CBPR_EL1S;
110  EndBitUnion(ICC_CTLR_EL3)
111 
112  BitUnion64(ICC_IGRPEN0_EL1)
113  Bitfield<63, 1> res0;
114  Bitfield<0> Enable;
115  EndBitUnion(ICC_IGRPEN0_EL1)
116 
117  BitUnion64(ICC_IGRPEN1_EL1)
118  Bitfield<63, 1> res0;
119  Bitfield<0> Enable;
120  EndBitUnion(ICC_IGRPEN1_EL1)
121 
122  BitUnion64(ICC_IGRPEN1_EL3)
123  Bitfield<63, 2> res0;
124  Bitfield<1> EnableGrp1S;
125  Bitfield<0> EnableGrp1NS;
126  EndBitUnion(ICC_IGRPEN1_EL3)
127 
128  BitUnion64(ICC_SRE_EL1)
129  Bitfield<63, 3> res0;
130  Bitfield<2> DIB;
131  Bitfield<1> DFB;
132  Bitfield<0> SRE;
133  EndBitUnion(ICC_SRE_EL1)
134 
135  BitUnion64(ICC_SRE_EL2)
136  Bitfield<63, 4> res0;
137  Bitfield<3> Enable;
138  Bitfield<2> DIB;
139  Bitfield<1> DFB;
140  Bitfield<0> SRE;
141  EndBitUnion(ICC_SRE_EL2)
142 
143  BitUnion64(ICC_SRE_EL3)
144  Bitfield<63, 4> res0;
145  Bitfield<3> Enable;
146  Bitfield<2> DIB;
147  Bitfield<1> DFB;
148  Bitfield<0> SRE;
149  EndBitUnion(ICC_SRE_EL3)
150 
151  static const uint8_t PRIORITY_BITS = 5;
152 
153  // Minimum BPR for Secure, or when security not enabled
154  static const uint8_t GIC_MIN_BPR = 2;
155  // Minimum BPR for Nonsecure when security is enabled
156  static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1;
157 
158  static const uint8_t VIRTUAL_PRIORITY_BITS = 5;
159  static const uint8_t VIRTUAL_PREEMPTION_BITS = 5;
160  static const uint8_t VIRTUAL_NUM_LIST_REGS = 16;
161 
162  static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS;
163 
164  struct hppi_t
165  {
166  uint32_t intid;
167  uint8_t prio;
169  };
170 
172 
173  // GIC CPU interface memory mapped control registers (legacy)
174  enum
175  {
176  GICC_CTLR = 0x0000,
177  GICC_PMR = 0x0004,
178  GICC_BPR = 0x0008,
179  GICC_IAR = 0x000C,
180  GICC_EOIR = 0x0010,
181  GICC_RPR = 0x0014,
182  GICC_HPPI = 0x0018,
183  GICC_ABPR = 0x001C,
184  GICC_AIAR = 0x0020,
185  GICC_AEOIR = 0x0024,
186  GICC_AHPPIR = 0x0028,
187  GICC_STATUSR = 0x002C,
188  GICC_IIDR = 0x00FC,
189  };
190 
191  static const AddrRange GICC_APR;
192  static const AddrRange GICC_NSAPR;
193 
194  // GIC CPU virtual interface memory mapped control registers (legacy)
195  enum
196  {
197  GICH_HCR = 0x0000,
198  GICH_VTR = 0x0004,
199  GICH_VMCR = 0x0008,
200  GICH_MISR = 0x0010,
201  GICH_EISR = 0x0020,
202  GICH_ELRSR = 0x0030,
203  };
204 
205  static const AddrRange GICH_APR;
206  static const AddrRange GICH_LR;
207 
208  public:
209  BitUnion64(ICH_HCR_EL2)
210  Bitfield<63, 32> res0_2;
211  Bitfield<31, 27> EOIcount;
212  Bitfield<26, 15> res0_1;
213  Bitfield<14> TDIR;
214  Bitfield<13> TSEI;
215  Bitfield<12> TALL1;
216  Bitfield<11> TALL0;
217  Bitfield<10> TC;
218  Bitfield<9, 8> res0_0;
219  Bitfield<7> VGrp1DIE;
220  Bitfield<6> VGrp1EIE;
221  Bitfield<5> VGrp0DIE;
222  Bitfield<4> VGrp0EIE;
223  Bitfield<3> NPIE;
224  Bitfield<2> LRENPIE;
225  Bitfield<1> UIE;
226  Bitfield<0> En;
227  EndBitUnion(ICH_HCR_EL2)
228 
229  protected:
230  BitUnion64(ICH_LR_EL2)
231  Bitfield<63, 62> State;
232  Bitfield<61> HW;
233  Bitfield<60> Group;
234  Bitfield<59, 56> res0_1;
235  Bitfield<55, 48> Priority;
236  Bitfield<47, 45> res0_0;
237  Bitfield<44, 32> pINTID;
238  Bitfield<41> EOI;
239  Bitfield<31, 0> vINTID;
240  EndBitUnion(ICH_LR_EL2)
241 
242  static const uint64_t ICH_LR_EL2_STATE_INVALID = 0;
243  static const uint64_t ICH_LR_EL2_STATE_PENDING = 1;
244  static const uint64_t ICH_LR_EL2_STATE_ACTIVE = 2;
245  static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3;
246 
247  BitUnion32(ICH_LRC)
248  Bitfield<31, 30> State;
249  Bitfield<29> HW;
250  Bitfield<28> Group;
251  Bitfield<27, 24> res0_1;
252  Bitfield<23, 16> Priority;
253  Bitfield<15, 13> res0_0;
254  Bitfield<12, 0> pINTID;
255  Bitfield<9> EOI;
256  EndBitUnion(ICH_LRC)
257 
258  BitUnion64(ICH_MISR_EL2)
259  Bitfield<63, 8> res0;
260  Bitfield<7> VGrp1D;
261  Bitfield<6> VGrp1E;
262  Bitfield<5> VGrp0D;
263  Bitfield<4> VGrp0E;
264  Bitfield<3> NP;
265  Bitfield<2> LRENP;
266  Bitfield<1> U;
267  Bitfield<0> EOI;
268  EndBitUnion(ICH_MISR_EL2)
269 
270  BitUnion64(ICH_VMCR_EL2)
271  Bitfield<63, 32> res0_2;
272  Bitfield<31, 24> VPMR;
273  Bitfield<23, 21> VBPR0;
274  Bitfield<20, 18> VBPR1;
275  Bitfield<17, 10> res0_1;
276  Bitfield<9> VEOIM;
277  Bitfield<8, 5> res0_0;
278  Bitfield<4> VCBPR;
279  Bitfield<3> VFIQEn;
280  Bitfield<2> VAckCtl;
281  Bitfield<1> VENG1;
282  Bitfield<0> VENG0;
283  EndBitUnion(ICH_VMCR_EL2)
284 
285  BitUnion64(ICH_VTR_EL2)
286  Bitfield<63, 32> res0_1;
287  Bitfield<31, 29> PRIbits;
288  Bitfield<28, 26> PREbits;
289  Bitfield<25, 23> IDbits;
290  Bitfield<22> SEIS;
291  Bitfield<21> A3V;
292  Bitfield<20> res1;
293  Bitfield<19> TDS;
294  Bitfield<18, 5> res0_0;
295  Bitfield<4, 0> ListRegs;
296  EndBitUnion(ICH_VTR_EL2)
297 
298  BitUnion64(ICV_CTLR_EL1)
299  Bitfield<63, 19> res0_2;
300  Bitfield<18> RSS;
301  Bitfield<17, 16> res0_1;
302  Bitfield<15> A3V;
303  Bitfield<14> SEIS;
304  Bitfield<13, 11> IDbits;
305  Bitfield<10, 8> PRIbits;
306  Bitfield<7, 2> res0_0;
307  Bitfield<1> EOImode;
308  Bitfield<0> CBPR;
309  EndBitUnion(ICV_CTLR_EL1)
310 
311  protected:
312 
313  void activateIRQ(uint32_t intid, Gicv3::GroupId group);
314  void generateSGI(RegVal val, Gicv3::GroupId group);
315  ArmISA::ExceptionLevel currEL() const;
316  void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
317  void dropPriority(Gicv3::GroupId group);
318  uint64_t eoiMaintenanceInterruptStatus() const;
319  bool getHCREL2FMO() const;
320  bool getHCREL2IMO() const;
321  uint32_t getHPPIR0() const;
322  uint32_t getHPPIR1() const;
323  int getHPPVILR() const;
324  bool groupEnabled(Gicv3::GroupId group) const;
325  uint32_t groupPriorityMask(Gicv3::GroupId group);
326  bool haveEL(ArmISA::ExceptionLevel el) const;
327  int highestActiveGroup() const;
328  uint8_t highestActivePriority() const;
329  bool hppiCanPreempt();
330  bool hppviCanPreempt(int lrIdx) const;
331  bool inSecureState() const;
332  ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
333  bool isAA64() const;
334  bool isEL3OrMon() const;
335  bool isEOISplitMode() const;
336  bool isSecureBelowEL3() const;
337  ICH_MISR_EL2 maintenanceInterruptStatus() const;
338  void resetHppi(uint32_t intid);
339  void serialize(CheckpointOut & cp) const override;
340  void unserialize(CheckpointIn & cp) override;
341  void update();
342  void updateDistributor();
343  void virtualActivateIRQ(uint32_t lrIdx);
344  void virtualDeactivateIRQ(int lrIdx);
345  uint8_t virtualDropPriority();
346  int virtualFindActive(uint32_t intid) const;
347  uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
348  uint8_t virtualHighestActivePriority() const;
350  bool virtualIsEOISplitMode() const;
351  void virtualUpdate();
352  RegVal bpr1(Gicv3::GroupId group);
353  bool havePendingInterrupts(void) const;
354  void clearPendingInterrupts(void);
355  void assertWakeRequest(void);
356  void deassertWakeRequest(void);
357 
358  RegVal readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) const;
359  void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
360  public:
361 
363 
364  void init();
365 
366  public:
367  void copy(Gicv3Registers *from, Gicv3Registers *to);
368 
369  public: // BaseISADevice
370  RegVal readMiscReg(int misc_reg) override;
371  void setMiscReg(int misc_reg, RegVal val) override;
372  void setThreadContext(ThreadContext *tc) override;
373 };
374 
375 } // namespace gem5
376 
377 #endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:82
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:62
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:200
void dropPriority(Gicv3::GroupId group)
EndBitUnion(ICC_CTLR_EL1) BitUnion64(ICC_CTLR_EL3) Bitfield< 63
static const uint8_t VIRTUAL_PREEMPTION_BITS
static const AddrRange GICC_APR
void unserialize(CheckpointIn &cp) override
Unserialize an object.
EndBitUnion(ICH_LR_EL2) static const uint64_t ICH_LR_EL2_STATE_INVALID=0
bool groupEnabled(Gicv3::GroupId group) const
static const AddrRange GICH_LR
void resetHppi(uint32_t intid)
EndBitUnion(ICV_CTLR_EL1) protected void generateSGI(RegVal val, Gicv3::GroupId group)
void serialize(CheckpointOut &cp) const override
Serialize an object.
ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const
ArmISA::ExceptionLevel currEL() const
uint64_t eoiMaintenanceInterruptStatus() const
BitUnion64(ICH_HCR_EL2) Bitfield< 63
bool hppviCanPreempt(int lrIdx) const
void virtualActivateIRQ(uint32_t lrIdx)
Gicv3Redistributor * redistributor
RegVal bpr1(Gicv3::GroupId group)
EndBitUnion(ICH_HCR_EL2) protected Bitfield< 61 > HW
static const AddrRange GICH_APR
void setThreadContext(ThreadContext *tc) override
static const uint8_t GIC_MIN_BPR
BitUnion32(ICH_LRC) Bitfield< 31
RegVal readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) const
uint32_t groupPriorityMask(Gicv3::GroupId group)
Gicv3Distributor * distributor
ArmInterruptPin * maintenanceInterrupt
ICH_MISR_EL2 maintenanceInterruptStatus() const
static const uint8_t GIC_MIN_BPR_NS
void deactivateIRQ(uint32_t intid, Gicv3::GroupId group)
static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING
static const uint8_t VIRTUAL_NUM_LIST_REGS
uint8_t virtualHighestActivePriority() const
void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const
uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const
void setMiscReg(int misc_reg, RegVal val) override
Write to a system register belonging to this device.
static const uint64_t ICH_LR_EL2_STATE_ACTIVE
static const AddrRange GICC_NSAPR
static const uint64_t ICH_LR_EL2_STATE_PENDING
bool haveEL(ArmISA::ExceptionLevel el) const
int virtualFindActive(uint32_t intid) const
bool havePendingInterrupts(void) const
static const uint8_t GIC_MIN_VBPR
BitUnion64(ICC_CTLR_EL1) Bitfield< 63
RegVal readMiscReg(int misc_reg) override
Read a system register belonging to this device.
static const uint8_t VIRTUAL_PRIORITY_BITS
void copy(Gicv3Registers *from, Gicv3Registers *to)
Basic support for object serialization.
Definition: serialize.hh:170
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Statistics container.
Definition: group.hh:94
MiscRegIndex
Definition: misc.hh:64
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
Bitfield< 25, 21 > to
Definition: types.hh:96
Bitfield< 63 > val
Definition: misc.hh:776
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::ostream CheckpointOut
Definition: serialize.hh:66
uint64_t RegVal
Definition: types.hh:173

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