gem5 v24.1.0.1
Loading...
Searching...
No Matches
misc64.hh
Go to the documentation of this file.
1/*
2 * Copyright (c) 2011-2013,2017-2019, 2021-2022, 2024 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __ARCH_ARM_INSTS_MISC64_HH__
39#define __ARCH_ARM_INSTS_MISC64_HH__
40
42#include "arch/arm/mmu.hh"
43#include "arch/arm/tlbi_op.hh"
44#include "arch/arm/types.hh"
45
46namespace gem5
47{
48
50{
51 protected:
52 uint64_t imm;
53
54 ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
55 OpClass __opClass, uint64_t _imm) :
56 ArmISA::ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
57 {}
58
59 std::string generateDisassembly(
60 Addr pc, const loader::SymbolTable *symtab) const override;
61};
62
64{
65 protected:
67
68 RegOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
69 OpClass __opClass, RegIndex _op1) :
70 ArmISA::ArmStaticInst(mnem, _machInst, __opClass), op1(_op1)
71 {}
72
73 std::string generateDisassembly(
74 Addr pc, const loader::SymbolTable *symtab) const override;
75};
76
78{
79 protected:
81 uint64_t imm1;
82 uint64_t imm2;
83
84 RegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
85 OpClass __opClass, RegIndex _op1,
86 uint64_t _imm1, uint64_t _imm2) :
87 ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
88 op1(_op1), imm1(_imm1), imm2(_imm2)
89 {}
90
91 std::string generateDisassembly(
92 Addr pc, const loader::SymbolTable *symtab) const override;
93};
94
96{
97 protected:
100 uint64_t imm1;
101 uint64_t imm2;
102
103 RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
104 OpClass __opClass, RegIndex _dest,
105 RegIndex _op1, uint64_t _imm1,
106 int64_t _imm2) :
107 ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
108 dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
109 {}
110
111 std::string generateDisassembly(
112 Addr pc, const loader::SymbolTable *symtab) const override;
113};
114
116{
117 protected:
121 uint64_t imm;
122
123 RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
124 OpClass __opClass, RegIndex _dest,
125 RegIndex _op1, RegIndex _op2,
126 uint64_t _imm) :
127 ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
128 dest(_dest), op1(_op1), op2(_op2), imm(_imm)
129 {}
130
131 std::string generateDisassembly(
132 Addr pc, const loader::SymbolTable *symtab) const override;
133};
134
136{
137 protected:
138
139 UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
140 OpClass __opClass) :
141 ArmISA::ArmStaticInst(mnem, _machInst, __opClass)
142 {}
143
144 std::string generateDisassembly(
145 Addr pc, const loader::SymbolTable *symtab) const override;
146};
147
160{
161 protected:
163
164 MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
165 OpClass __opClass, bool misc_read) :
166 ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
167 _miscRead(misc_read)
168 {}
169
170 uint32_t _iss(const ArmISA::MiscRegNum64 &misc_reg,
171 RegIndex int_index) const;
172
173 public:
174 virtual uint32_t iss() const { return 0; }
175
176 bool miscRead() const { return _miscRead; }
177
180};
181
183{
184 protected:
186 uint32_t imm;
187
188 MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
189 OpClass __opClass, ArmISA::MiscRegIndex _dest,
190 uint32_t _imm) :
191 MiscRegOp64(mnem, _machInst, __opClass, false),
192 dest(_dest), imm(_imm)
193 {}
194
200 RegVal miscRegImm() const;
201
202 std::string generateDisassembly(
203 Addr pc, const loader::SymbolTable *symtab) const override;
204};
205
207{
208 protected:
211
212 MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
213 OpClass __opClass, ArmISA::MiscRegIndex _dest,
214 RegIndex _op1) :
215 MiscRegOp64(mnem, _machInst, __opClass, false),
216 dest(_dest), op1(_op1)
217 {}
218
219 std::string generateDisassembly(
220 Addr pc, const loader::SymbolTable *symtab) const override;
221
222 uint32_t iss() const override;
223};
224
226{
227 protected:
230
231 RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
232 OpClass __opClass, RegIndex _dest,
234 MiscRegOp64(mnem, _machInst, __opClass, true),
235 dest(_dest), op1(_op1)
236 {}
237
238 std::string generateDisassembly(
239 Addr pc, const loader::SymbolTable *symtab) const override;
240
241 uint32_t iss() const override;
242};
243
245{
246 protected:
247 const std::string fullMnemonic;
250
251 public:
252 MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst,
253 ArmISA::MiscRegNum64 &&misc_reg, RegIndex int_reg,
254 bool misc_read, const std::string full_mnem) :
255 MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
256 fullMnemonic(full_mnem), miscReg(misc_reg), intReg(int_reg)
257 {
259 }
260
261 protected:
263 trace::InstRecord *traceData) const override;
264
265 std::string generateDisassembly(
266 Addr pc, const loader::SymbolTable *symtab) const override;
267
268 uint32_t iss() const override;
269};
270
272{
273 protected:
275
276 RegNone(const char *mnem, ArmISA::ExtMachInst _machInst,
277 OpClass __opClass, RegIndex _dest) :
278 ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
279 dest(_dest)
280 {}
281
282 std::string generateDisassembly(
283 Addr pc, const loader::SymbolTable *symtab) const;
284};
285
287{
288 protected:
289 using TlbiFunc = std::function<void(ThreadContext*,RegVal)>;
291
292 static std::unordered_map<ArmISA::MiscRegIndex, TlbiFunc> tlbiOps;
293
294 static void tlbiAll(ThreadContext *tc, RegVal value,
296 bool shareable, TlbiAttr attrs=TlbiAttr::None);
297
298 static void tlbiVmall(ThreadContext *tc, RegVal value,
300 bool shareable, bool stage2=false, TlbiAttr attrs=TlbiAttr::None);
301
302 static void tlbiVa(ThreadContext *tc, RegVal value,
304 bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None);
305
306 static void tlbiVaa(ThreadContext *tc, RegVal value,
308 bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None);
309
310 static void tlbiAsid(ThreadContext *tc, RegVal value,
312 bool shareable, TlbiAttr attrs=TlbiAttr::None);
313
314 static void tlbiIpaS2(ThreadContext *tc, RegVal value,
316 bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None);
317
318 static void tlbiRvaa(ThreadContext *tc, RegVal value,
320 bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None);
321
322 static void tlbiRva(ThreadContext *tc, RegVal value,
324 bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None);
325
326 static void tlbiRipaS2(ThreadContext *tc, RegVal value,
328 bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None);
329
330 static bool fnxsAttrs(ThreadContext *tc);
331
332 protected:
333 TlbiOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
334 OpClass __opClass, ArmISA::MiscRegIndex _dest,
335 RegIndex _op1) :
336 MiscRegRegImmOp64(mnem, _machInst, __opClass, _dest, _op1)
337 {}
338
339 void performTlbi(ExecContext *xc,
340 ArmISA::MiscRegIndex idx, RegVal value) const;
341};
342
344{
345 protected:
346 AtOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
347 OpClass __opClass, ArmISA::MiscRegIndex _dest,
348 RegIndex _op1) :
349 MiscRegRegImmOp64(mnem, _machInst, __opClass, _dest, _op1)
350 {}
351
353 ArmISA::MiscRegIndex idx, RegVal val) const;
354
358};
359
360} // namespace gem5
361
362#endif
Fault generateTrap(ArmISA::ExceptionLevel el, ArmISA::ExceptionClass ec, uint32_t iss) const
std::pair< Fault, uint64_t > performAt(ExecContext *xc, ArmISA::MiscRegIndex idx, RegVal val) const
Definition misc64.cc:2538
std::pair< Fault, uint64_t > addressTranslation64(ThreadContext *tc, ArmISA::MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val) const
Definition misc64.cc:2580
AtOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, RegIndex _op1)
Definition misc64.hh:346
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, uint64_t _imm)
Definition misc64.hh:54
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition misc64.cc:50
uint64_t imm
Definition misc64.hh:52
RegVal miscRegImm() const
Returns the "register view" of the immediate field.
Definition misc64.cc:133
ArmISA::MiscRegIndex dest
Definition misc64.hh:185
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition misc64.cc:148
MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, uint32_t _imm)
Definition misc64.hh:188
const ArmISA::MiscRegNum64 miscReg
Definition misc64.hh:248
const std::string fullMnemonic
Definition misc64.hh:247
uint32_t iss() const override
Definition misc64.cc:218
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition misc64.cc:211
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
Definition misc64.cc:200
const RegIndex intReg
Definition misc64.hh:249
MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst, ArmISA::MiscRegNum64 &&misc_reg, RegIndex int_reg, bool misc_read, const std::string full_mnem)
Definition misc64.hh:252
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition misc64.hh:160
uint32_t _iss(const ArmISA::MiscRegNum64 &misc_reg, RegIndex int_index) const
Definition misc64.cc:115
MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, bool misc_read)
Definition misc64.hh:164
Fault generateTrap(ArmISA::ExceptionLevel el) const
Definition misc64.cc:127
virtual uint32_t iss() const
Definition misc64.hh:174
bool miscRead() const
Definition misc64.hh:176
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition misc64.cc:160
ArmISA::MiscRegIndex dest
Definition misc64.hh:209
uint32_t iss() const override
Definition misc64.cc:172
MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, RegIndex _op1)
Definition misc64.hh:212
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition misc64.cc:68
RegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _op1, uint64_t _imm1, uint64_t _imm2)
Definition misc64.hh:84
uint32_t iss() const override
Definition misc64.cc:192
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition misc64.cc:180
ArmISA::MiscRegIndex op1
Definition misc64.hh:229
RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, ArmISA::MiscRegIndex _op1)
Definition misc64.hh:231
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
Definition misc64.cc:224
RegNone(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _dest)
Definition misc64.hh:276
RegIndex dest
Definition misc64.hh:274
RegOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _op1)
Definition misc64.hh:68
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition misc64.cc:59
RegIndex op1
Definition misc64.hh:66
RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint64_t _imm1, int64_t _imm2)
Definition misc64.hh:103
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition misc64.cc:80
RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, RegIndex _op2, uint64_t _imm)
Definition misc64.hh:123
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition misc64.cc:93
std::bitset< Num_Flags > flags
Flag values for this instruction.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
static void tlbiVa(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
Definition misc64.cc:260
static void tlbiIpaS2(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
Definition misc64.cc:322
static bool fnxsAttrs(ThreadContext *tc)
Definition misc64.cc:391
static void tlbiVaa(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
Definition misc64.cc:290
TlbiOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, RegIndex _op1)
Definition misc64.hh:333
static void tlbiAsid(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, TlbiAttr attrs=TlbiAttr::None)
Definition misc64.cc:305
static void tlbiRipaS2(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
Definition misc64.cc:374
static std::unordered_map< ArmISA::MiscRegIndex, TlbiFunc > tlbiOps
Definition misc64.hh:292
void performTlbi(ExecContext *xc, ArmISA::MiscRegIndex idx, RegVal value) const
Definition misc64.cc:2526
static void tlbiRvaa(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
Definition misc64.cc:339
static void tlbiRva(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
Definition misc64.cc:352
static void tlbiAll(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, TlbiAttr attrs=TlbiAttr::None)
Definition misc64.cc:234
static void tlbiVmall(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool stage2=false, TlbiAttr attrs=TlbiAttr::None)
Definition misc64.cc:247
std::function< void(ThreadContext *, RegVal)> TlbiFunc
Definition misc64.hh:289
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition misc64.cc:108
UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass)
Definition misc64.hh:139
STL pair class.
Definition stl.hh:58
Bitfield< 4, 0 > mode
Definition misc_types.hh:74
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition misc.cc:2930
SecurityState
Security State.
Definition types.hh:273
@ MISCREG_IMPDEF_UNIMPL
Definition misc.hh:1203
Bitfield< 3, 2 > el
Definition misc_types.hh:73
Bitfield< 21 > ss
Definition misc_types.hh:60
Bitfield< 4 > pc
Bitfield< 63 > val
Definition misc.hh:804
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
uint16_t RegIndex
Definition types.hh:176
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t RegVal
Definition types.hh:173
The file contains the definition of a set of TLB Invalidate Instructions.

Generated on Mon Jan 13 2025 04:28:18 for gem5 by doxygen 1.9.8