gem5  v21.1.0.2
misc64.hh
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37 
38 #ifndef __ARCH_ARM_INSTS_MISC64_HH__
39 #define __ARCH_ARM_INSTS_MISC64_HH__
40 
42 
43 namespace gem5
44 {
45 
47 {
48  protected:
49  uint64_t imm;
50 
51  ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
52  OpClass __opClass, uint64_t _imm) :
53  ArmISA::ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
54  {}
55 
56  std::string generateDisassembly(
57  Addr pc, const loader::SymbolTable *symtab) const override;
58 };
59 
61 {
62  protected:
63  ArmISA::IntRegIndex dest;
64  ArmISA::IntRegIndex op1;
65  uint64_t imm1;
66  uint64_t imm2;
67 
68  RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
69  OpClass __opClass, ArmISA::IntRegIndex _dest,
70  ArmISA::IntRegIndex _op1, uint64_t _imm1,
71  int64_t _imm2) :
72  ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
73  dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
74  {}
75 
76  std::string generateDisassembly(
77  Addr pc, const loader::SymbolTable *symtab) const override;
78 };
79 
81 {
82  protected:
83  ArmISA::IntRegIndex dest;
84  ArmISA::IntRegIndex op1;
85  ArmISA::IntRegIndex op2;
86  uint64_t imm;
87 
88  RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
89  OpClass __opClass, ArmISA::IntRegIndex _dest,
90  ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
91  uint64_t _imm) :
92  ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
93  dest(_dest), op1(_op1), op2(_op2), imm(_imm)
94  {}
95 
96  std::string generateDisassembly(
97  Addr pc, const loader::SymbolTable *symtab) const override;
98 };
99 
101 {
102  protected:
103 
104  UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
105  OpClass __opClass) :
106  ArmISA::ArmStaticInst(mnem, _machInst, __opClass)
107  {}
108 
109  std::string generateDisassembly(
110  Addr pc, const loader::SymbolTable *symtab) const override;
111 };
112 
125 {
126  protected:
127  bool miscRead;
128 
129  MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
130  OpClass __opClass, bool misc_read) :
131  ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
132  miscRead(misc_read)
133  {}
134 
136  ArmISA::ExceptionLevel el, uint32_t immediate) const;
137  private:
138  bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
140  uint32_t &immediate) const;
141 
142  bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
144  uint32_t &immediate) const;
145 
146  bool checkEL3Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
148  uint32_t &immediate) const;
149 
150 };
151 
153 {
154  protected:
156  uint32_t imm;
157 
158  MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
159  OpClass __opClass, ArmISA::MiscRegIndex _dest,
160  uint32_t _imm) :
161  MiscRegOp64(mnem, _machInst, __opClass, false),
162  dest(_dest), imm(_imm)
163  {}
164 
170  RegVal miscRegImm() const;
171 
172  std::string generateDisassembly(
173  Addr pc, const loader::SymbolTable *symtab) const override;
174 };
175 
177 {
178  protected:
180  ArmISA::IntRegIndex op1;
181  uint32_t imm;
182 
183  MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
184  OpClass __opClass, ArmISA::MiscRegIndex _dest,
185  ArmISA::IntRegIndex _op1, uint32_t _imm) :
186  MiscRegOp64(mnem, _machInst, __opClass, false),
187  dest(_dest), op1(_op1), imm(_imm)
188  {}
189 
190  std::string generateDisassembly(
191  Addr pc, const loader::SymbolTable *symtab) const override;
192 };
193 
195 {
196  protected:
197  ArmISA::IntRegIndex dest;
199  uint32_t imm;
200 
201  RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
202  OpClass __opClass, ArmISA::IntRegIndex _dest,
203  ArmISA::MiscRegIndex _op1, uint32_t _imm) :
204  MiscRegOp64(mnem, _machInst, __opClass, true),
205  dest(_dest), op1(_op1), imm(_imm)
206  {}
207 
208  std::string generateDisassembly(
209  Addr pc, const loader::SymbolTable *symtab) const override;
210 };
211 
213 {
214  protected:
215  const std::string fullMnemonic;
217  const uint32_t imm;
218  const bool warning;
219 
220  public:
221  MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst,
222  ArmISA::MiscRegIndex misc_reg, bool misc_read,
223  uint32_t _imm, const std::string full_mnem,
224  bool _warning) :
225  MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
226  fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm),
227  warning(_warning)
228  {
230  }
231 
232  protected:
234  Trace::InstRecord *traceData) const override;
235 
236  std::string generateDisassembly(
237  Addr pc, const loader::SymbolTable *symtab) const override;
238 };
239 
241 {
242  protected:
243  ArmISA::IntRegIndex dest;
244 
245  RegNone(const char *mnem, ArmISA::ExtMachInst _machInst,
246  OpClass __opClass, ArmISA::IntRegIndex _dest) :
247  ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
248  dest(_dest)
249  {}
250 
251  std::string generateDisassembly(
252  Addr pc, const loader::SymbolTable *symtab) const;
253 };
254 
255 } // namespace gem5
256 
257 #endif
gem5::MiscRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:813
gem5::RegNone::RegNone
RegNone(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest)
Definition: misc64.hh:245
gem5::MiscRegOp64::checkEL1Trap
bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:117
gem5::MiscRegImmOp64
Definition: misc64.hh:152
gem5::RegRegRegImmOp64::RegRegRegImmOp64
RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2, uint64_t _imm)
Definition: misc64.hh:88
gem5::MiscRegOp64::checkEL2Trap
bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:182
gem5::RegMiscRegImmOp64::RegMiscRegImmOp64
RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::MiscRegIndex _op1, uint32_t _imm)
Definition: misc64.hh:201
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::MiscRegImplDefined64::imm
const uint32_t imm
Definition: misc64.hh:217
gem5::RegRegImmImmOp64::imm2
uint64_t imm2
Definition: misc64.hh:66
gem5::RegRegRegImmOp64::op2
ArmISA::IntRegIndex op2
Definition: misc64.hh:85
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::RegRegImmImmOp64::imm1
uint64_t imm1
Definition: misc64.hh:65
gem5::RegRegRegImmOp64
Definition: misc64.hh:80
gem5::RegMiscRegImmOp64::imm
uint32_t imm
Definition: misc64.hh:199
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::UnknownOp64::UnknownOp64
UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass)
Definition: misc64.hh:104
gem5::ImmOp64::ImmOp64
ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, uint64_t _imm)
Definition: misc64.hh:51
gem5::MiscRegRegImmOp64::MiscRegRegImmOp64
MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, ArmISA::IntRegIndex _op1, uint32_t _imm)
Definition: misc64.hh:183
gem5::RegMiscRegImmOp64::dest
ArmISA::IntRegIndex dest
Definition: misc64.hh:197
gem5::ImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:47
gem5::RegMiscRegImmOp64
Definition: misc64.hh:194
gem5::MiscRegRegImmOp64::imm
uint32_t imm
Definition: misc64.hh:181
gem5::MiscRegImmOp64::dest
ArmISA::MiscRegIndex dest
Definition: misc64.hh:155
gem5::RegRegImmImmOp64
Definition: misc64.hh:60
gem5::MiscRegImplDefined64::MiscRegImplDefined64
MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst, ArmISA::MiscRegIndex misc_reg, bool misc_read, uint32_t _imm, const std::string full_mnem, bool _warning)
Definition: misc64.hh:221
gem5::MiscRegOp64::miscRead
bool miscRead
Definition: misc64.hh:127
gem5::ArmISA::ec
ec
Definition: misc_types.hh:669
gem5::ImmOp64
Definition: misc64.hh:46
gem5::MiscRegRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:825
gem5::UnknownOp64
Definition: misc64.hh:100
gem5::MiscRegImplDefined64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:872
gem5::RegNone::dest
ArmISA::IntRegIndex dest
Definition: misc64.hh:243
gem5::MiscRegOp64::MiscRegOp64
MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, bool misc_read)
Definition: misc64.hh:129
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::MiscRegOp64::checkEL3Trap
bool checkEL3Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:646
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::MiscRegImplDefined64::fullMnemonic
const std::string fullMnemonic
Definition: misc64.hh:215
gem5::MiscRegOp64::trap
Fault trap(ThreadContext *tc, ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, uint32_t immediate) const
Definition: misc64.cc:91
gem5::MiscRegImplDefined64::warning
const bool warning
Definition: misc64.hh:218
gem5::ImmOp64::imm
uint64_t imm
Definition: misc64.hh:49
gem5::MiscRegImmOp64::miscRegImm
RegVal miscRegImm() const
Returns the "register view" of the immediate field.
Definition: misc64.cc:801
gem5::MiscRegRegImmOp64::op1
ArmISA::IntRegIndex op1
Definition: misc64.hh:180
gem5::RegRegRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:69
gem5::MiscRegImplDefined64
Definition: misc64.hh:212
gem5::RegNone
Definition: misc64.hh:240
gem5::RegMiscRegImmOp64::op1
ArmISA::MiscRegIndex op1
Definition: misc64.hh:198
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::MiscRegOp64
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition: misc64.hh:124
gem5::RegNone::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
Definition: misc64.cc:879
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:293
gem5::MiscRegRegImmOp64::dest
ArmISA::MiscRegIndex dest
Definition: misc64.hh:179
gem5::MiscRegImmOp64::imm
uint32_t imm
Definition: misc64.hh:156
gem5::MiscRegRegImmOp64
Definition: misc64.hh:176
gem5::RegRegImmImmOp64::RegRegImmImmOp64
RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, uint64_t _imm1, int64_t _imm2)
Definition: misc64.hh:68
gem5::UnknownOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:84
static_inst.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::RegRegRegImmOp64::op1
ArmISA::IntRegIndex op1
Definition: misc64.hh:84
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::RegMiscRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:837
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::RegRegImmImmOp64::dest
ArmISA::IntRegIndex dest
Definition: misc64.hh:63
gem5::RegRegRegImmOp64::dest
ArmISA::IntRegIndex dest
Definition: misc64.hh:83
gem5::ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition: misc.hh:1077
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RegRegRegImmOp64::imm
uint64_t imm
Definition: misc64.hh:86
gem5::MiscRegImplDefined64::miscReg
const ArmISA::MiscRegIndex miscReg
Definition: misc64.hh:216
gem5::RegRegImmImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:56
gem5::RegRegImmImmOp64::op1
ArmISA::IntRegIndex op1
Definition: misc64.hh:64
gem5::MiscRegImmOp64::MiscRegImmOp64
MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, uint32_t _imm)
Definition: misc64.hh:158
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
gem5::MiscRegImplDefined64::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: misc64.cc:849

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