38#ifndef __ARCH_ARM_INSTS_MISC64_HH__
39#define __ARCH_ARM_INSTS_MISC64_HH__
54 ImmOp64(
const char *mnem, ArmISA::ExtMachInst _machInst,
55 OpClass __opClass, uint64_t _imm) :
68 RegOp64(
const char *mnem, ArmISA::ExtMachInst _machInst,
86 uint64_t _imm1, uint64_t _imm2) :
165 OpClass __opClass,
bool misc_read) :
174 virtual uint32_t
iss()
const {
return 0; }
222 uint32_t
iss()
const override;
241 uint32_t
iss()
const override;
254 bool misc_read,
const std::string full_mnem) :
255 MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
268 uint32_t
iss()
const override;
276 RegNone(
const char *mnem, ArmISA::ExtMachInst _machInst,
277 OpClass __opClass,
RegIndex _dest) :
292 static std::unordered_map<ArmISA::MiscRegIndex, TlbiFunc>
tlbiOps;
296 bool shareable,
TlbiAttr attrs=TlbiAttr::None);
300 bool shareable,
bool stage2=
false,
TlbiAttr attrs=TlbiAttr::None);
304 bool shareable,
bool last_level,
TlbiAttr attrs=TlbiAttr::None);
308 bool shareable,
bool last_level,
TlbiAttr attrs=TlbiAttr::None);
312 bool shareable,
TlbiAttr attrs=TlbiAttr::None);
316 bool shareable,
bool last_level,
TlbiAttr attrs=TlbiAttr::None);
320 bool shareable,
bool last_level,
TlbiAttr attrs=TlbiAttr::None);
324 bool shareable,
bool last_level,
TlbiAttr attrs=TlbiAttr::None);
328 bool shareable,
bool last_level,
TlbiAttr attrs=TlbiAttr::None);
333 TlbiOp64(
const char *mnem, ArmISA::ExtMachInst _machInst,
346 AtOp64(
const char *mnem, ArmISA::ExtMachInst _machInst,
Fault generateTrap(ArmISA::ExceptionLevel el, ArmISA::ExceptionClass ec, uint32_t iss) const
std::pair< Fault, uint64_t > performAt(ExecContext *xc, ArmISA::MiscRegIndex idx, RegVal val) const
std::pair< Fault, uint64_t > addressTranslation64(ThreadContext *tc, ArmISA::MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val) const
AtOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, RegIndex _op1)
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, uint64_t _imm)
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
RegVal miscRegImm() const
Returns the "register view" of the immediate field.
ArmISA::MiscRegIndex dest
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, uint32_t _imm)
const ArmISA::MiscRegNum64 miscReg
const std::string fullMnemonic
uint32_t iss() const override
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst, ArmISA::MiscRegNum64 &&misc_reg, RegIndex int_reg, bool misc_read, const std::string full_mnem)
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
uint32_t _iss(const ArmISA::MiscRegNum64 &misc_reg, RegIndex int_index) const
MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, bool misc_read)
Fault generateTrap(ArmISA::ExceptionLevel el) const
virtual uint32_t iss() const
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
ArmISA::MiscRegIndex dest
uint32_t iss() const override
MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, RegIndex _op1)
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
RegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _op1, uint64_t _imm1, uint64_t _imm2)
uint32_t iss() const override
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, ArmISA::MiscRegIndex _op1)
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
RegNone(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _dest)
RegOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _op1)
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint64_t _imm1, int64_t _imm2)
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, RegIndex _op2, uint64_t _imm)
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::bitset< Num_Flags > flags
Flag values for this instruction.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
static void tlbiVa(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
static void tlbiIpaS2(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
static bool fnxsAttrs(ThreadContext *tc)
static void tlbiVaa(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
TlbiOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, RegIndex _op1)
static void tlbiAsid(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, TlbiAttr attrs=TlbiAttr::None)
static void tlbiRipaS2(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
static std::unordered_map< ArmISA::MiscRegIndex, TlbiFunc > tlbiOps
void performTlbi(ExecContext *xc, ArmISA::MiscRegIndex idx, RegVal value) const
static void tlbiRvaa(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
static void tlbiRva(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None)
static void tlbiAll(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, TlbiAttr attrs=TlbiAttr::None)
static void tlbiVmall(ThreadContext *tc, RegVal value, ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, bool shareable, bool stage2=false, TlbiAttr attrs=TlbiAttr::None)
std::function< void(ThreadContext *, RegVal)> TlbiFunc
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass)
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
SecurityState
Security State.
Copyright (c) 2024 Arm Limited All rights reserved.
std::shared_ptr< FaultBase > Fault
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
The file contains the definition of a set of TLB Invalidate Instructions.