71 cacheTracking(
p.min_tracked_cache_size, size, blkSize, this)
74 fatal(
"cache block size (in bytes) `%d' must be a power of two",
77 fatal(
"Cache Size must be power of 2 for now");
79 fatal(
"Cannot use Cache Partitioning Policies with FALRU");
120 [[maybe_unused]]
auto num_erased =
124 assert(num_erased == 1);
157 if (in_caches_mask) {
158 *in_caches_mask =
mask;
175 auto iter =
tagHash.find(std::make_pair(tag, is_secure));
177 blk = (*iter).second;
181 assert(blk->
getTag() == tag);
182 assert(blk->
isSecure() == is_secure);
198 const uint64_t partition_id)
204 evict_blks.push_back(victim);
233 panic(
"Moving blocks in FALRU has not been implemented");
244 assert(blk->
next ==
nullptr);
271 assert(blk->
prev ==
nullptr);
293 static const char *SIZES[] = {
"B",
"kB",
"MB",
"GB",
"TB",
"ZB" };
295 while (size >= 1024 &&
div < (
sizeof SIZES /
sizeof *SIZES)) {
299 stream << size << SIZES[
div];
304 : statistics::
Group(parent),
306 minTrackedSize(min_size),
307 numTrackedCaches(max_size > min_size ?
309 inAllCachesMask(
mask(numTrackedCaches)),
310 boundaries(numTrackedCaches),
311 ADD_STAT(hits, statistics::units::Count::get(),
312 "The number of hits in each cache size."),
313 ADD_STAT(misses, statistics::units::Count::get(),
314 "The number of misses in each cache size."),
315 ADD_STAT(accesses, statistics::units::Count::get(),
316 "The number of accesses to the FA LRU cache.")
319 "Not enough bits (%s) in type CachesMask type to keep "
329 std::stringstream size_str;
332 hits.
subdesc(
i,
"Hits in a " + size_str.str() +
" cache");
343 unsigned curr_size = 0;
344 unsigned tracked_cache_size = minTrackedSize;
353 if (curr_size == tracked_cache_size && blk !=
tail) {
354 panic_if(boundaries[j] != blk,
"Unexpected boundary for the %d-th "
356 tracked_cache_size <<= 1;
358 in_caches_mask &= ~(1U << j);
371 unsigned curr_size = 0;
372 unsigned tracked_cache_size = minTrackedSize;
380 if (curr_size == tracked_cache_size && blk !=
tail) {
383 tracked_cache_size <<= 1;
385 in_caches_mask &= ~(1U << j);
400 for (
int i = 0;
i < numTrackedCaches;
i++) {
402 if (current_cache_mask & update_caches_mask) {
406 boundaries[
i]->inCachesMask &= ~current_cache_mask;
407 boundaries[
i] = boundaries[
i]->prev;
408 }
else if (boundaries[
i] == blk) {
411 boundaries[
i] = blk->
prev;
424 for (
int i = 0;
i < numTrackedCaches;
i++) {
426 if (current_cache_mask & update_caches_mask) {
430 boundaries[
i] = boundaries[
i]->next;
431 if (boundaries[
i] == blk) {
434 boundaries[
i] = blk->
next;
447 for (
int i = 0;
i < numTrackedCaches;
i++) {
457 hits[numTrackedCaches]++;
459 misses[numTrackedCaches]++;
std::string print() const override
Pretty-print tag, set and way, and interpret state bits to readable form including mapping to a MOESI...
uint8_t * data
Contains a copy of the data in this block for easy access.
virtual Addr getTag() const
Get tag associated to this block.
virtual bool isValid() const
Checks if the entry is valid.
Cycles is a wrapper class for representing cycle counts, i.e.
A fully associative cache block.
FALRUBlk * next
The next block in LRU order.
FALRUBlk * prev
The previous block in LRU order.
std::string print() const override
Pretty-print inCachesMask and other CacheBlk information.
CachesMask inCachesMask
A bit mask of the caches that fit this block.
void check(const FALRUBlk *head, const FALRUBlk *tail) const
Check that the tracking mechanism is in consistent state.
void recordAccess(FALRUBlk *blk)
Notify of a block access.
void init(FALRUBlk *head, FALRUBlk *tail)
Initialiaze cache blocks and the tracking mechanism.
void moveBlockToHead(FALRUBlk *blk)
Update boundaries as a block will be moved to the MRU.
void moveBlockToTail(FALRUBlk *blk)
Update boundaries as a block will be moved to the LRU.
const unsigned minTrackedSize
The smallest cache we are tracking.
CacheTracking(unsigned min_size, unsigned max_size, unsigned block_size, statistics::Group *parent)
const int numTrackedCaches
The number of different size caches being tracked.
void moveToTail(FALRUBlk *blk)
Move a cache block to the LRU position.
CacheBlk * accessBlock(const PacketPtr pkt, Cycles &lat, CachesMask *in_cache_mask)
Access block and update replacement data.
TagHash tagHash
The address hash table.
Addr extractTag(Addr addr) const override
Generate the tag from the addres.
FALRU(const Params &p)
Construct and initialize this cache tagstore.
ReplaceableEntry * findBlockBySetAndWay(int set, int way) const override
Find a block given set and way.
void moveBlock(CacheBlk *src_blk, CacheBlk *dest_blk) override
Move a block's metadata to another location decided by the replacement policy.
void invalidate(CacheBlk *blk) override
Invalidate a cache block.
void moveToHead(FALRUBlk *blk)
Move a cache block to the MRU position.
CacheBlk * findVictim(Addr addr, const bool is_secure, const std::size_t size, std::vector< CacheBlk * > &evict_blks, const uint64_t partition_id=0) override
Find replacement victim based on address.
CacheBlk * findBlock(Addr addr, bool is_secure) const override
Find the block in the cache, do not update the replacement data.
CacheTracking cacheTracking
void tagsInit() override
Initialize blocks as FALRUBlk instances.
FALRUBlk * tail
The LRU block.
FALRUBlk * head
The MRU block.
void insertBlock(const PacketPtr pkt, CacheBlk *blk) override
Insert the new block into the cache and update replacement data.
FALRUBlk * blks
The cache blocks.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
A replaceable entry is a basic entry in a 2d table-like structure that needs to have replacement func...
virtual void setPosition(const uint32_t set, const uint32_t way)
Set both the set and way.
bool isSecure() const
Check if this block holds data from the secure memory space.
Derived & subname(off_type index, const std::string &name)
Set the subfield name for the given index, and marks this stat to print at the end of simulation.
Derived & subdesc(off_type index, const std::string &desc)
Set the subfield description for the given index and marks this stat to print at the end of simulatio...
Derived & init(size_type size)
Set this vector to have the given size.
Declaration of a fully associative LRU tag store.
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
statistics::Vector hits
Hits in each cache.
statistics::Vector misses
Misses in each cache.
static constexpr std::enable_if_t< std::is_integral_v< T >, int > floorLog2(T x)
static constexpr bool isPowerOf2(const T &n)
#define panic(...)
This implements a cprintf based panic() function.
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
#define fatal(...)
This implements a cprintf based fatal() function.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Declares a basic cache interface BaseCache.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
std::string csprintf(const char *format, const Args &...args)
void printSize(std::ostream &stream, size_t size)