gem5  v21.1.0.2
noncoherent_cache.cc
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41 
48 
49 #include <cassert>
50 
51 #include "base/logging.hh"
52 #include "base/trace.hh"
53 #include "base/types.hh"
54 #include "debug/Cache.hh"
55 #include "mem/cache/cache_blk.hh"
56 #include "mem/cache/mshr.hh"
57 #include "params/NoncoherentCache.hh"
58 
59 namespace gem5
60 {
61 
62 NoncoherentCache::NoncoherentCache(const NoncoherentCacheParams &p)
63  : BaseCache(p, p.system->cacheLineSize())
64 {
65  assert(p.tags);
66  assert(p.replacement_policy);
67 }
68 
69 void
71 {
72  // As this a non-coherent cache located below the point of
73  // coherency, we do not expect requests that are typically used to
74  // keep caches coherent (e.g., InvalidateReq or UpdateReq).
75  assert(pkt->isRead() || pkt->isWrite());
76  BaseCache::satisfyRequest(pkt, blk);
77 }
78 
79 bool
81  PacketList &writebacks)
82 {
83  bool success = BaseCache::access(pkt, blk, lat, writebacks);
84 
85  if (pkt->isWriteback() || pkt->cmd == MemCmd::WriteClean) {
86  assert(blk && blk->isValid());
87  // Writeback and WriteClean can allocate and fill even if the
88  // referenced block was not present or it was invalid. If that
89  // is the case, make sure that the new block is marked as
90  // writable
92  }
93 
94  return success;
95 }
96 
97 void
99 {
100  while (!writebacks.empty()) {
101  PacketPtr wb_pkt = writebacks.front();
102  allocateWriteBuffer(wb_pkt, forward_time);
103  writebacks.pop_front();
104  }
105 }
106 
107 void
109 {
110  while (!writebacks.empty()) {
111  PacketPtr wb_pkt = writebacks.front();
112  memSidePort.sendAtomic(wb_pkt);
113  writebacks.pop_front();
114  delete wb_pkt;
115  }
116 }
117 
118 void
120  Tick forward_time, Tick request_time)
121 {
122  // miss
123  Addr blk_addr = pkt->getBlockAddr(blkSize);
124  MSHR *mshr = mshrQueue.findMatch(blk_addr, pkt->isSecure(), false);
125 
126  // We can always write to a non coherent cache if the block is
127  // present and therefore if we have reached this point then the
128  // block should not be in the cache.
129  assert(mshr || !blk || !blk->isValid());
130 
131  BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time);
132 }
133 
134 void
136 {
137  panic_if(pkt->cacheResponding(), "Should not see packets where cache "
138  "is responding");
139 
140  panic_if(!(pkt->isRead() || pkt->isWrite()),
141  "Should only see read and writes at non-coherent cache\n");
142 
144 }
145 
146 PacketPtr
148  bool needs_writable,
149  bool is_whole_line_write) const
150 {
151  // We also fill for writebacks from the coherent caches above us,
152  // and they do not need responses
153  assert(cpu_pkt->needsResponse());
154 
155  // A miss can happen only due to missing block
156  assert(!blk || !blk->isValid());
157 
158  PacketPtr pkt = new Packet(cpu_pkt->req, MemCmd::ReadReq, blkSize);
159 
160  // the packet should be block aligned
161  assert(pkt->getAddr() == pkt->getBlockAddr(blkSize));
162 
163  pkt->allocate();
164  DPRINTF(Cache, "%s created %s from %s\n", __func__, pkt->print(),
165  cpu_pkt->print());
166  return pkt;
167 }
168 
169 
170 Cycles
172  PacketList &writebacks)
173 {
174  PacketPtr bus_pkt = createMissPacket(pkt, blk, true,
175  pkt->isWholeLineWrite(blkSize));
176  DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print());
177 
178  Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt));
179 
180  assert(bus_pkt->isResponse());
181  // At the moment the only supported downstream requests we issue
182  // are ReadReq and therefore here we should only see the
183  // corresponding responses
184  assert(bus_pkt->isRead());
185  assert(pkt->cmd != MemCmd::UpgradeResp);
186  assert(!bus_pkt->isInvalidate());
187  assert(!bus_pkt->hasSharers());
188 
189  // We are now dealing with the response handling
190  DPRINTF(Cache, "Receive response: %s\n", bus_pkt->print());
191 
192  if (!bus_pkt->isError()) {
193  // Any reponse that does not have an error should be filling,
194  // afterall it is a read response
195  DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
196  bus_pkt->getAddr());
197  blk = handleFill(bus_pkt, blk, writebacks, allocOnFill(bus_pkt->cmd));
198  assert(blk);
199  }
200  satisfyRequest(pkt, blk);
201 
202  maintainClusivity(true, blk);
203 
204  // Use the separate bus_pkt to generate response to pkt and
205  // then delete it.
206  if (!pkt->isWriteback() && pkt->cmd != MemCmd::WriteClean) {
207  assert(pkt->needsResponse());
208  pkt->makeAtomicResponse();
209  if (bus_pkt->isError()) {
210  pkt->copyError(bus_pkt);
211  }
212  }
213 
214  delete bus_pkt;
215 
216  return latency;
217 }
218 
219 Tick
221 {
222  panic_if(pkt->cacheResponding(), "Should not see packets where cache "
223  "is responding");
224 
225  panic_if(!(pkt->isRead() || pkt->isWrite()),
226  "Should only see read and writes at non-coherent cache\n");
227 
228  return BaseCache::recvAtomic(pkt);
229 }
230 
231 
232 void
234 {
235  panic_if(!from_cpu_side, "Non-coherent cache received functional snoop"
236  " request\n");
237 
238  BaseCache::functionalAccess(pkt, from_cpu_side);
239 }
240 
241 void
243  CacheBlk *blk)
244 {
245  // First offset for critical word first calculations
246  const int initial_offset = mshr->getTarget()->pkt->getOffset(blkSize);
247 
248  MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
249  for (auto &target: targets) {
250  Packet *tgt_pkt = target.pkt;
251 
252  switch (target.source) {
254  // handle deferred requests comming from a cache or core
255  // above
256 
257  Tick completion_time;
258  // Here we charge on completion_time the delay of the xbar if the
259  // packet comes from it, charged on headerDelay.
260  completion_time = pkt->headerDelay;
261 
262  satisfyRequest(tgt_pkt, blk);
263 
264  // How many bytes past the first request is this one
265  int transfer_offset;
266  transfer_offset = tgt_pkt->getOffset(blkSize) - initial_offset;
267  if (transfer_offset < 0) {
268  transfer_offset += blkSize;
269  }
270  // If not critical word (offset) return payloadDelay.
271  // responseLatency is the latency of the return path
272  // from lower level caches/memory to an upper level cache or
273  // the core.
274  completion_time += clockEdge(responseLatency) +
275  (transfer_offset ? pkt->payloadDelay : 0);
276 
277  assert(tgt_pkt->req->requestorId() < system->maxRequestors());
278  stats.cmdStats(tgt_pkt).missLatency[tgt_pkt->req->requestorId()] +=
279  completion_time - target.recvTime;
280 
281  tgt_pkt->makeTimingResponse();
282  if (pkt->isError())
283  tgt_pkt->copyError(pkt);
284 
285  // Reset the bus additional time as it is now accounted for
286  tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
287  cpuSidePort.schedTimingResp(tgt_pkt, completion_time);
288  break;
289 
291  // handle deferred requests comming from a prefetcher
292  // attached to this cache
293  assert(tgt_pkt->cmd == MemCmd::HardPFReq);
294 
295  if (blk)
296  blk->setPrefetched();
297 
298  // We have filled the block and the prefetcher does not
299  // require responses.
300  delete tgt_pkt;
301  break;
302 
303  default:
304  // we should never see FromSnoop Targets as this is a
305  // non-coherent cache
306  panic("Illegal target->source enum %d\n", target.source);
307  }
308  }
309 
310  // Reponses are filling and bring in writable blocks, therefore
311  // there should be no deferred targets and all the non-deferred
312  // targets are now serviced.
313  assert(mshr->getNumTargets() == 0);
314 }
315 
316 void
318 {
319  assert(pkt->isResponse());
320  // At the moment the only supported downstream requests we issue
321  // are ReadReq and therefore here we should only see the
322  // corresponding responses
323  assert(pkt->isRead());
324  assert(pkt->cmd != MemCmd::UpgradeResp);
325  assert(!pkt->isInvalidate());
326  // This cache is non-coherent and any memories below are
327  // non-coherent too (non-coherent caches or the main memory),
328  // therefore the fetched block can be marked as writable.
329  assert(!pkt->hasSharers());
330 
332 }
333 
334 PacketPtr
336 {
337  // A dirty block is always written back.
338 
339  // A clean block can we written back, if we turned on writebacks
340  // for clean blocks. This could be useful if there is a cache
341  // below and we want to make sure the block is cached but if the
342  // memory below is the main memory WritebackCleans are
343  // unnecessary.
344 
345  // If we clean writebacks are not enabled, we do not take any
346  // further action for evictions of clean blocks (i.e., CleanEvicts
347  // are unnecessary).
349  writebackBlk(blk) : nullptr;
350 
351  invalidateBlock(blk);
352 
353  return pkt;
354 }
355 
356 } // namespace gem5
gem5::Packet::getBlockAddr
Addr getBlockAddr(unsigned int blk_size) const
Definition: packet.hh:805
gem5::NoncoherentCache::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Performs the access specified by the request.
Definition: noncoherent_cache.cc:220
gem5::MSHR
Miss Status and handling Register.
Definition: mshr.hh:74
gem5::NoncoherentCache::recvTimingResp
void recvTimingResp(PacketPtr pkt) override
Handles a response (cache line fill/write ack) from the bus.
Definition: noncoherent_cache.cc:317
gem5::NoncoherentCache::recvTimingReq
void recvTimingReq(PacketPtr pkt) override
Performs the access specified by the request.
Definition: noncoherent_cache.cc:135
gem5::BaseCache::cpuSidePort
CpuSidePort cpuSidePort
Definition: base.hh:338
gem5::BaseCache::handleTimingReqMiss
virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, Tick request_time)=0
gem5::NoncoherentCache::serviceMSHRTargets
void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk) override
Service non-deferred MSHR targets using the received response.
Definition: noncoherent_cache.cc:242
gem5::BaseCache::invalidateBlock
void invalidateBlock(CacheBlk *blk)
Invalidate a cache block.
Definition: base.cc:1587
gem5::MemCmd::WriteClean
@ WriteClean
Definition: packet.hh:94
gem5::Packet::getOffset
Addr getOffset(unsigned int blk_size) const
Definition: packet.hh:800
gem5::BaseCache::access
virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks)
Does all the processing necessary to perform the provided request.
Definition: base.cc:1153
gem5::NoncoherentCache::NoncoherentCache
NoncoherentCache(const NoncoherentCacheParams &p)
Definition: noncoherent_cache.cc:62
gem5::QueueEntry::Target::pkt
const PacketPtr pkt
Pending request packet.
Definition: queue_entry.hh:93
gem5::BaseCache::recvTimingResp
virtual void recvTimingResp(PacketPtr pkt)
Handles a response (cache line fill/write ack) from the bus.
Definition: base.cc:420
mshr.hh
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::RequestPort::sendAtomic
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
Definition: port.hh:464
gem5::NoncoherentCache::doWritebacks
void doWritebacks(PacketList &writebacks, Tick forward_time) override
Insert writebacks into the write buffer.
Definition: noncoherent_cache.cc:98
gem5::NoncoherentCache::handleAtomicReqMiss
Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) override
Handle a request in atomic mode that missed in this cache.
Definition: noncoherent_cache.cc:171
gem5::Packet::isWriteback
bool isWriteback() const
Definition: packet.hh:602
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:646
gem5::Packet::copyError
void copyError(Packet *pkt)
Definition: packet.hh:779
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::Packet::isSecure
bool isSecure() const
Definition: packet.hh:810
gem5::Packet::hasSharers
bool hasSharers() const
Definition: packet.hh:673
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::NoncoherentCache::createMissPacket
PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, bool needs_writable, bool is_whole_line_write) const override
Create an appropriate downstream bus request packet.
Definition: noncoherent_cache.cc:147
gem5::NoncoherentCache::access
bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks) override
Does all the processing necessary to perform the provided request.
Definition: noncoherent_cache.cc:80
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::CacheBlk::WritableBit
@ WritableBit
write permission
Definition: cache_blk.hh:80
gem5::MemCmd::HardPFReq
@ HardPFReq
Definition: packet.hh:98
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
gem5::CacheBlk::setPrefetched
void setPrefetched()
Marks this blocks as a recently prefetched block.
Definition: cache_blk.hh:258
gem5::CacheBlk
A Basic Cache block.
Definition: cache_blk.hh:70
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::MSHR::Target::FromCPU
@ FromCPU
Definition: mshr.hh:135
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::NoncoherentCache::evictBlock
GEM5_NO_DISCARD PacketPtr evictBlock(CacheBlk *blk) override
Evict a cache block.
Definition: noncoherent_cache.cc:335
gem5::System::maxRequestors
RequestorID maxRequestors()
Get the number of requestors registered in the system.
Definition: system.hh:518
gem5::Packet::isRead
bool isRead() const
Definition: packet.hh:582
gem5::BaseCache::allocateWriteBuffer
void allocateWriteBuffer(PacketPtr pkt, Tick time)
Definition: base.hh:1182
gem5::Packet::print
void print(std::ostream &o, int verbosity=0, const std::string &prefix="") const
Definition: packet.cc:373
gem5::BaseCache::stats
gem5::BaseCache::CacheStats stats
gem5::BaseCache
A basic cache interface.
Definition: base.hh:95
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::NoncoherentCache::functionalAccess
void functionalAccess(PacketPtr pkt, bool from_cpu_side) override
Performs the access specified by the request.
Definition: noncoherent_cache.cc:233
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MemCmd::UpgradeResp
@ UpgradeResp
Definition: packet.hh:104
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::BaseCache::blkSize
const unsigned blkSize
Block size of this cache.
Definition: base.hh:888
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::BaseCache::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Performs the access specified by the request.
Definition: base.cc:559
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::CacheBlk::setCoherenceBits
void setCoherenceBits(unsigned bits)
Sets the corresponding coherence bits.
Definition: cache_blk.hh:220
noncoherent_cache.hh
gem5::Queue::findMatch
Entry * findMatch(Addr blk_addr, bool is_secure, bool ignore_uncacheable=true) const
Find the first entry that matches the provided address.
Definition: queue.hh:168
gem5::BaseCache::CacheCmdStats::missLatency
statistics::Vector missLatency
Total number of cycles per thread/command spent waiting for a miss.
Definition: base.hh:1012
gem5::BaseCache::allocOnFill
bool allocOnFill(MemCmd cmd) const
Determine whether we should allocate on a fill or not.
Definition: base.hh:441
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::MSHR::TargetList
Definition: mshr.hh:169
gem5::Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:597
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Packet::isError
bool isError() const
Definition: packet.hh:610
gem5::CacheBlk::DirtyBit
@ DirtyBit
dirty (modified)
Definition: cache_blk.hh:87
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::BaseCache::recvTimingReq
virtual void recvTimingReq(PacketPtr pkt)
Performs the access specified by the request.
Definition: base.cc:350
gem5::Cache
A coherent cache that can be arranged in flexible topologies.
Definition: cache.hh:67
gem5::BaseCache::maintainClusivity
void maintainClusivity(bool from_cache, CacheBlk *blk)
Maintain the clusivity of this cache by potentially invalidating a block.
Definition: base.cc:1422
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::Packet::makeTimingResponse
void makeTimingResponse()
Definition: packet.hh:1049
cache_blk.hh
gem5::Packet::allocate
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1326
gem5::BaseCache::CacheStats::cmdStats
CacheCmdStats & cmdStats(const PacketPtr p)
Definition: base.hh:1043
types.hh
gem5::MSHR::getNumTargets
int getNumTargets() const
Returns the current number of allocated targets.
Definition: mshr.hh:430
gem5::BaseCache::system
System * system
System we are currently operating in.
Definition: base.hh:986
gem5::BaseCache::mshrQueue
MSHRQueue mshrQueue
Miss status registers.
Definition: base.hh:344
gem5::BaseCache::memSidePort
MemSidePort memSidePort
Definition: base.hh:339
gem5::BaseCache::writebackClean
const bool writebackClean
Determine if clean lines should be written back or not.
Definition: base.hh:675
gem5::CacheBlk::isSet
bool isSet(unsigned bits) const
Checks the given coherence bits are set.
Definition: cache_blk.hh:239
logging.hh
gem5::MSHR::extractServiceableTargets
TargetList extractServiceableTargets(PacketPtr pkt)
Extracts the subset of the targets that can be serviced given a received response.
Definition: mshr.cc:547
trace.hh
gem5::MSHR::Target::FromPrefetcher
@ FromPrefetcher
Definition: mshr.hh:137
gem5::Clocked::ticksToCycles
Cycles ticksToCycles(Tick t) const
Definition: clocked_object.hh:222
std::list
STL list class.
Definition: stl.hh:51
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::NoncoherentCache::doWritebacksAtomic
void doWritebacksAtomic(PacketList &writebacks) override
Send writebacks down the memory hierarchy in atomic mode.
Definition: noncoherent_cache.cc:108
gem5::NoncoherentCache::satisfyRequest
void satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool deferred_response=false, bool pending_downgrade=false) override
Perform any necessary updates to the block and perform any data exchange between the packet and the b...
Definition: noncoherent_cache.cc:70
gem5::QueuedResponsePort::schedTimingResp
void schedTimingResp(PacketPtr pkt, Tick when)
Schedule the sending of a timing response.
Definition: qport.hh:93
gem5::BaseCache::functionalAccess
virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side)
Performs the access specified by the request.
Definition: base.cc:639
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::NoncoherentCache::handleTimingReqMiss
void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, Tick request_time) override
Definition: noncoherent_cache.cc:119
gem5::MSHR::getTarget
QueueEntry::Target * getTarget() override
Returns a reference to the first target.
Definition: mshr.hh:457
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:587
gem5::BaseCache::handleFill
CacheBlk * handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, bool allocate)
Handle a fill operation caused by a received packet.
Definition: base.cc:1434
gem5::Packet::isWholeLineWrite
bool isWholeLineWrite(unsigned blk_size)
Definition: packet.hh:614
gem5::BaseCache::writebackBlk
PacketPtr writebackBlk(CacheBlk *blk)
Create a writeback request for the given block.
Definition: base.cc:1616
gem5::TaggedEntry::isValid
virtual bool isValid() const
Checks if the entry is valid.
Definition: tagged_entry.hh:57
gem5::Packet::isInvalidate
bool isInvalidate() const
Definition: packet.hh:598
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::BaseCache::satisfyRequest
virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool deferred_response=false, bool pending_downgrade=false)
Perform any necessary updates to the block and perform any data exchange between the packet and the b...
Definition: base.cc:1012
gem5::BaseCache::responseLatency
const Cycles responseLatency
The latency of sending reponse to its upper level cache/core on a linefill.
Definition: base.hh:917

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