50 #include "debug/Cache.hh"
51 #include "debug/CacheComp.hh"
52 #include "debug/CachePort.hh"
53 #include "debug/CacheRepl.hh"
54 #include "debug/CacheVerbose.hh"
55 #include "debug/HWPrefetch.hh"
62 #include "params/BaseCache.hh"
63 #include "params/WriteAllocator.hh"
71 const std::string &_label)
73 queue(*_cache, *this, true, _label),
74 blocked(false), mustSendRetry(false),
95 lookupLatency(
p.tag_latency),
96 dataLatency(
p.data_latency),
97 forwardLatency(
p.tag_latency),
98 fillLatency(
p.data_latency),
99 responseLatency(
p.response_latency),
100 sequentialAccess(
p.sequential_access),
101 numTarget(
p.tgts_per_mshr),
103 clusivity(
p.clusivity),
104 isReadOnly(
p.is_read_only),
105 replaceExpansions(
p.replace_expansions),
106 moveContractions(
p.move_contractions),
109 noTargetMSHR(
nullptr),
110 missCount(
p.max_miss_count),
111 addrRanges(
p.addr_ranges.begin(),
p.addr_ranges.end()),
128 prefetcher->setCache(
this);
131 "The tags of compressed cache %s must derive from CompressedTags",
134 "Compressed cache %s does not have a compression algorithm",
name());
136 compressor->setCache(
this);
148 DPRINTF(CachePort,
"Port is blocking new requests\n");
154 DPRINTF(CachePort,
"Port descheduled retry\n");
163 DPRINTF(CachePort,
"Port is accepting new requests\n");
167 owner.schedule(sendRetryEvent,
curTick() + 1);
174 DPRINTF(CachePort,
"Port is sending retry\n");
177 mustSendRetry =
false;
195 fatal(
"Cache ports on %s are not connected\n",
name());
203 if (if_name ==
"mem_side") {
205 }
else if (if_name ==
"cpu_side") {
216 if (
r.contains(
addr)) {
293 DPRINTF(
Cache,
"%s satisfied %s, no response needed\n", __func__,
306 Tick forward_time,
Tick request_time)
309 pkt && pkt->
isWrite() && !pkt->
req->isUncacheable()) {
391 pkt->
req->isCacheMaintenance());
425 bool satisfied =
false;
430 satisfied =
access(pkt, blk, lat, writebacks);
494 "%s saw a non-zero packet delay\n",
name());
496 const bool is_error = pkt->
isError();
499 DPRINTF(
Cache,
"%s: Cache received %s with error\n", __func__,
509 assert(pkt->
req->isUncacheable());
528 if (pkt->
req->isUncacheable()) {
550 if (is_fill && !is_error) {
551 DPRINTF(
Cache,
"Block for addr %#llx being updated in Cache\n",
556 blk =
handleFill(pkt, blk, writebacks, allocate);
557 assert(blk !=
nullptr);
577 !pkt->
req->isCacheInvalidate()) {
610 Tick next_pf_time = std::max(
627 DPRINTF(CacheVerbose,
"%s: Leaving with %s\n", __func__, pkt->
print());
645 bool satisfied =
access(pkt, blk, lat, writebacks);
652 DPRINTF(CacheVerbose,
"%s: packet %s found block: %s\n",
655 writebacks.push_back(wb_pkt);
662 assert(writebacks.empty());
730 bool have_data = blk && blk->
isValid()
740 bool done = have_dirty ||
746 DPRINTF(CacheVerbose,
"%s: %s %s%s%s\n", __func__, pkt->
print(),
747 (blk && blk->
isValid()) ?
"valid " :
"",
748 have_data ?
"data " :
"", done ?
"done " :
"");
799 uint64_t overwrite_val;
801 uint64_t condition_val64;
802 uint32_t condition_val32;
807 assert(
sizeof(uint64_t) >= pkt->
getSize());
816 overwrite_mem =
true;
819 pkt->
writeData((uint8_t *)&overwrite_val);
822 if (pkt->
req->isCondSwap()) {
823 if (pkt->
getSize() ==
sizeof(uint64_t)) {
824 condition_val64 = pkt->
req->getExtraData();
825 overwrite_mem = !std::memcmp(&condition_val64, blk_data,
827 }
else if (pkt->
getSize() ==
sizeof(uint32_t)) {
828 condition_val32 = (uint32_t)pkt->
req->getExtraData();
829 overwrite_mem = !std::memcmp(&condition_val32, blk_data,
832 panic(
"Invalid size for conditional read/write\n");
836 std::memcpy(blk_data, &overwrite_val, pkt->
getSize());
862 if (conflict_mshr && conflict_mshr->
order < wq_entry->
order) {
864 return conflict_mshr;
871 }
else if (miss_mshr) {
887 return conflict_mshr;
897 assert(!miss_mshr && !wq_entry);
904 DPRINTF(HWPrefetch,
"Prefetch %#x has hit in cache, "
905 "dropped.\n", pf_addr);
910 DPRINTF(HWPrefetch,
"Prefetch %#x has hit in a MSHR, "
911 "dropped.\n", pf_addr);
916 DPRINTF(HWPrefetch,
"Prefetch %#x has hit in the "
917 "Write Buffer, dropped.\n", pf_addr);
942 bool replacement =
false;
943 for (
const auto& blk : evict_blks) {
944 if (blk->isValid()) {
965 for (
auto& blk : evict_blks) {
966 if (blk->isValid()) {
988 const auto comp_data =
990 std::size_t compression_size = comp_data->getSizeBits();
994 [[maybe_unused]]
const std::size_t prev_size =
1001 bool is_data_expansion =
false;
1002 bool is_data_contraction =
false;
1005 std::string op_name =
"";
1007 op_name =
"expansion";
1008 is_data_expansion =
true;
1011 op_name =
"contraction";
1012 is_data_contraction =
true;
1019 if (is_data_expansion || is_data_contraction) {
1021 bool victim_itself =
false;
1025 blk->
isSecure(), compression_size, evict_blks);
1034 if (blk == victim) {
1035 victim_itself =
true;
1036 auto it = std::find_if(evict_blks.begin(), evict_blks.end(),
1037 [&blk](
CacheBlk* evict_blk){ return evict_blk == blk; });
1038 evict_blks.erase(it);
1042 DPRINTF(CacheRepl,
"Data %s replacement victim: %s\n",
1043 op_name, victim->
print());
1049 for (
auto& sub_blk : superblock->
blks) {
1050 if (sub_blk->isValid() && (blk != sub_blk)) {
1051 evict_blks.push_back(sub_blk);
1061 DPRINTF(CacheComp,
"Data %s: [%s] from %d to %d bits\n",
1062 op_name, blk->
print(), prev_size, compression_size);
1074 if (is_data_expansion) {
1076 }
else if (is_data_contraction) {
1091 assert(blk && blk->
isValid());
1149 DPRINTF(CacheVerbose,
"%s for %s (write)\n", __func__, pkt->
print());
1150 }
else if (pkt->
isRead()) {
1174 DPRINTF(CacheVerbose,
"%s for %s (invalidation)\n", __func__,
1186 const Cycles lookup_lat)
const
1195 const Cycles lookup_lat)
const
1199 if (blk !=
nullptr) {
1213 if (when_ready >
tick &&
1235 "Should never see a write in a read-only cache %s\n",
1243 blk ?
"hit " + blk->
print() :
"miss");
1245 if (pkt->
req->isCacheMaintenance()) {
1318 DPRINTF(
Cache,
"Clean writeback %#llx to block with MSHR, "
1319 "dropping\n", pkt->
getAddr());
1329 const bool has_old_data = blk && blk->
isValid();
1401 const bool has_old_data = blk && blk->
isValid();
1489 pkt->
req->setExtraData(0);
1499 if (from_cache && blk && blk->
isValid() &&
1515 const bool has_old_data = blk && blk->
isValid();
1516 const std::string old_state = (debug::Cache && blk) ? blk->
print() :
"";
1537 is_secure ?
"s" :
"ns");
1547 assert(blk->
isSecure() == is_secure);
1580 "in read-only cache %s\n",
name());
1585 DPRINTF(
Cache,
"Block addr %#llx (%s) moving from %s to %s\n",
1586 addr, is_secure ?
"s" :
"ns", old_state, blk->
print());
1611 const bool is_secure = pkt->
isSecure();
1616 std::size_t blk_size_bits =
blkSize*8;
1627 pkt->
getConstPtr<uint64_t>(), compression_lat, decompression_lat);
1628 blk_size_bits = comp_data->getSizeBits();
1641 DPRINTF(CacheRepl,
"Replacement victim: %s\n", victim->
print());
1686 writebacks.push_back(pkt);
1694 "Writeback from read-only cache");
1695 assert(blk && blk->
isValid() &&
1712 DPRINTF(
Cache,
"Create Writeback %s writable: %d, dirty: %d\n",
1754 req->setFlags(dest);
1817 RequestPtr request = std::make_shared<Request>(
1838 warn_once(
"Invalidating dirty cache lines. " \
1839 "Expect things to break.\n");
1856 nextReady = std::min(nextReady,
1885 DPRINTF(CacheVerbose,
"Delaying pkt %s %llu ticks to allow "
1886 "for write coalescing\n", tgt_pkt->
print(), delay);
1910 pkt =
new Packet(tgt_pkt,
false,
true);
1945 bool pending_modified_resp = !pkt->
hasSharers() &&
1954 DPRINTF(CacheVerbose,
"%s: packet %s found block: %s\n",
1959 writebacks.push_back(wb_pkt);
1997 warn(
"*** The cache still contains dirty data. ***\n");
1998 warn(
" Make sure to drain the system using the correct flags.\n");
1999 warn(
" This checkpoint will not restore correctly " \
2000 "and dirty data in the cache will be lost!\n");
2007 bool bad_checkpoint(dirty);
2014 bool bad_checkpoint;
2016 if (bad_checkpoint) {
2017 fatal(
"Restoring from checkpoints with dirty caches is not "
2018 "supported in the classic memory system. Please remove any "
2019 "caches or drain them properly before taking checkpoints.\n");
2025 const std::string &
name)
2028 (
"number of " +
name +
" hits").c_str()),
2030 (
"number of " +
name +
" misses").c_str()),
2032 (
"number of " +
name +
" hit ticks").c_str()),
2034 (
"number of " +
name +
" miss ticks").c_str()),
2036 (
"number of " +
name +
" accesses(hits+misses)").c_str()),
2037 ADD_STAT(missRate, statistics::units::Ratio::get(),
2038 (
"miss rate for " +
name +
" accesses").c_str()),
2039 ADD_STAT(avgMissLatency, statistics::units::Rate<
2040 statistics::units::
Tick, statistics::units::
Count>::get(),
2041 (
"average " +
name +
" miss latency").c_str()),
2043 (
"number of " +
name +
" MSHR hits").c_str()),
2045 (
"number of " +
name +
" MSHR misses").c_str()),
2047 (
"number of " +
name +
" MSHR uncacheable").c_str()),
2048 ADD_STAT(mshrMissLatency, statistics::units::
Tick::get(),
2049 (
"number of " +
name +
" MSHR miss ticks").c_str()),
2050 ADD_STAT(mshrUncacheableLatency, statistics::units::
Tick::get(),
2051 (
"number of " +
name +
" MSHR uncacheable ticks").c_str()),
2052 ADD_STAT(mshrMissRate, statistics::units::Ratio::get(),
2053 (
"mshr miss rate for " +
name +
" accesses").c_str()),
2054 ADD_STAT(avgMshrMissLatency, statistics::units::Rate<
2055 statistics::units::
Tick, statistics::units::
Count>::get(),
2056 (
"average " +
name +
" mshr miss latency").c_str()),
2057 ADD_STAT(avgMshrUncacheableLatency, statistics::units::Rate<
2058 statistics::units::
Tick, statistics::units::
Count>::get(),
2059 (
"average " +
name +
" mshr uncacheable latency").c_str())
2066 using namespace statistics;
2073 .init(max_requestors)
2076 for (
int i = 0;
i < max_requestors;
i++) {
2082 .init(max_requestors)
2085 for (
int i = 0;
i < max_requestors;
i++) {
2091 .init(max_requestors)
2094 for (
int i = 0;
i < max_requestors;
i++) {
2100 .init(max_requestors)
2103 for (
int i = 0;
i < max_requestors;
i++) {
2109 accesses = hits + misses;
2110 for (
int i = 0;
i < max_requestors;
i++) {
2116 missRate = misses / accesses;
2117 for (
int i = 0;
i < max_requestors;
i++) {
2123 avgMissLatency = missLatency / misses;
2124 for (
int i = 0;
i < max_requestors;
i++) {
2131 .init(max_requestors)
2134 for (
int i = 0;
i < max_requestors;
i++) {
2140 .init(max_requestors)
2143 for (
int i = 0;
i < max_requestors;
i++) {
2149 .init(max_requestors)
2152 for (
int i = 0;
i < max_requestors;
i++) {
2158 .init(max_requestors)
2161 for (
int i = 0;
i < max_requestors;
i++) {
2166 mshrUncacheableLatency
2167 .init(max_requestors)
2170 for (
int i = 0;
i < max_requestors;
i++) {
2176 mshrMissRate = mshrMisses / accesses;
2178 for (
int i = 0;
i < max_requestors;
i++) {
2184 avgMshrMissLatency = mshrMissLatency / mshrMisses;
2185 for (
int i = 0;
i < max_requestors;
i++) {
2191 avgMshrUncacheableLatency = mshrUncacheableLatency / mshrUncacheable;
2192 for (
int i = 0;
i < max_requestors;
i++) {
2198 : statistics::
Group(&
c), cache(
c),
2201 "number of demand (read+write) hits"),
2203 "number of overall hits"),
2204 ADD_STAT(demandHitLatency, statistics::units::
Tick::get(),
2205 "number of demand (read+write) hit ticks"),
2206 ADD_STAT(overallHitLatency, statistics::units::
Tick::get(),
2207 "number of overall hit ticks"),
2209 "number of demand (read+write) misses"),
2211 "number of overall misses"),
2212 ADD_STAT(demandMissLatency, statistics::units::
Tick::get(),
2213 "number of demand (read+write) miss ticks"),
2214 ADD_STAT(overallMissLatency, statistics::units::
Tick::get(),
2215 "number of overall miss ticks"),
2217 "number of demand (read+write) accesses"),
2219 "number of overall (read+write) accesses"),
2220 ADD_STAT(demandMissRate, statistics::units::Ratio::get(),
2221 "miss rate for demand accesses"),
2222 ADD_STAT(overallMissRate, statistics::units::Ratio::get(),
2223 "miss rate for overall accesses"),
2224 ADD_STAT(demandAvgMissLatency, statistics::units::Rate<
2225 statistics::units::
Tick, statistics::units::
Count>::get(),
2226 "average overall miss latency in ticks"),
2227 ADD_STAT(overallAvgMissLatency, statistics::units::Rate<
2228 statistics::units::
Tick, statistics::units::
Count>::get(),
2229 "average overall miss latency"),
2230 ADD_STAT(blockedCycles, statistics::units::Cycle::get(),
2231 "number of cycles access was blocked"),
2233 "number of times access was blocked"),
2234 ADD_STAT(avgBlocked, statistics::units::Rate<
2235 statistics::units::Cycle, statistics::units::
Count>::get(),
2236 "average number of cycles each access was blocked"),
2238 "number of writebacks"),
2240 "number of demand (read+write) MSHR hits"),
2242 "number of overall MSHR hits"),
2244 "number of demand (read+write) MSHR misses"),
2245 ADD_STAT(overallMshrMisses, statistics::units::
Count::get(),
2246 "number of overall MSHR misses"),
2247 ADD_STAT(overallMshrUncacheable, statistics::units::
Count::get(),
2248 "number of overall MSHR uncacheable misses"),
2249 ADD_STAT(demandMshrMissLatency, statistics::units::
Tick::get(),
2250 "number of demand (read+write) MSHR miss ticks"),
2251 ADD_STAT(overallMshrMissLatency, statistics::units::
Tick::get(),
2252 "number of overall MSHR miss ticks"),
2253 ADD_STAT(overallMshrUncacheableLatency, statistics::units::
Tick::get(),
2254 "number of overall MSHR uncacheable ticks"),
2255 ADD_STAT(demandMshrMissRate, statistics::units::Ratio::get(),
2256 "mshr miss ratio for demand accesses"),
2257 ADD_STAT(overallMshrMissRate, statistics::units::Ratio::get(),
2258 "mshr miss ratio for overall accesses"),
2259 ADD_STAT(demandAvgMshrMissLatency, statistics::units::Rate<
2260 statistics::units::
Tick, statistics::units::
Count>::get(),
2261 "average overall mshr miss latency"),
2262 ADD_STAT(overallAvgMshrMissLatency, statistics::units::Rate<
2263 statistics::units::
Tick, statistics::units::
Count>::get(),
2264 "average overall mshr miss latency"),
2265 ADD_STAT(overallAvgMshrUncacheableLatency, statistics::units::Rate<
2266 statistics::units::
Tick, statistics::units::
Count>::get(),
2267 "average overall mshr uncacheable latency"),
2269 "number of replacements"),
2271 "number of data expansions"),
2273 "number of data contractions"),
2274 cmd(
MemCmd::NUM_MEM_CMDS)
2283 using namespace statistics;
2290 for (
auto &cs : cmd)
2291 cs->regStatsFromParent();
2296 #define SUM_DEMAND(s) \
2297 (cmd[MemCmd::ReadReq]->s + cmd[MemCmd::WriteReq]->s + \
2298 cmd[MemCmd::WriteLineReq]->s + cmd[MemCmd::ReadExReq]->s + \
2299 cmd[MemCmd::ReadCleanReq]->s + cmd[MemCmd::ReadSharedReq]->s)
2302 #define SUM_NON_DEMAND(s) \
2303 (cmd[MemCmd::SoftPFReq]->s + cmd[MemCmd::HardPFReq]->s + \
2304 cmd[MemCmd::SoftPFExReq]->s)
2308 for (
int i = 0;
i < max_requestors;
i++) {
2314 for (
int i = 0;
i < max_requestors;
i++) {
2320 for (
int i = 0;
i < max_requestors;
i++) {
2326 for (
int i = 0;
i < max_requestors;
i++) {
2332 for (
int i = 0;
i < max_requestors;
i++) {
2337 overallMissLatency = demandMissLatency +
SUM_NON_DEMAND(missLatency);
2338 for (
int i = 0;
i < max_requestors;
i++) {
2344 for (
int i = 0;
i < max_requestors;
i++) {
2348 overallHitLatency = demandHitLatency +
SUM_NON_DEMAND(hitLatency);
2349 for (
int i = 0;
i < max_requestors;
i++) {
2354 demandAccesses = demandHits + demandMisses;
2355 for (
int i = 0;
i < max_requestors;
i++) {
2360 overallAccesses = overallHits + overallMisses;
2361 for (
int i = 0;
i < max_requestors;
i++) {
2366 demandMissRate = demandMisses / demandAccesses;
2367 for (
int i = 0;
i < max_requestors;
i++) {
2372 overallMissRate = overallMisses / overallAccesses;
2373 for (
int i = 0;
i < max_requestors;
i++) {
2378 demandAvgMissLatency = demandMissLatency / demandMisses;
2379 for (
int i = 0;
i < max_requestors;
i++) {
2384 overallAvgMissLatency = overallMissLatency / overallMisses;
2385 for (
int i = 0;
i < max_requestors;
i++) {
2406 avgBlocked = blockedCycles / blockedCauses;
2409 .init(max_requestors)
2412 for (
int i = 0;
i < max_requestors;
i++) {
2418 for (
int i = 0;
i < max_requestors;
i++) {
2424 for (
int i = 0;
i < max_requestors;
i++) {
2430 for (
int i = 0;
i < max_requestors;
i++) {
2435 overallMshrMisses = demandMshrMisses +
SUM_NON_DEMAND(mshrMisses);
2436 for (
int i = 0;
i < max_requestors;
i++) {
2441 demandMshrMissLatency =
SUM_DEMAND(mshrMissLatency);
2442 for (
int i = 0;
i < max_requestors;
i++) {
2447 overallMshrMissLatency =
2449 for (
int i = 0;
i < max_requestors;
i++) {
2454 overallMshrUncacheable =
2456 for (
int i = 0;
i < max_requestors;
i++) {
2462 overallMshrUncacheableLatency =
2465 for (
int i = 0;
i < max_requestors;
i++) {
2470 demandMshrMissRate = demandMshrMisses / demandAccesses;
2471 for (
int i = 0;
i < max_requestors;
i++) {
2476 overallMshrMissRate = overallMshrMisses / overallAccesses;
2477 for (
int i = 0;
i < max_requestors;
i++) {
2482 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
2483 for (
int i = 0;
i < max_requestors;
i++) {
2488 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
2489 for (
int i = 0;
i < max_requestors;
i++) {
2494 overallAvgMshrUncacheableLatency =
2495 overallMshrUncacheableLatency / overallMshrUncacheable;
2496 for (
int i = 0;
i < max_requestors;
i++) {
2497 overallAvgMshrUncacheableLatency.subname(
i,
2524 assert(!cache->system->bypassCaches());
2529 cache->recvTimingSnoopResp(pkt);
2540 }
else if (
blocked || mustSendRetry) {
2542 mustSendRetry =
true;
2545 mustSendRetry =
false;
2554 if (cache->system->bypassCaches()) {
2557 [[maybe_unused]]
bool success = cache->memSidePort.sendTimingReq(pkt);
2560 }
else if (tryTiming(pkt)) {
2561 cache->recvTimingReq(pkt);
2570 if (cache->system->bypassCaches()) {
2572 return cache->memSidePort.sendAtomic(pkt);
2574 return cache->recvAtomic(pkt);
2581 if (cache->system->bypassCaches()) {
2584 cache->memSidePort.sendFunctional(pkt);
2589 cache->functionalAccess(pkt,
true);
2595 return cache->getAddrRanges();
2601 const std::string &_label)
2614 cache->recvTimingResp(pkt);
2623 assert(!cache->system->bypassCaches());
2626 cache->recvTimingSnoopReq(pkt);
2633 assert(!cache->system->bypassCaches());
2635 return cache->recvAtomicSnoop(pkt);
2642 assert(!cache->system->bypassCaches());
2647 cache->functionalAccess(pkt,
false);
2654 assert(!waitingOnRetry);
2659 assert(deferredPacketReadyTime() ==
MaxTick);
2662 QueueEntry* entry = cache.getNextQueueEntry();
2681 if (!waitingOnRetry) {
2682 schedSendEvent(cache.nextQueueReadyTime());
2688 const std::string &_label)
2690 _reqQueue(*_cache, *this, _snoopRespQueue, _label),
2691 _snoopRespQueue(*_cache, *this, true, _label), cache(_cache)
2700 if (nextAddr == write_addr) {
2701 delayCtr[blk_addr] = delayThreshold;
2703 if (
mode != WriteMode::NO_ALLOCATE) {
2704 byteCount += write_size;
2707 if (
mode == WriteMode::ALLOCATE &&
2708 byteCount > coalesceLimit) {
2709 mode = WriteMode::COALESCE;
2711 }
else if (
mode == WriteMode::COALESCE &&
2712 byteCount > noAllocateLimit) {
2715 mode = WriteMode::NO_ALLOCATE;
2722 byteCount = write_size;
2723 mode = WriteMode::ALLOCATE;
2724 resetDelay(blk_addr);
2726 nextAddr = write_addr + write_size;
virtual void sendDeferredPacket()
Override the normal sendDeferredPacket and do not only consider the transmit list (used for responses...
A cache request port is used for the memory-side port of the cache, and in addition to the basic timi...
A cache response port is used for the CPU-side port of the cache, and it is basically a simple timing...
void clearBlocked()
Return to normal operation and accept new requests.
EventFunctionWrapper sendRetryEvent
CacheResponsePort(const std::string &_name, BaseCache *_cache, const std::string &_label)
void setBlocked()
Do not accept any new requests.
CpuSidePort(const std::string &_name, BaseCache *_cache, const std::string &_label)
virtual bool recvTimingSnoopResp(PacketPtr pkt) override
Receive a timing snoop response from the peer.
virtual Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
virtual bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the peer.
virtual bool tryTiming(PacketPtr pkt) override
Availability request from the peer.
virtual void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
virtual AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
virtual Tick recvAtomicSnoop(PacketPtr pkt)
Receive an atomic snoop request packet from our peer.
virtual void recvFunctionalSnoop(PacketPtr pkt)
Receive a functional snoop request packet from the peer.
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
virtual void recvTimingSnoopReq(PacketPtr pkt)
Receive a timing snoop request from the peer.
MemSidePort(const std::string &_name, BaseCache *_cache, const std::string &_label)
virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk)=0
Service non-deferred MSHR targets using the received response.
virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side)
Performs the access specified by the request.
const bool isReadOnly
Is this cache read only, for example the instruction cache, or table-walker cache.
virtual void recvTimingReq(PacketPtr pkt)
Performs the access specified by the request.
virtual void doWritebacks(PacketList &writebacks, Tick forward_time)=0
Insert writebacks into the write buffer.
const Cycles fillLatency
The latency to fill a cache block.
const Cycles dataLatency
The latency of data access of a cache.
void invalidateVisitor(CacheBlk &blk)
Cache block visitor that invalidates all blocks in the cache.
virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks)=0
Handle a request in atomic mode that missed in this cache.
ProbePointArg< DataUpdate > * ppDataUpdate
To probe when the contents of a block are updated.
virtual void doWritebacksAtomic(PacketList &writebacks)=0
Send writebacks down the memory hierarchy in atomic mode.
void updateBlockData(CacheBlk *blk, const PacketPtr cpkt, bool has_old_data)
Update the data contents of a block.
MSHR * allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send=true)
PacketPtr tempBlockWriteback
Writebacks from the tempBlock, resulting on the response path in atomic mode, must happen after the c...
bool isDirty() const
Determine if there are any dirty blocks in the cache.
void invalidateBlock(CacheBlk *blk)
Invalidate a cache block.
MSHR * noTargetMSHR
Pointer to the MSHR that has no targets.
const bool writebackClean
Determine if clean lines should be written back or not.
bool sendWriteQueuePacket(WriteQueueEntry *wq_entry)
Similar to sendMSHR, but for a write-queue entry instead.
bool inRange(Addr addr) const
Determine if an address is in the ranges covered by this cache.
virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, Tick request_time)=0
bool allocOnFill(MemCmd cmd) const
Determine whether we should allocate on a fill or not.
bool forwardSnoops
Do we forward snoops from mem side port through to cpu side port?
uint64_t order
Increasing order number assigned to each incoming request.
void incHitCount(PacketPtr pkt)
virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool deferred_response=false, bool pending_downgrade=false)
Perform any necessary updates to the block and perform any data exchange between the packet and the b...
virtual void memWriteback() override
Write back dirty blocks in the cache using functional accesses.
bool updateCompressionData(CacheBlk *&blk, const uint64_t *data, PacketList &writebacks)
When a block is overwriten, its compression information must be updated, and it may need to be recomp...
bool isBlocked() const
Returns true if the cache is blocked for accesses.
gem5::BaseCache::CacheStats stats
ProbePointArg< PacketPtr > * ppFill
To probe when a cache fill occurs.
const Cycles lookupLatency
The latency of tag lookup of a cache.
Cycles calculateAccessLatency(const CacheBlk *blk, const uint32_t delay, const Cycles lookup_lat) const
Calculate access latency in ticks given a tag lookup latency, and whether access was a hit or miss.
Tick nextQueueReadyTime() const
Find next request ready time from among possible sources.
ProbePointArg< PacketPtr > * ppHit
To probe when a cache hit occurs.
void regProbePoints() override
Registers probes.
virtual void memInvalidate() override
Invalidates all blocks in the cache.
MSHRQueue mshrQueue
Miss status registers.
virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, bool needs_writable, bool is_whole_line_write) const =0
Create an appropriate downstream bus request packet.
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
QueueEntry * getNextQueueEntry()
Return the next queue entry to service, either a pending miss from the MSHR queue,...
void handleUncacheableWriteResp(PacketPtr pkt)
Handling the special case of uncacheable write responses to make recvTimingResp less cluttered.
const unsigned blkSize
Block size of this cache.
void writebackTempBlockAtomic()
Send the outstanding tempBlock writeback.
const Cycles forwardLatency
This is the forward latency of the cache.
compression::Base * compressor
Compression method being used.
const Cycles responseLatency
The latency of sending reponse to its upper level cache/core on a linefill.
PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
Create a writeclean request for the given block.
void schedMemSideSendEvent(Tick time)
Schedule a send event for the memory-side port.
ProbePointArg< PacketPtr > * ppMiss
To probe when a cache miss occurs.
virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
virtual Tick recvAtomic(PacketPtr pkt)
Performs the access specified by the request.
void unserialize(CheckpointIn &cp) override
Unserialize an object.
void cmpAndSwap(CacheBlk *blk, PacketPtr pkt)
Handle doing the Compare and Swap function for SPARC.
virtual void recvTimingResp(PacketPtr pkt)
Handles a response (cache line fill/write ack) from the bus.
virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks)
Does all the processing necessary to perform the provided request.
void setBlocked(BlockedCause cause)
Marks the access path of the cache as blocked for the given cause.
BaseCache(const BaseCacheParams &p, unsigned blk_size)
Addr regenerateBlkAddr(CacheBlk *blk)
Regenerate block address using tags.
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
CacheBlk * allocateBlock(const PacketPtr pkt, PacketList &writebacks)
Allocate a new block and perform any necessary writebacks.
prefetch::Base * prefetcher
Prefetcher.
uint8_t blocked
Bit vector of the blocking reasons for the access path.
TempCacheBlk * tempBlock
Temporary cache block for occasional transitory use.
const AddrRangeList addrRanges
The address range to which the cache responds on the CPU side.
const int numTarget
The number of targets for each MSHR.
const bool moveContractions
Similar to data expansions, after a block improves its compression, it may need to be moved elsewhere...
WriteAllocator *const writeAllocator
The writeAllocator drive optimizations for streaming writes.
void markInService(MSHR *mshr, bool pending_modified_resp)
Mark a request as in service (sent downstream in the memory system), effectively making this MSHR the...
void allocateWriteBuffer(PacketPtr pkt, Tick time)
Cycles calculateTagOnlyLatency(const uint32_t delay, const Cycles lookup_lat) const
Calculate latency of accesses that only touch the tag array.
CacheBlk * handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, bool allocate)
Handle a fill operation caused by a received packet.
void incMissCount(PacketPtr pkt)
WriteQueue writeBuffer
Write/writeback buffer.
const bool replaceExpansions
when a data expansion of a compressed block happens it will not be able to co-allocate where it is at...
void serialize(CheckpointOut &cp) const override
Serialize the state of the caches.
bool coalesce() const
Checks if the cache is coalescing writes.
const bool sequentialAccess
Whether tags and data are accessed sequentially.
bool handleEvictions(std::vector< CacheBlk * > &evict_blks, PacketList &writebacks)
Try to evict the given blocks.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
PacketPtr writebackBlk(CacheBlk *blk)
Create a writeback request for the given block.
void clearBlocked(BlockedCause cause)
Marks the cache as unblocked for the given cause.
virtual PacketPtr evictBlock(CacheBlk *blk)=0
Evict a cache block.
void writebackVisitor(CacheBlk &blk)
Cache block visitor that writes back dirty cache blocks using functional writes.
EventFunctionWrapper writebackTempBlockAtomicEvent
An event to writeback the tempBlock after recvAtomic finishes.
BaseTags * tags
Tag and data Storage.
const enums::Clusivity clusivity
Clusivity with respect to the upstream cache, determining if we fill into both this cache and the cac...
virtual bool sendMSHRQueuePacket(MSHR *mshr)
Take an MSHR, turn it into a suitable downstream packet, and send it out.
void maintainClusivity(bool from_cache, CacheBlk *blk)
Maintain the clusivity of this cache by potentially invalidating a block.
System * system
System we are currently operating in.
Simple class to provide virtual print() method on cache blocks without allocating a vtable pointer fo...
void setWhenReady(const Tick tick)
Set tick at which block's data will be available for access.
@ ReadableBit
Read permission.
@ WritableBit
write permission
@ DirtyBit
dirty (modified)
Tick getWhenReady() const
Get tick at which block's data will be available for access.
void clearPrefetched()
Clear the prefetching bit.
std::string print() const override
Pretty-print tag, set and way, and interpret state bits to readable form including mapping to a MOESI...
bool isSet(unsigned bits) const
Checks the given coherence bits are set.
bool checkWrite(PacketPtr pkt)
Handle interaction of load-locked operations and stores.
void clearCoherenceBits(unsigned bits)
Clear the corresponding coherence bits.
uint32_t getTaskId() const
Get the task id associated to this block.
void trackLoadLocked(PacketPtr pkt)
Track the fact that a local locked was issued to the block.
bool wasPrefetched() const
Check if this block was the result of a hardware prefetch, yet to be touched.
uint8_t * data
Contains a copy of the data in this block for easy access.
void setCoherenceBits(unsigned bits)
Sets the corresponding coherence bits.
A coherent cache that can be arranged in flexible topologies.
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Tick cyclesToTicks(Cycles c) const
Cycles ticksToCycles(Tick t) const
A superblock is composed of sub-blocks, and each sub-block has information regarding its superblock a...
std::size_t getSizeBits() const
void setSizeBits(const std::size_t size)
Set size, in bits, of this compressed block's data.
void setDecompressionLatency(const Cycles lat)
Set number of cycles needed to decompress this block.
OverwriteType
When an overwrite happens, the data size may change an not fit in its current container any longer.
@ DATA_EXPANSION
New data contents are considered larger than previous contents.
@ DATA_CONTRACTION
New data contents are considered smaller than previous contents.
OverwriteType checkExpansionContraction(const std::size_t size) const
Determines if changing the size of the block will cause a data expansion (new size is bigger) or cont...
Cycles is a wrapper class for representing cycle counts, i.e.
void delay(MSHR *mshr, Tick delay_ticks)
Adds a delay to the provided MSHR and moves MSHRs that will be ready earlier than this entry to the t...
void deallocate(MSHR *mshr) override
Deallocate a MSHR and its targets.
bool canPrefetch() const
Returns true if sufficient mshrs for prefetch.
void markPending(MSHR *mshr)
Mark an in service entry as pending, used to resend a request.
void markInService(MSHR *mshr, bool pending_modified_resp)
Mark the given MSHR as in service.
Miss Status and handling Register.
bool wasWholeLineWrite
Track if we sent this as a whole line write or not.
bool isPendingModified() const
void promoteReadable()
Promotes deferred targets that do not require writable.
int getNumTargets() const
Returns the current number of allocated targets.
bool needsWritable() const
The pending* and post* flags are only valid if inService is true.
bool isForward
True if the entry is just a simple forward from an upper level.
bool hasLockedRMWReadTarget()
Determine if there are any LockedRMWReads in the Targets list.
bool promoteDeferredTargets()
bool isWholeLineWrite() const
Check if this MSHR contains only compatible writes, and if they span the entire cache line.
void allocateTarget(PacketPtr target, Tick when, Counter order, bool alloc_on_fill)
Add a request to the list of targets.
void promoteWritable()
Promotes deferred targets that do not require writable.
QueueEntry::Target * getTarget() override
Returns a reference to the first target.
virtual std::string name() const
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
void writeDataToBlock(uint8_t *blk_data, int blkSize) const
Copy data from the packet to the provided block pointer, which is aligned to the given block size.
AtomicOpFunctor * getAtomicOp() const
Accessor function to atomic op.
void pushLabel(const std::string &lbl)
Push label for PrintReq (safe to call unconditionally).
void setWriteThrough()
A writeback/writeclean cmd gets propagated further downstream by the receiver when the flag is set.
void makeTimingResponse()
bool needsWritable() const
void print(std::ostream &o, int verbosity=0, const std::string &prefix="") const
bool isCleanEviction() const
Is this packet a clean eviction, including both actual clean evict packets, but also clean writebacks...
bool needsResponse() const
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
SenderState * senderState
This packet's sender state.
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Addr getOffset(unsigned int blk_size) const
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
bool writeThrough() const
void setData(const uint8_t *p)
Copy data into the packet from the provided pointer.
void setDataFromBlock(const uint8_t *blk_data, int blkSize)
Copy data into the packet from the provided block pointer, which is aligned to the given block size.
bool trySatisfyFunctional(PacketPtr other)
Check a functional request against a memory value stored in another packet (i.e.
Addr getBlockAddr(unsigned int blk_size) const
RequestPtr req
A pointer to the original request.
void setCacheResponding()
Snoop flags.
void popLabel()
Pop label for PrintReq (safe to call unconditionally).
bool isExpressSnoop() const
void setHasSharers()
On fills, the hasSharers flag is used by the caches in combination with the cacheResponding flag,...
const T * getConstPtr() const
bool cacheResponding() const
void makeAtomicResponse()
void setSatisfied()
Set when a request hits in a cache and the cache is not going to respond.
MemCmd cmd
The command field of the packet.
bool isInvalidate() const
void writeData(uint8_t *p) const
Copy data from the packet to the memory at the provided pointer.
void allocate()
Allocate memory for the packet.
Ports are used to interface objects to each other.
bool isConnected() const
Is this port currently connected to a peer?
ProbePointArg generates a point for the class of Arg.
A queue entry is holding packets that will be serviced as soon as resources are available.
const Tick recvTime
Time when request was received (for stats)
PacketPtr pkt
Pending request packet.
A queue entry base class, to be used by both the MSHRs and write-queue entries.
virtual bool sendPacket(BaseCache &cache)=0
Send this queue entry as a downstream packet, with the exact behaviour depending on the specific entr...
Addr blkAddr
Block aligned address.
Counter order
Order number assigned to disambiguate writes and misses.
bool inService
True if the entry has been sent downstream.
bool isSecure
True if the entry targets the secure memory space.
virtual Target * getTarget()=0
Returns a pointer to the first target.
Entry * findPending(const QueueEntry *entry) const
Find any pending requests that overlap the given request of a different queue.
bool trySatisfyFunctional(PacketPtr pkt)
Tick nextReadyTime() const
Entry * getNext() const
Returns the WriteQueueEntry at the head of the readyList.
Entry * findMatch(Addr blk_addr, bool is_secure, bool ignore_uncacheable=true) const
Find the first entry that matches the provided address.
bool trySatisfyFunctional(PacketPtr pkt)
Check the list of buffered packets against the supplied functional request.
A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module...
bool trySatisfyFunctional(PacketPtr pkt)
Check the list of buffered packets against the supplied functional request.
void schedTimingResp(PacketPtr pkt, Tick when)
Schedule the sending of a timing response.
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
void sendFunctional(PacketPtr pkt) const
Send a functional request packet, where the data is instantly updated everywhere in the memory system...
@ SECURE
The request targets the secure memory space.
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
@ wbRequestorId
This requestor id is used for writeback requests by the caches.
void sendFunctionalSnoop(PacketPtr pkt) const
Send a functional snoop request packet, where the data is instantly updated everywhere in the memory ...
bool isSnooping() const
Find out if the peer request port is snooping or not.
void sendRangeChange() const
Called by the owner to send a range change.
std::vector< SectorSubBlk * > blks
List of blocks associated to this sector.
SectorBlk * getSectorBlock() const
Get sector block associated to this block.
A basic compression superblock.
std::string getRequestorName(RequestorID requestor_id)
Get the name of an object for a given request id.
RequestorID maxRequestors()
Get the number of requestors registered in the system.
virtual bool isValid() const
Checks if the entry is valid.
bool isSecure() const
Check if this block holds data from the secure memory space.
Special instance of CacheBlk for use with tempBlk that deals with its block address regeneration.
void insert(const Addr addr, const bool is_secure) override
Insert the block by assigning it a tag and marking it valid.
Addr getAddr() const
Get block's address.
void invalidate() override
Invalidate the block and clear all state.
bool coalesce() const
Should writes be coalesced? This is true if the mode is set to NO_ALLOCATE.
bool delay(Addr blk_addr)
Access whether we need to delay the current write.
void reset()
Reset the write allocator state, meaning that it allocates for writes and has not recorded any inform...
bool allocate() const
Should writes allocate?
void updateMode(Addr write_addr, unsigned write_size, Addr blk_addr)
Update the write mode based on the current write packet.
void resetDelay(Addr blk_addr)
Clear delay counter for the input block.
int getNumTargets() const
Returns the current number of allocated targets.
Target * getTarget() override
Returns a reference to the first target.
virtual std::unique_ptr< CompressionData > compress(const std::vector< Chunk > &chunks, Cycles &comp_lat, Cycles &decomp_lat)=0
Apply the compression process to the cache line.
Cycles getDecompressionLatency(const CacheBlk *blk)
Get the decompression latency if the block is compressed.
static void setSizeBits(CacheBlk *blk, const std::size_t size_bits)
Set the size of the compressed block, in bits.
static void setDecompressionLatency(CacheBlk *blk, const Cycles lat)
Set the decompression latency of compressed block.
void incrDemandMhsrMisses()
virtual PacketPtr getPacket()=0
virtual Tick nextPrefetchReadyTime() const =0
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
static const Priority Delayed_Writeback_Pri
For some reason "delayed" inter-cluster writebacks are scheduled before regular writebacks (which hav...
void deschedule(Event &event)
bool scheduled() const
Determine if the current event is scheduled.
void schedule(Event &event, Tick when)
#define panic(...)
This implements a cprintf based panic() function.
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
#define gem5_assert(cond,...)
The assert macro will function like a normal assert, but will use panic instead of straight abort().
#define fatal(...)
This implements a cprintf based fatal() function.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
ProbeManager * getProbeManager()
Get the probe manager for this object.
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
virtual void regStats()
Callback to set stat parameters.
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
#define SUM_NON_DEMAND(s)
Declares a basic cache interface BaseCache.
Definition of a basic cache compressor.
Miss and writeback queue declarations.
Miss Status and Handling Register (MSHR) declaration.
ProbePointArg< PacketInfo > Packet
Packet probe point.
const FlagsType nonan
Don't print if this is NAN.
const FlagsType nozero
Don't print if this is zero.
const FlagsType total
Print the total.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< Request > RequestPtr
Tick curTick()
The universal simulation clock.
std::ostream CheckpointOut
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
uint64_t Tick
Tick count type.
#define UNSERIALIZE_SCALAR(scalar)
#define SERIALIZE_SCALAR(scalar)
void regStatsFromParent()
Callback to register stats from parent CacheStats::regStats().
statistics::Vector mshrUncacheableLatency
Total tick latency of each MSHR miss, per command and thread.
statistics::Vector mshrHits
Number of misses that hit in the MSHRs per command and thread.
CacheCmdStats(BaseCache &c, const std::string &name)
statistics::Vector mshrMisses
Number of misses that miss in the MSHRs, per command and thread.
statistics::Vector mshrMissLatency
Total tick latency of each MSHR miss, per command and thread.
statistics::Scalar replacements
Number of replacements of valid blocks.
statistics::Scalar dataContractions
Number of data contractions (blocks that had their compression factor improved).
void regStats() override
Callback to set stat parameters.
statistics::Scalar dataExpansions
Number of data expansions.
std::vector< std::unique_ptr< CacheCmdStats > > cmd
Per-command statistics.
statistics::Vector writebacks
Number of blocks written back per thread.
CacheCmdStats & cmdStats(const PacketPtr p)
A data contents update is composed of the updated block's address, the old contents,...
std::vector< uint64_t > newData
The new data contents.
std::vector< uint64_t > oldData
The stale data contents.
Copyright (c) 2018 Inria All rights reserved.
const std::string & name()