gem5  v21.1.0.2
Protected Member Functions | Protected Attributes | List of all members
gem5::PowerISA::PCDependentDisassembly Class Reference

Base class for instructions whose disassembly is not purely a function of the machine instruction (i.e., it depends on the PC). More...

#include <branch.hh>

Inheritance diagram for gem5::PowerISA::PCDependentDisassembly:
gem5::PowerISA::PowerStaticInst gem5::StaticInst gem5::RefCounted gem5::PowerISA::BranchCondOp gem5::PowerISA::BranchOp gem5::PowerISA::BranchDispCondOp gem5::PowerISA::BranchRegCondOp

Protected Member Functions

 PCDependentDisassembly (const char *mnem, ExtMachInst _machInst, OpClass __opClass)
 Constructor. More...
 
const std::string & disassemble (Addr pc, const loader::SymbolTable *symtab) const
 Return string representation of disassembled instruction. More...
 
- Protected Member Functions inherited from gem5::PowerISA::PowerStaticInst
 PowerStaticInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass)
 
uint32_t insertCRField (uint32_t cr, uint32_t bf, uint32_t value) const
 
void printReg (std::ostream &os, RegId reg) const
 Print a register name for disassembly given the unique dependence tag number (FP or int). More...
 
std::string generateDisassembly (Addr pc, const loader::SymbolTable *symtab) const override
 Internal function to generate disassembly string. More...
 
void advancePC (PowerISA::PCState &pcState) const override
 
PCState buildRetPC (const PCState &curPC, const PCState &callPC) const override
 
size_t asBytes (void *buf, size_t max_size) override
 Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst. More...
 
- Protected Member Functions inherited from gem5::StaticInst
void setRegIdxArrays (RegIdArrayPtr src, RegIdArrayPtr dest)
 Set the pointers which point to the arrays of source and destination register indices. More...
 
 StaticInst (const char *_mnemonic, OpClass op_class)
 Constructor. More...
 
template<typename T >
size_t simpleAsBytes (void *buf, size_t max_size, const T &t)
 

Protected Attributes

Addr cachedPC
 Cached program counter from last disassembly. More...
 
const loader::SymbolTablecachedSymtab
 Cached symbol table pointer from last disassembly. More...
 
- Protected Attributes inherited from gem5::PowerISA::PowerStaticInst
ExtMachInst machInst
 
- Protected Attributes inherited from gem5::StaticInst
std::bitset< Num_Flags > flags
 Flag values for this instruction. More...
 
OpClass _opClass
 See opClass(). More...
 
int8_t _numSrcRegs = 0
 See numSrcRegs(). More...
 
int8_t _numDestRegs = 0
 See numDestRegs(). More...
 
int8_t _numFPDestRegs = 0
 The following are used to track physical register usage for machines with separate int & FP reg files. More...
 
int8_t _numIntDestRegs = 0
 
int8_t _numCCDestRegs = 0
 
int8_t _numVecDestRegs = 0
 To use in architectures with vector register file. More...
 
int8_t _numVecElemDestRegs = 0
 
int8_t _numVecPredDestRegs = 0
 
const char * mnemonic
 Base mnemonic (e.g., "add"). More...
 
std::unique_ptr< std::string > cachedDisassembly
 String representation of disassembly (lazily evaluated via disassemble()). More...
 

Additional Inherited Members

- Public Types inherited from gem5::StaticInst
using RegIdArrayPtr = RegId(StaticInst::*)[]
 
- Public Member Functions inherited from gem5::StaticInst
int8_t numSrcRegs () const
 Number of source registers. More...
 
int8_t numDestRegs () const
 Number of destination registers. More...
 
int8_t numFPDestRegs () const
 Number of floating-point destination regs. More...
 
int8_t numIntDestRegs () const
 Number of integer destination regs. More...
 
int8_t numVecDestRegs () const
 Number of vector destination regs. More...
 
int8_t numVecElemDestRegs () const
 Number of vector element destination regs. More...
 
int8_t numVecPredDestRegs () const
 Number of predicate destination regs. More...
 
int8_t numCCDestRegs () const
 Number of coprocesor destination regs. More...
 
bool isNop () const
 
bool isMemRef () const
 
bool isLoad () const
 
bool isStore () const
 
bool isAtomic () const
 
bool isStoreConditional () const
 
bool isInstPrefetch () const
 
bool isDataPrefetch () const
 
bool isPrefetch () const
 
bool isInteger () const
 
bool isFloating () const
 
bool isVector () const
 
bool isControl () const
 
bool isCall () const
 
bool isReturn () const
 
bool isDirectCtrl () const
 
bool isIndirectCtrl () const
 
bool isCondCtrl () const
 
bool isUncondCtrl () const
 
bool isSerializing () const
 
bool isSerializeBefore () const
 
bool isSerializeAfter () const
 
bool isSquashAfter () const
 
bool isFullMemBarrier () const
 
bool isReadBarrier () const
 
bool isWriteBarrier () const
 
bool isNonSpeculative () const
 
bool isQuiesce () const
 
bool isUnverifiable () const
 
bool isSyscall () const
 
bool isMacroop () const
 
bool isMicroop () const
 
bool isDelayedCommit () const
 
bool isLastMicroop () const
 
bool isFirstMicroop () const
 
bool isHtmStart () const
 
bool isHtmStop () const
 
bool isHtmCancel () const
 
bool isHtmCmd () const
 
void setFirstMicroop ()
 
void setLastMicroop ()
 
void setDelayedCommit ()
 
void setFlag (Flags f)
 
OpClass opClass () const
 Operation class. Used to select appropriate function unit in issue. More...
 
const RegIddestRegIdx (int i) const
 Return logical index (architectural reg num) of i'th destination reg. More...
 
void setDestRegIdx (int i, const RegId &val)
 
const RegIdsrcRegIdx (int i) const
 Return logical index (architectural reg num) of i'th source reg. More...
 
void setSrcRegIdx (int i, const RegId &val)
 
virtual uint64_t getEMI () const
 
virtual ~StaticInst ()
 
virtual Fault execute (ExecContext *xc, Trace::InstRecord *traceData) const =0
 
virtual Fault initiateAcc (ExecContext *xc, Trace::InstRecord *traceData) const
 
virtual Fault completeAcc (Packet *pkt, ExecContext *xc, Trace::InstRecord *trace_data) const
 
virtual void advancePC (TheISA::PCState &pc_state) const =0
 
virtual TheISA::PCState buildRetPC (const TheISA::PCState &cur_pc, const TheISA::PCState &call_pc) const
 
virtual StaticInstPtr fetchMicroop (MicroPC upc) const
 Return the microop that goes with a particular micropc. More...
 
virtual TheISA::PCState branchTarget (const TheISA::PCState &pc) const
 Return the target address for a PC-relative branch. More...
 
virtual TheISA::PCState branchTarget (ThreadContext *tc) const
 Return the target address for an indirect branch (jump). More...
 
bool hasBranchTarget (const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
 Return true if the instruction is a control transfer, and if so, return the target address as well. More...
 
void printFlags (std::ostream &outs, const std::string &separator) const
 Print a separator separated list of this instruction's set flag names on the given stream. More...
 
std::string getName ()
 Return name of machine instruction. More...
 
- Public Member Functions inherited from gem5::RefCounted
 RefCounted ()
 We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...
 
virtual ~RefCounted ()
 We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...
 
void incref () const
 Increment the reference count. More...
 
void decref () const
 Decrement the reference count and destroy the object if all references are gone. More...
 
- Static Public Attributes inherited from gem5::StaticInst
static StaticInstPtr nullStaticInstPtr
 Pointer to a statically allocated "null" instruction object. More...
 

Detailed Description

Base class for instructions whose disassembly is not purely a function of the machine instruction (i.e., it depends on the PC).

This class overrides the disassemble() method to check the PC and symbol table values before re-using a cached disassembly string. This is necessary for branches and jumps, where the disassembly string includes the target address (which may depend on the PC and/or symbol table).

Definition at line 50 of file branch.hh.

Constructor & Destructor Documentation

◆ PCDependentDisassembly()

gem5::PowerISA::PCDependentDisassembly::PCDependentDisassembly ( const char *  mnem,
ExtMachInst  _machInst,
OpClass  __opClass 
)
inlineprotected

Constructor.

Definition at line 59 of file branch.hh.

Member Function Documentation

◆ disassemble()

const std::string & gem5::PCDependentDisassembly::disassemble ( Addr  pc,
const loader::SymbolTable symtab 
) const
protectedvirtual

Return string representation of disassembled instruction.

The default version of this function will call the internal virtual generateDisassembly() function to get the string, then cache it in cachedDisassembly. If the disassembly should not be cached, this function should be overridden directly.

Reimplemented from gem5::StaticInst.

Definition at line 43 of file branch.cc.

References gem5::StaticInst::cachedDisassembly, cachedPC, cachedSymtab, gem5::PowerISA::PowerStaticInst::generateDisassembly(), and gem5::MipsISA::pc.

Member Data Documentation

◆ cachedPC

Addr gem5::PowerISA::PCDependentDisassembly::cachedPC
mutableprotected

Cached program counter from last disassembly.

Definition at line 54 of file branch.hh.

Referenced by disassemble().

◆ cachedSymtab

const loader::SymbolTable* gem5::PowerISA::PCDependentDisassembly::cachedSymtab
mutableprotected

Cached symbol table pointer from last disassembly.

Definition at line 56 of file branch.hh.

Referenced by disassemble().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:31:50 for gem5 by doxygen 1.8.17