gem5  v21.1.0.2
branch.hh
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29 
30 #ifndef __ARCH_POWER_INSTS_BRANCH_HH__
31 #define __ARCH_POWER_INSTS_BRANCH_HH__
32 
34 
35 namespace gem5
36 {
37 
38 namespace PowerISA
39 {
40 
51 {
52  protected:
54  mutable Addr cachedPC;
57 
59  PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
60  OpClass __opClass)
61  : PowerStaticInst(mnem, _machInst, __opClass),
62  cachedPC(0), cachedSymtab(0)
63  {
64  }
65 
66  const std::string &
67  disassemble(Addr pc, const loader::SymbolTable *symtab) const;
68 };
69 
70 
75 {
76  protected:
77 
78  bool aa;
79  bool lk;
80  int64_t li;
81 
83  BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
84  : PCDependentDisassembly(mnem, _machInst, __opClass),
85  aa(machInst.aa),
86  lk(machInst.lk),
87  li(sext<26>(machInst.li << 2))
88  {
89  }
90 
91  PowerISA::PCState branchTarget(ThreadContext *tc) const override;
92 
95 
96  std::string generateDisassembly(
97  Addr pc, const loader::SymbolTable *symtab) const override;
98 };
99 
100 
105 {
106  protected:
107 
108  bool lk;
109  uint8_t bi;
110  uint8_t bo;
111 
113  BranchCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
114  : PCDependentDisassembly(mnem, _machInst, __opClass),
115  lk(machInst.lk),
116  bi(machInst.bi),
117  bo(machInst.bo)
118  {
119  }
120 
121  inline bool
122  ctrOk(uint64_t& ctr) const
123  {
124  if (bits(bo, 2)) {
125  return true;
126  }
127 
128  ctr--;
129  return !((ctr != 0) ^ (bits(bo, 1) == 0));
130  }
131 
132  inline bool
133  condOk(uint32_t cr) const
134  {
135  if (bits(bo, 4)) {
136  return true;
137  }
138 
139  return bits(cr >> (31 - bi), 0) == bits(bo >> 3, 0);
140  }
141 };
142 
143 
148 {
149  protected:
150 
151  bool aa;
152  int64_t bd;
153 
155  BranchDispCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
156  : BranchCondOp(mnem, _machInst, __opClass),
157  aa(machInst.aa),
158  bd(sext<16>(machInst.bd << 2))
159  {
160  }
161 
162  PowerISA::PCState branchTarget(ThreadContext *tc) const override;
163 
166 
167  std::string generateDisassembly(
168  Addr pc, const loader::SymbolTable *symtab) const override;
169 };
170 
171 
176 {
177  protected:
178 
180  uint8_t bh;
181 
183  BranchRegCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
184  : BranchCondOp(mnem, _machInst, __opClass),
185  bh(machInst.bh)
186  {
187  }
188 
189  PowerISA::PCState branchTarget(ThreadContext *tc) const override;
190 
193 
194  std::string generateDisassembly(
195  Addr pc, const loader::SymbolTable *symtab) const override;
196 };
197 
198 } // namespace PowerISA
199 } // namespace gem5
200 
201 #endif //__ARCH_POWER_INSTS_BRANCH_HH__
gem5::PowerISA::PowerStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:45
gem5::PowerISA::PCDependentDisassembly::disassemble
const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab) const
Return string representation of disassembled instruction.
Definition: branch.cc:43
gem5::PowerISA::BranchDispCondOp
Base class for conditional, PC-relative or absolute address branches.
Definition: branch.hh:147
gem5::PowerISA::BranchDispCondOp::branchTarget
PowerISA::PCState branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:108
gem5::sext
constexpr uint64_t sext(uint64_t val)
Sign-extend an N-bit value to 64 bits.
Definition: bitfield.hh:126
gem5::PowerISA::BranchOp::BranchOp
BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:83
gem5::PowerISA::BranchCondOp::ctrOk
bool ctrOk(uint64_t &ctr) const
Definition: branch.hh:122
gem5::PowerISA::PCDependentDisassembly
Base class for instructions whose disassembly is not purely a function of the machine instruction (i....
Definition: branch.hh:50
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::PowerISA::PCDependentDisassembly::cachedSymtab
const loader::SymbolTable * cachedSymtab
Cached symbol table pointer from last disassembly.
Definition: branch.hh:56
gem5::PowerISA::BranchCondOp::bo
uint8_t bo
Definition: branch.hh:110
gem5::PowerISA::BranchCondOp::condOk
bool condOk(uint32_t cr) const
Definition: branch.hh:133
gem5::PowerISA::BranchDispCondOp::bd
int64_t bd
Definition: branch.hh:152
gem5::PowerISA::BranchOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:75
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::PowerISA::BranchCondOp::bi
uint8_t bi
Definition: branch.hh:109
gem5::PowerISA::BranchRegCondOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:168
gem5::PowerISA::BranchRegCondOp::BranchRegCondOp
BranchRegCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:183
gem5::PowerISA::BranchDispCondOp::aa
bool aa
Definition: branch.hh:151
gem5::StaticInst::branchTarget
virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:61
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::PowerISA::BranchOp::aa
bool aa
Definition: branch.hh:78
gem5::PowerISA::BranchRegCondOp::branchTarget
PowerISA::PCState branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:159
gem5::PowerISA::BranchCondOp::lk
bool lk
Definition: branch.hh:108
gem5::PowerISA::BranchOp::branchTarget
PowerISA::PCState branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:60
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::PowerISA::BranchRegCondOp
Base class for conditional, register-based branches.
Definition: branch.hh:175
gem5::PowerISA::BranchCondOp::BranchCondOp
BranchCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:113
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::BranchOp::lk
bool lk
Definition: branch.hh:79
gem5::PowerISA::BranchOp
Base class for unconditional, PC-relative or absolute address branches.
Definition: branch.hh:74
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::PowerISA::BranchDispCondOp::BranchDispCondOp
BranchDispCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:155
gem5::PowerISA::BranchRegCondOp::bh
uint8_t bh
TODO: Branch hints are currently ignored.
Definition: branch.hh:180
gem5::PowerISA::MachInst
uint32_t MachInst
Definition: types.hh:44
gem5::PowerISA::PCDependentDisassembly::PCDependentDisassembly
PCDependentDisassembly(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:59
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::PowerISA::BranchOp::li
int64_t li
Definition: branch.hh:80
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::PowerISA::BranchCondOp
Base class for conditional branches.
Definition: branch.hh:104
static_inst.hh
gem5::PowerISA::PowerStaticInst
Definition: static_inst.hh:42
gem5::PowerISA::BranchDispCondOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:123
gem5::PowerISA::PCDependentDisassembly::cachedPC
Addr cachedPC
Cached program counter from last disassembly.
Definition: branch.hh:54

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