gem5  v22.1.0.0
branch.hh
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29 
30 #ifndef __ARCH_POWER_INSTS_BRANCH_HH__
31 #define __ARCH_POWER_INSTS_BRANCH_HH__
32 
34 
35 namespace gem5
36 {
37 
38 namespace PowerISA
39 {
40 
51 {
52  protected:
54  mutable Addr cachedPC;
57 
59  PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
60  OpClass __opClass)
61  : PowerStaticInst(mnem, _machInst, __opClass),
62  cachedPC(0), cachedSymtab(0)
63  {
64  }
65 
66  const std::string &
67  disassemble(Addr pc, const loader::SymbolTable *symtab) const;
68 };
69 
70 
75 {
76  protected:
77 
78  bool aa;
79  bool lk;
80  int64_t li;
81 
83  BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
84  : PCDependentDisassembly(mnem, _machInst, __opClass),
85  aa(machInst.aa),
86  lk(machInst.lk),
87  li(sext<26>(machInst.li << 2))
88  {
89  }
90 
91  std::unique_ptr<PCStateBase> branchTarget(
92  ThreadContext *tc) const override;
93 
96 
97  std::string generateDisassembly(
98  Addr pc, const loader::SymbolTable *symtab) const override;
99 };
100 
101 
106 {
107  protected:
108 
109  bool lk;
110  uint8_t bi;
111  uint8_t bo;
112 
114  BranchCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
115  : PCDependentDisassembly(mnem, _machInst, __opClass),
116  lk(machInst.lk),
117  bi(machInst.bi),
118  bo(machInst.bo)
119  {
120  }
121 
122  inline bool
123  ctrOk(uint64_t& ctr) const
124  {
125  if (bits(bo, 2)) {
126  return true;
127  }
128 
129  ctr--;
130  return !((ctr != 0) ^ (bits(bo, 1) == 0));
131  }
132 
133  inline bool
134  condOk(uint32_t cr) const
135  {
136  if (bits(bo, 4)) {
137  return true;
138  }
139 
140  return bits(cr >> (31 - bi), 0) == bits(bo >> 3, 0);
141  }
142 };
143 
144 
149 {
150  protected:
151 
152  bool aa;
153  int64_t bd;
154 
156  BranchDispCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
157  : BranchCondOp(mnem, _machInst, __opClass),
158  aa(machInst.aa),
159  bd(sext<16>(machInst.bd << 2))
160  {
161  }
162 
163  std::unique_ptr<PCStateBase> branchTarget(
164  ThreadContext *tc) const override;
165 
168 
169  std::string generateDisassembly(
170  Addr pc, const loader::SymbolTable *symtab) const override;
171 };
172 
173 
178 {
179  protected:
180 
182  uint8_t bh;
183 
185  BranchRegCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
186  : BranchCondOp(mnem, _machInst, __opClass),
187  bh(machInst.bh)
188  {
189  }
190 
191  std::unique_ptr<PCStateBase> branchTarget(
192  ThreadContext *tc) const override;
193 
196 
197  std::string generateDisassembly(
198  Addr pc, const loader::SymbolTable *symtab) const override;
199 };
200 
201 } // namespace PowerISA
202 } // namespace gem5
203 
204 #endif //__ARCH_POWER_INSTS_BRANCH_HH__
Base class for conditional branches.
Definition: branch.hh:106
bool ctrOk(uint64_t &ctr) const
Definition: branch.hh:123
BranchCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:114
bool condOk(uint32_t cr) const
Definition: branch.hh:134
Base class for conditional, PC-relative or absolute address branches.
Definition: branch.hh:149
BranchDispCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:156
virtual std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &pc) const
Explicitly import the otherwise hidden branchTarget.
Definition: static_inst.cc:46
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:125
Base class for unconditional, PC-relative or absolute address branches.
Definition: branch.hh:75
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:76
virtual std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &pc) const
Explicitly import the otherwise hidden branchTarget.
Definition: static_inst.cc:46
BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:83
Base class for conditional, register-based branches.
Definition: branch.hh:178
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:171
virtual std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &pc) const
Explicitly import the otherwise hidden branchTarget.
Definition: static_inst.cc:46
uint8_t bh
TODO: Branch hints are currently ignored.
Definition: branch.hh:182
BranchRegCondOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:185
Base class for instructions whose disassembly is not purely a function of the machine instruction (i....
Definition: branch.hh:51
PCDependentDisassembly(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition: branch.hh:59
const loader::SymbolTable * cachedSymtab
Cached symbol table pointer from last disassembly.
Definition: branch.hh:56
Addr cachedPC
Cached program counter from last disassembly.
Definition: branch.hh:54
const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab) const
Return string representation of disassembled instruction.
Definition: branch.cc:43
virtual std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:46
ThreadContext is the external interface to all thread state for anything outside of the CPU.
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
constexpr uint64_t sext(uint64_t val)
Sign-extend an N-bit value to 64 bits.
Definition: bitfield.hh:126
Bitfield< 4 > pc
uint32_t MachInst
Definition: types.hh:44
static RegIndex cr(int index)
Definition: misc.hh:421
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147

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