gem5  v21.1.0.2
branch.cc
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29 
31 #include "arch/power/regs/int.hh"
32 #include "arch/power/regs/misc.hh"
33 
34 #include "base/loader/symtab.hh"
35 #include "cpu/thread_context.hh"
36 
37 namespace gem5
38 {
39 
40 using namespace PowerISA;
41 
42 const std::string &
44  Addr pc, const loader::SymbolTable *symtab) const
45 {
46  if (!cachedDisassembly || pc != cachedPC || symtab != cachedSymtab) {
47  if (!cachedDisassembly)
48  cachedDisassembly.reset(new std::string);
49 
51  cachedPC = pc;
52  cachedSymtab = symtab;
53  }
54 
55  return *cachedDisassembly;
56 }
57 
58 
61 {
62  Msr msr = tc->readIntReg(INTREG_MSR);
63  Addr addr;
64 
65  if (aa)
66  addr = li;
67  else
68  addr = tc->pcState().pc() + li;
69 
70  return msr.sf ? addr : addr & UINT32_MAX;
71 }
72 
73 
74 std::string
76  Addr pc, const loader::SymbolTable *symtab) const
77 {
78  std::stringstream ss;
79  Addr target;
80 
81  // Generate correct mnemonic
82  std::string myMnemonic(mnemonic);
83  std::string suffix;
84 
85  // Additional characters depending on isa bits being set
86  if (lk)
87  suffix += "l";
88  if (aa)
89  suffix += "a";
90  ccprintf(ss, "%-10s ", myMnemonic + suffix);
91 
92  if (aa)
93  target = li;
94  else
95  target = pc + li;
96 
98  if (symtab && (it = symtab->find(target)) != symtab->end())
99  ss << it->name;
100  else
101  ccprintf(ss, "%#x", target);
102 
103  return ss.str();
104 }
105 
106 
109 {
110  Msr msr = tc->readIntReg(INTREG_MSR);
111  Addr addr;
112 
113  if (aa)
114  addr = bd;
115  else
116  addr = tc->pcState().pc() + bd;
117 
118  return msr.sf ? addr : addr & UINT32_MAX;
119 }
120 
121 
122 std::string
124  Addr pc, const loader::SymbolTable *symtab) const
125 {
126  std::stringstream ss;
127  Addr target;
128 
129  // Generate the correct mnemonic
130  std::string myMnemonic(mnemonic);
131  std::string suffix;
132 
133  // Additional characters depending on isa bits being set
134  if (lk)
135  suffix += "l";
136  if (aa)
137  suffix += "a";
138  ccprintf(ss, "%-10s ", myMnemonic + suffix);
139 
140  // Print BI and BO fields
141  ss << (int) bi << ", " << (int) bo << ", ";
142 
143  if (aa)
144  target = bd;
145  else
146  target = pc + bd;
147 
149  if (symtab && (it = symtab->find(target)) != symtab->end())
150  ss << it->name;
151  else
152  ccprintf(ss, "%#x", target);
153 
154  return ss.str();
155 }
156 
157 
160 {
161  Msr msr = tc->readIntReg(INTREG_MSR);
162  Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index()) & -4ULL;
163  return msr.sf ? addr : addr & UINT32_MAX;
164 }
165 
166 
167 std::string
169  Addr pc, const loader::SymbolTable *symtab) const
170 {
171  std::stringstream ss;
172 
173  // Generate the correct mnemonic
174  std::string myMnemonic(mnemonic);
175  std::string suffix;
176 
177  // Additional characters depending on isa bits being set
178  if (lk)
179  suffix += "l";
180  ccprintf(ss, "%-10s ", myMnemonic + suffix);
181 
182  // Print the BI and BO fields
183  ss << (int) bi << ", " << (int) bo;
184 
185  return ss.str();
186 }
187 
188 } // namespace gem5
gem5::PowerISA::PCDependentDisassembly::disassemble
const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab) const
Return string representation of disassembled instruction.
Definition: branch.cc:43
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::PowerISA::BranchDispCondOp::branchTarget
PowerISA::PCState branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:108
gem5::PowerISA::PowerStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:65
gem5::loader::SymbolTable::end
const_iterator end() const
Definition: symtab.hh:176
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::PowerISA::PCDependentDisassembly::cachedSymtab
const loader::SymbolTable * cachedSymtab
Cached symbol table pointer from last disassembly.
Definition: branch.hh:56
gem5::PowerISA::BranchCondOp::bo
uint8_t bo
Definition: branch.hh:110
gem5::PowerISA::BranchDispCondOp::bd
int64_t bd
Definition: branch.hh:152
gem5::PowerISA::BranchOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:75
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::loader::SymbolTable::const_iterator
SymbolVector::const_iterator const_iterator
Definition: symtab.hh:170
gem5::PowerISA::BranchCondOp::bi
uint8_t bi
Definition: branch.hh:109
gem5::PowerISA::BranchRegCondOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:168
gem5::PowerISA::BranchDispCondOp::aa
bool aa
Definition: branch.hh:151
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::PowerISA::BranchOp::aa
bool aa
Definition: branch.hh:78
gem5::PowerISA::BranchRegCondOp::branchTarget
PowerISA::PCState branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:159
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::PowerISA::BranchCondOp::lk
bool lk
Definition: branch.hh:108
gem5::PowerISA::INTREG_MSR
@ INTREG_MSR
Definition: int.hh:68
gem5::PowerISA::BranchOp::branchTarget
PowerISA::PCState branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:60
int.hh
ss
std::stringstream ss
Definition: trace.test.cc:45
branch.hh
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
misc.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::PowerISA::BranchOp::lk
bool lk
Definition: branch.hh:79
gem5::loader::SymbolTable::find
const_iterator find(Addr address) const
Search for a symbol by its address.
Definition: symtab.hh:322
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::StaticInst::cachedDisassembly
std::unique_ptr< std::string > cachedDisassembly
String representation of disassembly (lazily evaluated via disassemble()).
Definition: static_inst.hh:287
gem5::PowerISA::BranchOp::li
int64_t li
Definition: branch.hh:80
symtab.hh
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:109
thread_context.hh
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::PowerISA::BranchDispCondOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:123
gem5::PowerISA::PCDependentDisassembly::cachedPC
Addr cachedPC
Cached program counter from last disassembly.
Definition: branch.hh:54

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