gem5  v21.2.1.1
branch.cc
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29 
31 #include "arch/power/regs/int.hh"
32 #include "arch/power/regs/misc.hh"
33 
34 #include "base/loader/symtab.hh"
35 #include "cpu/thread_context.hh"
36 
37 namespace gem5
38 {
39 
40 using namespace PowerISA;
41 
42 const std::string &
44  Addr pc, const loader::SymbolTable *symtab) const
45 {
46  if (!cachedDisassembly || pc != cachedPC || symtab != cachedSymtab) {
47  if (!cachedDisassembly)
48  cachedDisassembly.reset(new std::string);
49 
51  cachedPC = pc;
52  cachedSymtab = symtab;
53  }
54 
55  return *cachedDisassembly;
56 }
57 
58 
59 std::unique_ptr<PCStateBase>
61 {
62  Msr msr = tc->readIntReg(INTREG_MSR);
63  Addr addr;
64 
65  if (aa)
66  addr = li;
67  else
68  addr = tc->pcState().instAddr() + li;
69 
70  return std::make_unique<PowerISA::PCState>(
71  msr.sf ? addr : addr & UINT32_MAX);
72 }
73 
74 
75 std::string
77  Addr pc, const loader::SymbolTable *symtab) const
78 {
79  std::stringstream ss;
80  Addr target;
81 
82  // Generate correct mnemonic
83  std::string myMnemonic(mnemonic);
84  std::string suffix;
85 
86  // Additional characters depending on isa bits being set
87  if (lk)
88  suffix += "l";
89  if (aa)
90  suffix += "a";
91  ccprintf(ss, "%-10s ", myMnemonic + suffix);
92 
93  if (aa)
94  target = li;
95  else
96  target = pc + li;
97 
99  if (symtab && (it = symtab->find(target)) != symtab->end())
100  ss << it->name;
101  else
102  ccprintf(ss, "%#x", target);
103 
104  return ss.str();
105 }
106 
107 
108 std::unique_ptr<PCStateBase>
110 {
111  Msr msr = tc->readIntReg(INTREG_MSR);
112  Addr addr;
113 
114  if (aa)
115  addr = bd;
116  else
117  addr = tc->pcState().instAddr() + bd;
118 
119  return std::make_unique<PowerISA::PCState>(
120  msr.sf ? addr : addr & UINT32_MAX);
121 }
122 
123 
124 std::string
126  Addr pc, const loader::SymbolTable *symtab) const
127 {
128  std::stringstream ss;
129  Addr target;
130 
131  // Generate the correct mnemonic
132  std::string myMnemonic(mnemonic);
133  std::string suffix;
134 
135  // Additional characters depending on isa bits being set
136  if (lk)
137  suffix += "l";
138  if (aa)
139  suffix += "a";
140  ccprintf(ss, "%-10s ", myMnemonic + suffix);
141 
142  // Print BI and BO fields
143  ss << (int) bi << ", " << (int) bo << ", ";
144 
145  if (aa)
146  target = bd;
147  else
148  target = pc + bd;
149 
151  if (symtab && (it = symtab->find(target)) != symtab->end())
152  ss << it->name;
153  else
154  ccprintf(ss, "%#x", target);
155 
156  return ss.str();
157 }
158 
159 
160 std::unique_ptr<PCStateBase>
162 {
163  Msr msr = tc->readIntReg(INTREG_MSR);
164  Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index()) & -4ULL;
165  return std::make_unique<PowerISA::PCState>(
166  msr.sf ? addr : addr & UINT32_MAX);
167 }
168 
169 
170 std::string
172  Addr pc, const loader::SymbolTable *symtab) const
173 {
174  std::stringstream ss;
175 
176  // Generate the correct mnemonic
177  std::string myMnemonic(mnemonic);
178  std::string suffix;
179 
180  // Additional characters depending on isa bits being set
181  if (lk)
182  suffix += "l";
183  ccprintf(ss, "%-10s ", myMnemonic + suffix);
184 
185  // Print the BI and BO fields
186  ss << (int) bi << ", " << (int) bo;
187 
188  return ss.str();
189 }
190 
191 } // namespace gem5
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::PowerISA::PCDependentDisassembly::disassemble
const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab) const
Return string representation of disassembled instruction.
Definition: branch.cc:43
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::PowerISA::PowerStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:65
gem5::loader::SymbolTable::end
const_iterator end() const
Definition: symtab.hh:176
gem5::PowerISA::BranchDispCondOp::branchTarget
std::unique_ptr< PCStateBase > branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:109
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::PowerISA::PCDependentDisassembly::cachedSymtab
const loader::SymbolTable * cachedSymtab
Cached symbol table pointer from last disassembly.
Definition: branch.hh:56
gem5::PowerISA::BranchCondOp::bo
uint8_t bo
Definition: branch.hh:111
gem5::PowerISA::BranchDispCondOp::bd
int64_t bd
Definition: branch.hh:153
gem5::PowerISA::BranchOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:76
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::loader::SymbolTable::const_iterator
SymbolVector::const_iterator const_iterator
Definition: symtab.hh:170
gem5::PowerISA::BranchCondOp::bi
uint8_t bi
Definition: branch.hh:110
gem5::PowerISA::BranchRegCondOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:171
gem5::PowerISA::BranchDispCondOp::aa
bool aa
Definition: branch.hh:152
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::PowerISA::BranchOp::aa
bool aa
Definition: branch.hh:78
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:246
gem5::PowerISA::BranchCondOp::lk
bool lk
Definition: branch.hh:109
gem5::PowerISA::INTREG_MSR
@ INTREG_MSR
Definition: int.hh:68
int.hh
ss
std::stringstream ss
Definition: trace.test.cc:45
branch.hh
misc.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::PowerISA::BranchOp::lk
bool lk
Definition: branch.hh:79
gem5::loader::SymbolTable::find
const_iterator find(Addr address) const
Search for a symbol by its address.
Definition: symtab.hh:322
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::StaticInst::cachedDisassembly
std::unique_ptr< std::string > cachedDisassembly
String representation of disassembly (lazily evaluated via disassemble()).
Definition: static_inst.hh:286
gem5::PowerISA::BranchOp::li
int64_t li
Definition: branch.hh:80
symtab.hh
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:280
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:108
gem5::PowerISA::BranchOp::branchTarget
std::unique_ptr< PCStateBase > branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:60
thread_context.hh
gem5::PowerISA::BranchRegCondOp::branchTarget
std::unique_ptr< PCStateBase > branchTarget(ThreadContext *tc) const override
Return the target address for an indirect branch (jump).
Definition: branch.cc:161
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::PowerISA::BranchDispCondOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:125
gem5::PowerISA::PCDependentDisassembly::cachedPC
Addr cachedPC
Cached program counter from last disassembly.
Definition: branch.hh:54

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