gem5  v22.0.0.2
exec_stage.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
33 
34 #include <sstream>
35 
36 #include "base/trace.hh"
37 #include "debug/GPUSched.hh"
40 #include "gpu-compute/wavefront.hh"
41 
42 namespace gem5
43 {
44 
45 ExecStage::ExecStage(const ComputeUnitParams &p, ComputeUnit &cu,
46  ScheduleToExecute &from_schedule)
47  : computeUnit(cu), fromSchedule(from_schedule),
48  lastTimeInstExecuted(false),
49  thisTimeInstExecuted(false), instrExecuted (false),
50  executionResourcesUsed(0), _name(cu.name() + ".ExecStage"),
51  stats(&cu)
52 
53 {
55  idle_dur = 0;
56 }
57 
58 void
60 {
61  idle_dur = 0;
62 }
63 
64 void
65 ExecStage::collectStatistics(enum STAT_STATUS stage, int unitId) {
66  if (stage == IdleExec) {
67  // count cycles when no instruction to a specific execution resource
68  // is executed
70  } else if (stage == BusyExec) {
71  // count the number of cycles an instruction to a specific execution
72  // resource type was issued
74  thisTimeInstExecuted = true;
75  instrExecuted = true;
77  } else if (stage == PostExec) {
78  // count the number of transitions from active to idle
81  }
82 
85  idle_dur = 0;
86  } else if (!thisTimeInstExecuted) {
87  idle_dur++;
88  }
89 
91  // track the number of cycles we either issued at least
92  // instruction or issued no instructions at all
93  if (instrExecuted) {
95  } else {
97  }
99  }
100 }
101 
102 void
104 {
105  instrExecuted = false;
107  thisTimeInstExecuted = false;
108 }
109 
110 std::string
112 {
113  std::string s("INVALID");
114  switch (i) {
115  case EMPTY:
116  s = "EMPTY";
117  break;
118  case SKIP:
119  s = "SKIP";
120  break;
121  case EXREADY:
122  s = "EXREADY";
123  break;
124  }
125  return s;
126 }
127 
128 void
130 {
131  std::stringstream ss;
132  bool empty = true;
133  for (int i = 0; i < computeUnit.numExeUnits(); i++) {
135  ss << i << ": " << dispStatusToStr(s);
136  if (s != EMPTY) {
137  empty = false;
138  GPUDynInstPtr &gpu_dyn_inst = fromSchedule.readyInst(i);
139  Wavefront *wf = gpu_dyn_inst->wavefront();
140  ss << " SIMD[" << wf->simdId << "] WV[" << wf->wfDynId << "]: ";
141  ss << (wf->instructionBuffer.front())->seqNum() << ": ";
142  ss << (wf->instructionBuffer.front())->disassemble();
143  }
144  ss << "\n";
145  }
146  if (!empty) {
147  DPRINTF(GPUSched, "Dispatch List:\n%s", ss.str());
148  }
149 }
150 
151 void
153 {
154  initStatistics();
155  if (debug::GPUSched) {
156  dumpDispList();
157  }
158  for (int unitId = 0; unitId < computeUnit.numExeUnits(); ++unitId) {
160  switch (s) {
161  case EMPTY:
162  // Do not execute if empty, waiting for VRF reads,
163  // or LM tied to GM waiting for VRF reads
164  collectStatistics(IdleExec, unitId);
165  break;
166  case EXREADY:
167  {
168  collectStatistics(BusyExec, unitId);
169  GPUDynInstPtr &gpu_dyn_inst = fromSchedule.readyInst(unitId);
170  assert(gpu_dyn_inst);
171  Wavefront *wf = gpu_dyn_inst->wavefront();
172  DPRINTF(GPUSched, "Exec[%d]: SIMD[%d] WV[%d]: %s\n",
173  unitId, wf->simdId, wf->wfDynId,
174  gpu_dyn_inst->disassemble());
175  DPRINTF(GPUSched, "dispatchList[%d] EXREADY->EMPTY\n", unitId);
176  wf->exec();
177  (computeUnit.scheduleStage).deleteFromSch(wf);
179  wf->freeResources();
180  break;
181  }
182  case SKIP:
183  {
184  collectStatistics(BusyExec, unitId);
185  GPUDynInstPtr &gpu_dyn_inst = fromSchedule.readyInst(unitId);
186  assert(gpu_dyn_inst);
187  Wavefront *wf = gpu_dyn_inst->wavefront();
188  DPRINTF(GPUSched, "dispatchList[%d] SKIP->EMPTY\n", unitId);
190  wf->freeResources();
191  break;
192  }
193  default:
194  panic("Unknown dispatch status in exec()\n");
195  }
196  }
197 
199 }
200 
202  : statistics::Group(parent, "ExecStage"),
203  ADD_STAT(numTransActiveIdle,
204  "number of CU transitions from active to idle"),
205  ADD_STAT(numCyclesWithNoIssue, "number of cycles the CU issues nothing"),
206  ADD_STAT(numCyclesWithInstrIssued,
207  "number of cycles the CU issued at least one instruction"),
208  ADD_STAT(spc,
209  "Execution units active per cycle (Exec unit=SIMD,MemPipe)"),
210  ADD_STAT(idleDur, "duration of idle periods in cycles"),
211  ADD_STAT(numCyclesWithInstrTypeIssued, "Number of cycles at least one "
212  "instruction issued to execution resource type"),
213  ADD_STAT(numCyclesWithNoInstrTypeIssued, "Number of clks no instructions"
214  " issued to execution resource type")
215 {
216  ComputeUnit *compute_unit = static_cast<ComputeUnit*>(parent);
217 
218  spc.init(0, compute_unit->numExeUnits(), 1);
219  idleDur.init(0, 75, 5);
222 
223  int c = 0;
224  for (int i = 0; i < compute_unit->numVectorALUs; i++,c++) {
225  std::string s = "VectorALU" + std::to_string(i);
228  }
229  for (int i = 0; i < compute_unit->numScalarALUs; i++,c++) {
230  std::string s = "ScalarALU" + std::to_string(i);
233  }
234  numCyclesWithNoInstrTypeIssued.subname(c, "VectorMemPipe");
235  numCyclesWithInstrTypeIssued.subname(c++, "VectorMemPipe");
236 
237  numCyclesWithNoInstrTypeIssued.subname(c, "SharedMemPipe");
238  numCyclesWithInstrTypeIssued.subname(c++, "SharedMemPipe");
239 }
240 
241 } // namespace gem5
gem5::VegaISA::s
Bitfield< 1 > s
Definition: pagetable.hh:64
gem5::BusyExec
@ BusyExec
Definition: exec_stage.hh:55
gem5::Wavefront::exec
void exec()
Definition: wavefront.cc:862
gem5::ScheduleToExecute
Communication interface between Schedule and Execute stages.
Definition: comm.hh:98
gem5::ExecStage::thisTimeInstExecuted
bool thisTimeInstExecuted
Definition: exec_stage.hh:94
gem5::Wavefront
Definition: wavefront.hh:60
compute_unit.hh
gem5::ExecStage::ExecStageStats::numCyclesWithNoInstrTypeIssued
statistics::Vector numCyclesWithNoInstrTypeIssued
Definition: exec_stage.hh:121
sc_dt::to_string
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:91
gem5::SKIP
@ SKIP
Definition: exec_stage.hh:63
gem5::statistics::DataWrapVec::subname
Derived & subname(off_type index, const std::string &name)
Set the subfield name for the given index, and marks this stat to print at the end of simulation.
Definition: statistics.hh:402
gem5::ExecStage::lastTimeInstExecuted
bool lastTimeInstExecuted
Definition: exec_stage.hh:93
gem5::EXREADY
@ EXREADY
Definition: exec_stage.hh:62
gem5::ScheduleToExecute::dispatchStatus
DISPATCH_STATUS dispatchStatus(int func_unit_id) const
Definition: comm.cc:150
gem5::ExecStage::stats
gem5::ExecStage::ExecStageStats stats
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ExecStage::ExecStageStats::idleDur
statistics::Distribution idleDur
Definition: exec_stage.hh:114
gem5::ExecStage::ExecStageStats::numCyclesWithInstrTypeIssued
statistics::Vector numCyclesWithInstrTypeIssued
Definition: exec_stage.hh:117
gem5::ExecStage::executionResourcesUsed
int executionResourcesUsed
Definition: exec_stage.hh:96
gem5::statistics::DistBase::sample
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Definition: statistics.hh:1328
wavefront.hh
gem5::ExecStage::computeUnit
ComputeUnit & computeUnit
Definition: exec_stage.hh:90
gem5::ExecStage::ExecStageStats::spc
statistics::Distribution spc
Definition: exec_stage.hh:112
gem5::VegaISA::c
Bitfield< 2 > c
Definition: pagetable.hh:63
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::ComputeUnit::numScalarALUs
int numScalarALUs
Definition: compute_unit.hh:248
gem5::ComputeUnit::numVectorALUs
int numVectorALUs
Definition: compute_unit.hh:244
vector_register_file.hh
gem5::ExecStage::dispStatusToStr
std::string dispStatusToStr(int j)
Definition: exec_stage.cc:111
gem5::ScheduleToExecute::readyInst
GPUDynInstPtr & readyInst(int func_unit_id)
Definition: comm.cc:127
gem5::statistics::Distribution::init
Distribution & init(Counter min, Counter max, Counter bkt)
Set the parameters of this distribution.
Definition: statistics.hh:2113
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::ExecStage::ExecStageStats::numCyclesWithInstrIssued
statistics::Scalar numCyclesWithInstrIssued
Definition: exec_stage.hh:110
gem5::EMPTY
@ EMPTY
Definition: exec_stage.hh:61
gem5::ExecStage::idle_dur
uint64_t idle_dur
Definition: exec_stage.hh:97
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::ExecStage::ExecStage
ExecStage(const ComputeUnitParams &p, ComputeUnit &cu, ScheduleToExecute &from_schedule)
Definition: exec_stage.cc:45
gem5::ExecStage::collectStatistics
void collectStatistics(enum STAT_STATUS stage, int unitId)
Definition: exec_stage.cc:65
gem5::ExecStage::init
void init()
Definition: exec_stage.cc:59
gem5::IdleExec
@ IdleExec
Definition: exec_stage.hh:54
gem5::Wavefront::wfDynId
uint64_t wfDynId
Definition: wavefront.hh:226
gem5::DISPATCH_STATUS
DISPATCH_STATUS
Definition: exec_stage.hh:59
gem5::ExecStage::fromSchedule
ScheduleToExecute & fromSchedule
Definition: exec_stage.hh:91
name
const std::string & name()
Definition: trace.cc:49
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::ExecStage::ExecStageStats::ExecStageStats
ExecStageStats(statistics::Group *parent)
Definition: exec_stage.cc:201
gem5::STAT_STATUS
STAT_STATUS
Definition: exec_stage.hh:52
gem5::ExecStage::ExecStageStats::numCyclesWithNoIssue
statistics::Scalar numCyclesWithNoIssue
Definition: exec_stage.hh:108
gem5::ExecStage::initStatistics
void initStatistics()
Definition: exec_stage.cc:103
gem5::ScheduleToExecute::dispatchTransition
void dispatchTransition(const GPUDynInstPtr &gpu_dyn_inst, int func_unit_id, DISPATCH_STATUS disp_status)
Once the scheduler has chosen a winning WF for execution, and after the WF's oldest instruction's ope...
Definition: comm.cc:133
gem5::ExecStage::ExecStageStats::numTransActiveIdle
statistics::Scalar numTransActiveIdle
Definition: exec_stage.hh:106
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::PostExec
@ PostExec
Definition: exec_stage.hh:56
gem5::Wavefront::instructionBuffer
std::deque< GPUDynInstPtr > instructionBuffer
Definition: wavefront.hh:109
gem5::ExecStage::exec
void exec()
Definition: exec_stage.cc:152
trace.hh
gem5::ExecStage::dumpDispList
void dumpDispList()
Definition: exec_stage.cc:129
gem5::Wavefront::freeResources
void freeResources()
Definition: wavefront.cc:741
gem5::ExecStage::instrExecuted
bool instrExecuted
Definition: exec_stage.hh:95
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1040
exec_stage.hh
gem5::ComputeUnit::scheduleStage
ScheduleStage scheduleStage
Definition: compute_unit.hh:282
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ComputeUnit::numExeUnits
int numExeUnits() const
Definition: compute_unit.cc:238
gem5::Wavefront::simdId
const int simdId
Definition: wavefront.hh:99

Generated on Thu Jul 28 2022 13:32:33 for gem5 by doxygen 1.8.17