gem5  v21.1.0.2
exec_stage.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
35 
36 #include <sstream>
37 
38 #include "base/trace.hh"
39 #include "debug/GPUSched.hh"
42 #include "gpu-compute/wavefront.hh"
43 
44 namespace gem5
45 {
46 
47 ExecStage::ExecStage(const ComputeUnitParams &p, ComputeUnit &cu,
48  ScheduleToExecute &from_schedule)
49  : computeUnit(cu), fromSchedule(from_schedule),
50  lastTimeInstExecuted(false),
51  thisTimeInstExecuted(false), instrExecuted (false),
52  executionResourcesUsed(0), _name(cu.name() + ".ExecStage"),
53  stats(&cu)
54 
55 {
57  idle_dur = 0;
58 }
59 
60 void
62 {
63  idle_dur = 0;
64 }
65 
66 void
67 ExecStage::collectStatistics(enum STAT_STATUS stage, int unitId) {
68  if (stage == IdleExec) {
69  // count cycles when no instruction to a specific execution resource
70  // is executed
72  } else if (stage == BusyExec) {
73  // count the number of cycles an instruction to a specific execution
74  // resource type was issued
76  thisTimeInstExecuted = true;
77  instrExecuted = true;
79  } else if (stage == PostExec) {
80  // count the number of transitions from active to idle
83  }
84 
87  idle_dur = 0;
88  } else if (!thisTimeInstExecuted) {
89  idle_dur++;
90  }
91 
93  // track the number of cycles we either issued at least
94  // instruction or issued no instructions at all
95  if (instrExecuted) {
97  } else {
99  }
101  }
102 }
103 
104 void
106 {
107  instrExecuted = false;
109  thisTimeInstExecuted = false;
110 }
111 
112 std::string
114 {
115  std::string s("INVALID");
116  switch (i) {
117  case EMPTY:
118  s = "EMPTY";
119  break;
120  case SKIP:
121  s = "SKIP";
122  break;
123  case EXREADY:
124  s = "EXREADY";
125  break;
126  }
127  return s;
128 }
129 
130 void
132 {
133  std::stringstream ss;
134  bool empty = true;
135  for (int i = 0; i < computeUnit.numExeUnits(); i++) {
137  ss << i << ": " << dispStatusToStr(s);
138  if (s != EMPTY) {
139  empty = false;
140  GPUDynInstPtr &gpu_dyn_inst = fromSchedule.readyInst(i);
141  Wavefront *wf = gpu_dyn_inst->wavefront();
142  ss << " SIMD[" << wf->simdId << "] WV[" << wf->wfDynId << "]: ";
143  ss << (wf->instructionBuffer.front())->seqNum() << ": ";
144  ss << (wf->instructionBuffer.front())->disassemble();
145  }
146  ss << "\n";
147  }
148  if (!empty) {
149  DPRINTF(GPUSched, "Dispatch List:\n%s", ss.str());
150  }
151 }
152 
153 void
155 {
156  initStatistics();
157  if (debug::GPUSched) {
158  dumpDispList();
159  }
160  for (int unitId = 0; unitId < computeUnit.numExeUnits(); ++unitId) {
162  switch (s) {
163  case EMPTY:
164  // Do not execute if empty, waiting for VRF reads,
165  // or LM tied to GM waiting for VRF reads
166  collectStatistics(IdleExec, unitId);
167  break;
168  case EXREADY:
169  {
170  collectStatistics(BusyExec, unitId);
171  GPUDynInstPtr &gpu_dyn_inst = fromSchedule.readyInst(unitId);
172  assert(gpu_dyn_inst);
173  Wavefront *wf = gpu_dyn_inst->wavefront();
174  DPRINTF(GPUSched, "Exec[%d]: SIMD[%d] WV[%d]: %s\n",
175  unitId, wf->simdId, wf->wfDynId,
176  gpu_dyn_inst->disassemble());
177  DPRINTF(GPUSched, "dispatchList[%d] EXREADY->EMPTY\n", unitId);
178  wf->exec();
179  (computeUnit.scheduleStage).deleteFromSch(wf);
181  wf->freeResources();
182  break;
183  }
184  case SKIP:
185  {
186  collectStatistics(BusyExec, unitId);
187  GPUDynInstPtr &gpu_dyn_inst = fromSchedule.readyInst(unitId);
188  assert(gpu_dyn_inst);
189  Wavefront *wf = gpu_dyn_inst->wavefront();
190  DPRINTF(GPUSched, "dispatchList[%d] SKIP->EMPTY\n", unitId);
192  wf->freeResources();
193  break;
194  }
195  default:
196  panic("Unknown dispatch status in exec()\n");
197  }
198  }
199 
201 }
202 
204  : statistics::Group(parent, "ExecStage"),
205  ADD_STAT(numTransActiveIdle,
206  "number of CU transitions from active to idle"),
207  ADD_STAT(numCyclesWithNoIssue, "number of cycles the CU issues nothing"),
208  ADD_STAT(numCyclesWithInstrIssued,
209  "number of cycles the CU issued at least one instruction"),
210  ADD_STAT(spc,
211  "Execution units active per cycle (Exec unit=SIMD,MemPipe)"),
212  ADD_STAT(idleDur, "duration of idle periods in cycles"),
213  ADD_STAT(numCyclesWithInstrTypeIssued, "Number of cycles at least one "
214  "instruction issued to execution resource type"),
215  ADD_STAT(numCyclesWithNoInstrTypeIssued, "Number of clks no instructions"
216  " issued to execution resource type")
217 {
218  ComputeUnit *compute_unit = static_cast<ComputeUnit*>(parent);
219 
220  spc.init(0, compute_unit->numExeUnits(), 1);
221  idleDur.init(0, 75, 5);
224 
225  int c = 0;
226  for (int i = 0; i < compute_unit->numVectorALUs; i++,c++) {
227  std::string s = "VectorALU" + std::to_string(i);
230  }
231  for (int i = 0; i < compute_unit->numScalarALUs; i++,c++) {
232  std::string s = "ScalarALU" + std::to_string(i);
235  }
236  numCyclesWithNoInstrTypeIssued.subname(c, "VectorMemPipe");
237  numCyclesWithInstrTypeIssued.subname(c++, "VectorMemPipe");
238 
239  numCyclesWithNoInstrTypeIssued.subname(c, "SharedMemPipe");
240  numCyclesWithInstrTypeIssued.subname(c++, "SharedMemPipe");
241 }
242 
243 } // namespace gem5
gem5::BusyExec
@ BusyExec
Definition: exec_stage.hh:57
gem5::Wavefront::exec
void exec()
Definition: wavefront.cc:864
gem5::ScheduleToExecute
Communication interface between Schedule and Execute stages.
Definition: comm.hh:100
gem5::ExecStage::thisTimeInstExecuted
bool thisTimeInstExecuted
Definition: exec_stage.hh:96
gem5::Wavefront
Definition: wavefront.hh:62
compute_unit.hh
gem5::ExecStage::ExecStageStats::numCyclesWithNoInstrTypeIssued
statistics::Vector numCyclesWithNoInstrTypeIssued
Definition: exec_stage.hh:123
sc_dt::to_string
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:91
gem5::SKIP
@ SKIP
Definition: exec_stage.hh:65
gem5::statistics::DataWrapVec::subname
Derived & subname(off_type index, const std::string &name)
Set the subfield name for the given index, and marks this stat to print at the end of simulation.
Definition: statistics.hh:399
gem5::ExecStage::lastTimeInstExecuted
bool lastTimeInstExecuted
Definition: exec_stage.hh:95
gem5::EXREADY
@ EXREADY
Definition: exec_stage.hh:64
gem5::ScheduleToExecute::dispatchStatus
DISPATCH_STATUS dispatchStatus(int func_unit_id) const
Definition: comm.cc:152
gem5::ExecStage::stats
gem5::ExecStage::ExecStageStats stats
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ExecStage::ExecStageStats::idleDur
statistics::Distribution idleDur
Definition: exec_stage.hh:116
gem5::ExecStage::ExecStageStats::numCyclesWithInstrTypeIssued
statistics::Vector numCyclesWithInstrTypeIssued
Definition: exec_stage.hh:119
gem5::ExecStage::executionResourcesUsed
int executionResourcesUsed
Definition: exec_stage.hh:98
gem5::statistics::DistBase::sample
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Definition: statistics.hh:1325
wavefront.hh
gem5::ExecStage::computeUnit
ComputeUnit & computeUnit
Definition: exec_stage.hh:92
gem5::ExecStage::ExecStageStats::spc
statistics::Distribution spc
Definition: exec_stage.hh:114
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::ComputeUnit::numScalarALUs
int numScalarALUs
Definition: compute_unit.hh:250
gem5::ComputeUnit::numVectorALUs
int numVectorALUs
Definition: compute_unit.hh:246
vector_register_file.hh
gem5::ExecStage::dispStatusToStr
std::string dispStatusToStr(int j)
Definition: exec_stage.cc:113
gem5::ScheduleToExecute::readyInst
GPUDynInstPtr & readyInst(int func_unit_id)
Definition: comm.cc:129
gem5::statistics::Distribution::init
Distribution & init(Counter min, Counter max, Counter bkt)
Set the parameters of this distribution.
Definition: statistics.hh:2110
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ExecStage::ExecStageStats::numCyclesWithInstrIssued
statistics::Scalar numCyclesWithInstrIssued
Definition: exec_stage.hh:112
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::EMPTY
@ EMPTY
Definition: exec_stage.hh:63
gem5::ExecStage::idle_dur
uint64_t idle_dur
Definition: exec_stage.hh:99
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::ExecStage::ExecStage
ExecStage(const ComputeUnitParams &p, ComputeUnit &cu, ScheduleToExecute &from_schedule)
Definition: exec_stage.cc:47
gem5::ExecStage::collectStatistics
void collectStatistics(enum STAT_STATUS stage, int unitId)
Definition: exec_stage.cc:67
gem5::ExecStage::init
void init()
Definition: exec_stage.cc:61
gem5::IdleExec
@ IdleExec
Definition: exec_stage.hh:56
gem5::ArmISA::c
Bitfield< 29 > c
Definition: misc_types.hh:53
gem5::Wavefront::wfDynId
uint64_t wfDynId
Definition: wavefront.hh:228
gem5::DISPATCH_STATUS
DISPATCH_STATUS
Definition: exec_stage.hh:61
gem5::ExecStage::fromSchedule
ScheduleToExecute & fromSchedule
Definition: exec_stage.hh:93
name
const std::string & name()
Definition: trace.cc:49
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::ExecStage::ExecStageStats::ExecStageStats
ExecStageStats(statistics::Group *parent)
Definition: exec_stage.cc:203
gem5::STAT_STATUS
STAT_STATUS
Definition: exec_stage.hh:54
gem5::ExecStage::ExecStageStats::numCyclesWithNoIssue
statistics::Scalar numCyclesWithNoIssue
Definition: exec_stage.hh:110
gem5::ExecStage::initStatistics
void initStatistics()
Definition: exec_stage.cc:105
gem5::ScheduleToExecute::dispatchTransition
void dispatchTransition(const GPUDynInstPtr &gpu_dyn_inst, int func_unit_id, DISPATCH_STATUS disp_status)
Once the scheduler has chosen a winning WF for execution, and after the WF's oldest instruction's ope...
Definition: comm.cc:135
gem5::ExecStage::ExecStageStats::numTransActiveIdle
statistics::Scalar numTransActiveIdle
Definition: exec_stage.hh:108
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::PostExec
@ PostExec
Definition: exec_stage.hh:58
gem5::Wavefront::instructionBuffer
std::deque< GPUDynInstPtr > instructionBuffer
Definition: wavefront.hh:111
gem5::ExecStage::exec
void exec()
Definition: exec_stage.cc:154
trace.hh
gem5::ExecStage::dumpDispList
void dumpDispList()
Definition: exec_stage.cc:131
gem5::Wavefront::freeResources
void freeResources()
Definition: wavefront.cc:743
gem5::ExecStage::instrExecuted
bool instrExecuted
Definition: exec_stage.hh:97
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1037
exec_stage.hh
gem5::ComputeUnit::scheduleStage
ScheduleStage scheduleStage
Definition: compute_unit.hh:284
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ComputeUnit::numExeUnits
int numExeUnits() const
Definition: compute_unit.cc:233
gem5::Wavefront::simdId
const int simdId
Definition: wavefront.hh:101

Generated on Tue Sep 21 2021 12:25:23 for gem5 by doxygen 1.8.17