gem5  v21.1.0.2
bpred_unit.cc
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4  * Copyright (c) 2012 Mark D. Hill and David A. Wood
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42 
43 #include "cpu/pred/bpred_unit.hh"
44 
45 #include <algorithm>
46 
47 #include "arch/pcstate.hh"
48 #include "base/compiler.hh"
49 #include "base/trace.hh"
50 #include "config/the_isa.hh"
51 #include "debug/Branch.hh"
52 
53 namespace gem5
54 {
55 
56 namespace branch_prediction
57 {
58 
60  : SimObject(params),
61  numThreads(params.numThreads),
62  predHist(numThreads),
63  BTB(params.BTBEntries,
64  params.BTBTagSize,
65  params.instShiftAmt,
66  params.numThreads),
67  RAS(numThreads),
68  iPred(params.indirectBranchPred),
69  stats(this),
70  instShiftAmt(params.instShiftAmt)
71 {
72  for (auto& r : RAS)
73  r.init(params.RASSize);
74 }
75 
77  : statistics::Group(parent),
78  ADD_STAT(lookups, statistics::units::Count::get(), "Number of BP lookups"),
79  ADD_STAT(condPredicted, statistics::units::Count::get(),
80  "Number of conditional branches predicted"),
81  ADD_STAT(condIncorrect, statistics::units::Count::get(),
82  "Number of conditional branches incorrect"),
83  ADD_STAT(BTBLookups, statistics::units::Count::get(),
84  "Number of BTB lookups"),
85  ADD_STAT(BTBHits, statistics::units::Count::get(), "Number of BTB hits"),
86  ADD_STAT(BTBHitRatio, statistics::units::Ratio::get(), "BTB Hit Ratio",
87  BTBHits / BTBLookups),
88  ADD_STAT(RASUsed, statistics::units::Count::get(),
89  "Number of times the RAS was used to get a target."),
90  ADD_STAT(RASIncorrect, statistics::units::Count::get(),
91  "Number of incorrect RAS predictions."),
92  ADD_STAT(indirectLookups, statistics::units::Count::get(),
93  "Number of indirect predictor lookups."),
94  ADD_STAT(indirectHits, statistics::units::Count::get(),
95  "Number of indirect target hits."),
96  ADD_STAT(indirectMisses, statistics::units::Count::get(),
97  "Number of indirect misses."),
98  ADD_STAT(indirectMispredicted, statistics::units::Count::get(),
99  "Number of mispredicted indirect branches.")
100 {
102 }
103 
106 {
107  probing::PMUUPtr ptr;
108  ptr.reset(new probing::PMU(getProbeManager(), name));
109 
110  return ptr;
111 }
112 
113 void
115 {
116  ppBranches = pmuProbePoint("Branches");
117  ppMisses = pmuProbePoint("Misses");
118 }
119 
120 void
122 {
123  // We shouldn't have any outstanding requests when we resume from
124  // a drained system.
125  for (GEM5_VAR_USED const auto& ph : predHist)
126  assert(ph.empty());
127 }
128 
129 bool
130 BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
132 {
133  // See if branch predictor predicts taken.
134  // If so, get its target addr either from the BTB or the RAS.
135  // Save off record of branch stuff so the RAS can be fixed
136  // up once it's done.
137 
138  bool pred_taken = false;
139  TheISA::PCState target = pc;
140 
141  ++stats.lookups;
142  ppBranches->notify(1);
143 
144  void *bp_history = NULL;
145  void *indirect_history = NULL;
146 
147  if (inst->isUncondCtrl()) {
148  DPRINTF(Branch, "[tid:%i] [sn:%llu] "
149  "Unconditional control\n",
150  tid,seqNum);
151  pred_taken = true;
152  // Tell the BP there was an unconditional branch.
153  uncondBranch(tid, pc.instAddr(), bp_history);
154  } else {
156  pred_taken = lookup(tid, pc.instAddr(), bp_history);
157 
158  DPRINTF(Branch, "[tid:%i] [sn:%llu] "
159  "Branch predictor predicted %i for PC %s\n",
160  tid, seqNum, pred_taken, pc);
161  }
162 
163  const bool orig_pred_taken = pred_taken;
164  if (iPred) {
165  iPred->genIndirectInfo(tid, indirect_history);
166  }
167 
168  DPRINTF(Branch, "[tid:%i] [sn:%llu] "
169  "Creating prediction history "
170  "for PC %s\n", tid, seqNum, pc);
171 
172  PredictorHistory predict_record(seqNum, pc.instAddr(), pred_taken,
173  bp_history, indirect_history, tid, inst);
174 
175  // Now lookup in the BTB or RAS.
176  if (pred_taken) {
177  if (inst->isReturn()) {
178  ++stats.RASUsed;
179  predict_record.wasReturn = true;
180  // If it's a function return call, then look up the address
181  // in the RAS.
182  TheISA::PCState rasTop = RAS[tid].top();
183  target = inst->buildRetPC(pc, rasTop);
184 
185  // Record the top entry of the RAS, and its index.
186  predict_record.usedRAS = true;
187  predict_record.RASIndex = RAS[tid].topIdx();
188  predict_record.RASTarget = rasTop;
189 
190  RAS[tid].pop();
191 
192  DPRINTF(Branch, "[tid:%i] [sn:%llu] Instruction %s is a return, "
193  "RAS predicted target: %s, RAS index: %i\n",
194  tid, seqNum, pc, target, predict_record.RASIndex);
195  } else {
196 
197  if (inst->isCall()) {
198  RAS[tid].push(pc);
199  predict_record.pushedRAS = true;
200 
201  // Record that it was a call so that the top RAS entry can
202  // be popped off if the speculation is incorrect.
203  predict_record.wasCall = true;
204 
205  DPRINTF(Branch,
206  "[tid:%i] [sn:%llu] Instruction %s was a call, adding "
207  "%s to the RAS index: %i\n",
208  tid, seqNum, pc, pc, RAS[tid].topIdx());
209  }
210 
211  if (inst->isDirectCtrl() || !iPred) {
212  ++stats.BTBLookups;
213  // Check BTB on direct branches
214  if (BTB.valid(pc.instAddr(), tid)) {
215  ++stats.BTBHits;
216  // If it's not a return, use the BTB to get target addr.
217  target = BTB.lookup(pc.instAddr(), tid);
218  DPRINTF(Branch,
219  "[tid:%i] [sn:%llu] Instruction %s predicted "
220  "target is %s\n",
221  tid, seqNum, pc, target);
222  } else {
223  DPRINTF(Branch, "[tid:%i] [sn:%llu] BTB doesn't have a "
224  "valid entry\n",tid,seqNum);
225  pred_taken = false;
226  predict_record.predTaken = pred_taken;
227  // The Direction of the branch predictor is altered
228  // because the BTB did not have an entry
229  // The predictor needs to be updated accordingly
230  if (!inst->isCall() && !inst->isReturn()) {
231  btbUpdate(tid, pc.instAddr(), bp_history);
232  DPRINTF(Branch,
233  "[tid:%i] [sn:%llu] btbUpdate "
234  "called for %s\n",
235  tid, seqNum, pc);
236  } else if (inst->isCall() && !inst->isUncondCtrl()) {
237  RAS[tid].pop();
238  predict_record.pushedRAS = false;
239  }
240  inst->advancePC(target);
241  }
242  } else {
243  predict_record.wasIndirect = true;
245  //Consult indirect predictor on indirect control
246  if (iPred->lookup(pc.instAddr(), target, tid)) {
247  // Indirect predictor hit
249  DPRINTF(Branch,
250  "[tid:%i] [sn:%llu] "
251  "Instruction %s predicted "
252  "indirect target is %s\n",
253  tid, seqNum, pc, target);
254  } else {
256  pred_taken = false;
257  predict_record.predTaken = pred_taken;
258  DPRINTF(Branch,
259  "[tid:%i] [sn:%llu] "
260  "Instruction %s no indirect "
261  "target\n",
262  tid, seqNum, pc);
263  if (!inst->isCall() && !inst->isReturn()) {
264 
265  } else if (inst->isCall() && !inst->isUncondCtrl()) {
266  RAS[tid].pop();
267  predict_record.pushedRAS = false;
268  }
269  inst->advancePC(target);
270  }
271  iPred->recordIndirect(pc.instAddr(), target.instAddr(), seqNum,
272  tid);
273  }
274  }
275  } else {
276  if (inst->isReturn()) {
277  predict_record.wasReturn = true;
278  }
279  inst->advancePC(target);
280  }
281  predict_record.target = target.instAddr();
282 
283  pc = target;
284 
285  if (iPred) {
286  // Update the indirect predictor with the direction prediction
287  // Note that this happens after indirect lookup, so it does not use
288  // the new information
289  // Note also that we use orig_pred_taken instead of pred_taken in
290  // as this is the actual outcome of the direction prediction
291  iPred->updateDirectionInfo(tid, orig_pred_taken);
292  }
293 
294  predHist[tid].push_front(predict_record);
295 
296  DPRINTF(Branch,
297  "[tid:%i] [sn:%llu] History entry added. "
298  "predHist.size(): %i\n",
299  tid, seqNum, predHist[tid].size());
300 
301  return pred_taken;
302 }
303 
304 void
306 {
307  DPRINTF(Branch, "[tid:%i] Committing branches until "
308  "sn:%llu]\n", tid, done_sn);
309 
310  while (!predHist[tid].empty() &&
311  predHist[tid].back().seqNum <= done_sn) {
312  // Update the branch predictor with the correct results.
313  update(tid, predHist[tid].back().pc,
314  predHist[tid].back().predTaken,
315  predHist[tid].back().bpHistory, false,
316  predHist[tid].back().inst,
317  predHist[tid].back().target);
318 
319  if (iPred) {
320  iPred->commit(done_sn, tid, predHist[tid].back().indirectHistory);
321  }
322 
323  predHist[tid].pop_back();
324  }
325 }
326 
327 void
328 BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid)
329 {
330  History &pred_hist = predHist[tid];
331 
332  if (iPred) {
333  iPred->squash(squashed_sn, tid);
334  }
335 
336  while (!pred_hist.empty() &&
337  pred_hist.front().seqNum > squashed_sn) {
338  if (pred_hist.front().usedRAS) {
339  DPRINTF(Branch, "[tid:%i] [squash sn:%llu]"
340  " Restoring top of RAS to: %i,"
341  " target: %s\n", tid, squashed_sn,
342  pred_hist.front().RASIndex, pred_hist.front().RASTarget);
343 
344  RAS[tid].restore(pred_hist.front().RASIndex,
345  pred_hist.front().RASTarget);
346  } else if (pred_hist.front().wasCall && pred_hist.front().pushedRAS) {
347  // Was a call but predicated false. Pop RAS here
348  DPRINTF(Branch, "[tid:%i] [squash sn:%llu] Squashing"
349  " Call [sn:%llu] PC: %s Popping RAS\n", tid, squashed_sn,
350  pred_hist.front().seqNum, pred_hist.front().pc);
351  RAS[tid].pop();
352  }
353 
354  // This call should delete the bpHistory.
355  squash(tid, pred_hist.front().bpHistory);
356  if (iPred) {
357  iPred->deleteIndirectInfo(tid, pred_hist.front().indirectHistory);
358  }
359 
360  DPRINTF(Branch, "[tid:%i] [squash sn:%llu] "
361  "Removing history for [sn:%llu] "
362  "PC %#x\n", tid, squashed_sn, pred_hist.front().seqNum,
363  pred_hist.front().pc);
364 
365  pred_hist.pop_front();
366 
367  DPRINTF(Branch, "[tid:%i] [squash sn:%llu] predHist.size(): %i\n",
368  tid, squashed_sn, predHist[tid].size());
369  }
370 }
371 
372 void
373 BPredUnit::squash(const InstSeqNum &squashed_sn,
374  const TheISA::PCState &corrTarget,
375  bool actually_taken, ThreadID tid)
376 {
377  // Now that we know that a branch was mispredicted, we need to undo
378  // all the branches that have been seen up until this branch and
379  // fix up everything.
380  // NOTE: This should be call conceivably in 2 scenarios:
381  // (1) After an branch is executed, it updates its status in the ROB
382  // The commit stage then checks the ROB update and sends a signal to
383  // the fetch stage to squash history after the mispredict
384  // (2) In the decode stage, you can find out early if a unconditional
385  // PC-relative, branch was predicted incorrectly. If so, a signal
386  // to the fetch stage is sent to squash history after the mispredict
387 
388  History &pred_hist = predHist[tid];
389 
391  ppMisses->notify(1);
392 
393  DPRINTF(Branch, "[tid:%i] Squashing from sequence number %i, "
394  "setting target to %s\n", tid, squashed_sn, corrTarget);
395 
396  // Squash All Branches AFTER this mispredicted branch
397  squash(squashed_sn, tid);
398 
399  // If there's a squash due to a syscall, there may not be an entry
400  // corresponding to the squash. In that case, don't bother trying to
401  // fix up the entry.
402  if (!pred_hist.empty()) {
403 
404  auto hist_it = pred_hist.begin();
405  //HistoryIt hist_it = find(pred_hist.begin(), pred_hist.end(),
406  // squashed_sn);
407 
408  //assert(hist_it != pred_hist.end());
409  if (pred_hist.front().seqNum != squashed_sn) {
410  DPRINTF(Branch, "Front sn %i != Squash sn %i\n",
411  pred_hist.front().seqNum, squashed_sn);
412 
413  assert(pred_hist.front().seqNum == squashed_sn);
414  }
415 
416 
417  if ((*hist_it).usedRAS) {
419  DPRINTF(Branch,
420  "[tid:%i] [squash sn:%llu] Incorrect RAS [sn:%llu]\n",
421  tid, squashed_sn, hist_it->seqNum);
422  }
423 
424  // There are separate functions for in-order and out-of-order
425  // branch prediction, but not for update. Therefore, this
426  // call should take into account that the mispredicted branch may
427  // be on the wrong path (i.e., OoO execution), and that the counter
428  // counter table(s) should not be updated. Thus, this call should
429  // restore the state of the underlying predictor, for instance the
430  // local/global histories. The counter tables will be updated when
431  // the branch actually commits.
432 
433  // Remember the correct direction for the update at commit.
434  pred_hist.front().predTaken = actually_taken;
435  pred_hist.front().target = corrTarget.instAddr();
436 
437  update(tid, (*hist_it).pc, actually_taken,
438  pred_hist.front().bpHistory, true, pred_hist.front().inst,
439  corrTarget.instAddr());
440 
441  if (iPred) {
443  pred_hist.front().indirectHistory, actually_taken);
444  }
445 
446  if (actually_taken) {
447  if (hist_it->wasReturn && !hist_it->usedRAS) {
448  DPRINTF(Branch, "[tid:%i] [squash sn:%llu] "
449  "Incorrectly predicted "
450  "return [sn:%llu] PC: %#x\n", tid, squashed_sn,
451  hist_it->seqNum,
452  hist_it->pc);
453  RAS[tid].pop();
454  hist_it->usedRAS = true;
455  }
456  if (hist_it->wasIndirect) {
458  if (iPred) {
460  hist_it->seqNum, pred_hist.front().indirectHistory,
461  corrTarget, tid);
462  }
463  } else {
464  DPRINTF(Branch,"[tid:%i] [squash sn:%llu] "
465  "BTB Update called for [sn:%llu] "
466  "PC %#x\n", tid, squashed_sn,
467  hist_it->seqNum, hist_it->pc);
468 
469  BTB.update((*hist_it).pc, corrTarget, tid);
470  }
471  } else {
472  //Actually not Taken
473  if (hist_it->usedRAS) {
474  DPRINTF(Branch,
475  "[tid:%i] [squash sn:%llu] Incorrectly predicted "
476  "return [sn:%llu] PC: %#x Restoring RAS\n", tid,
477  squashed_sn,
478  hist_it->seqNum, hist_it->pc);
479  DPRINTF(Branch,
480  "[tid:%i] [squash sn:%llu] Restoring top of RAS "
481  "to: %i, target: %s\n", tid, squashed_sn,
482  hist_it->RASIndex, hist_it->RASTarget);
483  RAS[tid].restore(hist_it->RASIndex, hist_it->RASTarget);
484  hist_it->usedRAS = false;
485  } else if (hist_it->wasCall && hist_it->pushedRAS) {
486  //Was a Call but predicated false. Pop RAS here
487  DPRINTF(Branch,
488  "[tid:%i] [squash sn:%llu] "
489  "Incorrectly predicted "
490  "Call [sn:%llu] PC: %s Popping RAS\n",
491  tid, squashed_sn,
492  hist_it->seqNum, hist_it->pc);
493  RAS[tid].pop();
494  hist_it->pushedRAS = false;
495  }
496  }
497  } else {
498  DPRINTF(Branch, "[tid:%i] [sn:%llu] pred_hist empty, can't "
499  "update\n", tid, squashed_sn);
500  }
501 }
502 
503 void
505 {
506  int i = 0;
507  for (const auto& ph : predHist) {
508  if (!ph.empty()) {
509  auto pred_hist_it = ph.begin();
510 
511  cprintf("predHist[%i].size(): %i\n", i++, ph.size());
512 
513  while (pred_hist_it != ph.end()) {
514  cprintf("sn:%llu], PC:%#x, tid:%i, predTaken:%i, "
515  "bpHistory:%#x\n",
516  pred_hist_it->seqNum, pred_hist_it->pc,
517  pred_hist_it->tid, pred_hist_it->predTaken,
518  pred_hist_it->bpHistory);
519  pred_hist_it++;
520  }
521 
522  cprintf("\n");
523  }
524  }
525 }
526 
527 } // namespace branch_prediction
528 } // namespace gem5
gem5::branch_prediction::BPredUnit::update
void update(const InstSeqNum &done_sn, ThreadID tid)
Tells the branch predictor to commit any updates until the given sequence number.
Definition: bpred_unit.cc:305
gem5::branch_prediction::BPredUnit::pmuProbePoint
probing::PMUUPtr pmuProbePoint(const char *name)
Helper method to instantiate probe points belonging to this object.
Definition: bpred_unit.cc:105
gem5::branch_prediction::BPredUnit::BPredUnit
BPredUnit(const Params &p)
Definition: bpred_unit.cc:59
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::branch_prediction::BPredUnit::PredictorHistory::RASIndex
unsigned RASIndex
The RAS index of the instruction (only valid if a call).
Definition: bpred_unit.hh:233
gem5::branch_prediction::BPredUnit::PredictorHistory::target
Addr target
Target of the branch.
Definition: bpred_unit.hh:259
gem5::branch_prediction::IndirectPredictor::genIndirectInfo
virtual void genIndirectInfo(ThreadID tid, void *&indirect_history)=0
gem5::branch_prediction::BPredUnit::PredictorHistory::wasIndirect
bool wasIndirect
Wether this instruction was an indirect branch.
Definition: bpred_unit.hh:254
gem5::branch_prediction::BPredUnit::PredictorHistory::wasCall
bool wasCall
Whether or not the instruction was a call.
Definition: bpred_unit.hh:248
gem5::branch_prediction::BPredUnit::Params
BranchPredictorParams Params
Definition: bpred_unit.hh:71
gem5::branch_prediction::BPredUnit::stats
gem5::branch_prediction::BPredUnit::BPredUnitStats stats
gem5::branch_prediction::IndirectPredictor::lookup
virtual bool lookup(Addr br_addr, TheISA::PCState &br_target, ThreadID tid)=0
gem5::branch_prediction::IndirectPredictor::recordIndirect
virtual void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num, ThreadID tid)=0
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::branch_prediction::IndirectPredictor::deleteIndirectInfo
virtual void deleteIndirectInfo(ThreadID tid, void *indirect_history)=0
gem5::branch_prediction::BPredUnit::BPredUnitStats::BTBHits
statistics::Scalar BTBHits
Stat for number of BTB hits.
Definition: bpred_unit.hh:300
gem5::branch_prediction::BPredUnit::BPredUnitStats::indirectMispredicted
statistics::Scalar indirectMispredicted
Stat for the number of indirect target mispredictions.
Definition: bpred_unit.hh:315
gem5::RefCountingPtr< StaticInst >
gem5::branch_prediction::DefaultBTB::update
void update(Addr instPC, const TheISA::PCState &targetPC, ThreadID tid)
Updates the BTB with the target of a branch.
Definition: btb.cc:134
gem5::branch_prediction::BPredUnit::PredictorHistory::RASTarget
TheISA::PCState RASTarget
The RAS target (only valid if a return).
Definition: bpred_unit.hh:230
gem5::branch_prediction::BPredUnit::PredictorHistory::wasReturn
bool wasReturn
Whether or not the instruction was a return.
Definition: bpred_unit.hh:251
gem5::branch_prediction::BPredUnit::predHist
std::vector< History > predHist
The per-thread predictor history.
Definition: bpred_unit.hh:276
gem5::branch_prediction::BPredUnit::BPredUnitStats::condIncorrect
statistics::Scalar condIncorrect
Stat for number of conditional branches predicted incorrectly.
Definition: bpred_unit.hh:296
gem5::StaticInst::isReturn
bool isReturn() const
Definition: static_inst.hh:184
gem5::branch_prediction::BPredUnit::BPredUnitStats::BTBLookups
statistics::Scalar BTBLookups
Stat for number of BTB lookups.
Definition: bpred_unit.hh:298
gem5::branch_prediction::BPredUnit::PredictorHistory
Definition: bpred_unit.hh:194
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::probing::PMUUPtr
std::unique_ptr< PMU > PMUUPtr
Definition: pmu.hh:61
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::branch_prediction::BPredUnit::BPredUnitStats::indirectMisses
statistics::Scalar indirectMisses
Stat for the number of indirect target misses.
Definition: bpred_unit.hh:313
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::branch_prediction::BPredUnit::BTB
DefaultBTB BTB
The BTB.
Definition: bpred_unit.hh:279
gem5::branch_prediction::DefaultBTB::lookup
TheISA::PCState lookup(Addr instPC, ThreadID tid)
Looks up an address in the BTB.
Definition: btb.cc:116
gem5::branch_prediction::BPredUnit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: bpred_unit.cc:121
gem5::branch_prediction::IndirectPredictor::updateDirectionInfo
virtual void updateDirectionInfo(ThreadID tid, bool actually_taken)=0
gem5::branch_prediction::BPredUnit::ppBranches
probing::PMUUPtr ppBranches
Branches seen by the branch predictor.
Definition: bpred_unit.hh:342
gem5::branch_prediction::BPredUnit::BPredUnitStats::indirectHits
statistics::Scalar indirectHits
Stat for the number of indirect target hits.
Definition: bpred_unit.hh:311
compiler.hh
gem5::branch_prediction::BPredUnit::BPredUnitStats::BPredUnitStats
BPredUnitStats(statistics::Group *parent)
Definition: bpred_unit.cc:76
gem5::StaticInst::isDirectCtrl
bool isDirectCtrl() const
Definition: static_inst.hh:185
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::branch_prediction::BPredUnit::squash
void squash(const InstSeqNum &squashed_sn, ThreadID tid)
Squashes all outstanding updates until a given sequence number.
Definition: bpred_unit.cc:328
gem5::statistics::DataWrap::precision
Derived & precision(int _precision)
Set the precision and marks this stat to print at the end of simulation.
Definition: statistics.hh:343
gem5::branch_prediction::BPredUnit::BPredUnitStats::RASIncorrect
statistics::Scalar RASIncorrect
Stat for number of times the RAS is incorrect.
Definition: bpred_unit.hh:306
gem5::branch_prediction::BPredUnit::PredictorHistory::pushedRAS
bool pushedRAS
Definition: bpred_unit.hh:245
gem5::branch_prediction::BPredUnit::PredictorHistory::predTaken
bool predTaken
Whether or not it was predicted taken.
Definition: bpred_unit.hh:239
gem5::branch_prediction::BPredUnit::BPredUnitStats::condPredicted
statistics::Scalar condPredicted
Stat for number of conditional branches predicted.
Definition: bpred_unit.hh:294
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::branch_prediction::BPredUnit::BPredUnitStats::lookups
statistics::Scalar lookups
Stat for number of BP lookups.
Definition: bpred_unit.hh:292
gem5::SimObject::getProbeManager
ProbeManager * getProbeManager()
Get the probe manager for this object.
Definition: sim_object.cc:120
gem5::branch_prediction::BPredUnit::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: bpred_unit.cc:114
gem5::branch_prediction::BPredUnit::RAS
std::vector< ReturnAddrStack > RAS
The per-thread return address stack.
Definition: bpred_unit.hh:282
gem5::branch_prediction::BPredUnit::lookup
virtual bool lookup(ThreadID tid, Addr instPC, void *&bp_history)=0
Looks up a given PC in the BP to see if it is taken or not taken.
bpred_unit.hh
gem5::SparcISA::Branch
Base class for branch operations.
Definition: branch.hh:48
gem5::branch_prediction::BPredUnit::PredictorHistory::usedRAS
bool usedRAS
Whether or not the RAS was used.
Definition: bpred_unit.hh:242
gem5::branch_prediction::BPredUnit::uncondBranch
virtual void uncondBranch(ThreadID tid, Addr pc, void *&bp_history)=0
gem5::branch_prediction::IndirectPredictor::commit
virtual void commit(InstSeqNum seq_num, ThreadID tid, void *indirect_history)=0
std::deque
STL deque class.
Definition: stl.hh:44
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::StaticInst::isCall
bool isCall() const
Definition: static_inst.hh:183
gem5::branch_prediction::BPredUnit::BPredUnitStats::indirectLookups
statistics::Scalar indirectLookups
Stat for the number of indirect target lookups.
Definition: bpred_unit.hh:309
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::branch_prediction::BPredUnit::iPred
IndirectPredictor * iPred
The indirect target predictor.
Definition: bpred_unit.hh:285
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::branch_prediction::IndirectPredictor::squash
virtual void squash(InstSeqNum seq_num, ThreadID tid)=0
gem5::branch_prediction::BPredUnit::ppMisses
probing::PMUUPtr ppMisses
Miss-predicted branches.
Definition: bpred_unit.hh:345
trace.hh
gem5::StaticInst::isUncondCtrl
bool isUncondCtrl() const
Definition: static_inst.hh:188
gem5::branch_prediction::IndirectPredictor::recordTarget
virtual void recordTarget(InstSeqNum seq_num, void *indirect_history, const TheISA::PCState &target, ThreadID tid)=0
gem5::branch_prediction::IndirectPredictor::changeDirectionPrediction
virtual void changeDirectionPrediction(ThreadID tid, void *indirect_history, bool actually_taken)=0
gem5::branch_prediction::BPredUnit::BPredUnitStats::BTBHitRatio
statistics::Formula BTBHitRatio
Stat for the ratio between BTB hits and BTB lookups.
Definition: bpred_unit.hh:302
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::StaticInst::buildRetPC
virtual TheISA::PCState buildRetPC(const TheISA::PCState &cur_pc, const TheISA::PCState &call_pc) const
Definition: static_inst.hh:326
gem5::branch_prediction::DefaultBTB::valid
bool valid(Addr instPC, ThreadID tid)
Checks if a branch is in the BTB.
Definition: btb.cc:95
gem5::branch_prediction::BPredUnit::dump
void dump()
Definition: bpred_unit.cc:504
gem5::StaticInst::advancePC
virtual void advancePC(TheISA::PCState &pc_state) const =0
gem5::branch_prediction::BPredUnit::predict
bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, TheISA::PCState &pc, ThreadID tid)
Predicts whether or not the instruction is a taken branch, and the target of the branch if it is take...
Definition: bpred_unit.cc:130
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::branch_prediction::BPredUnit::BPredUnitStats::RASUsed
statistics::Scalar RASUsed
Stat for number of times the RAS is used to get a target.
Definition: bpred_unit.hh:304
gem5::branch_prediction::BPredUnit::btbUpdate
virtual void btbUpdate(ThreadID tid, Addr instPC, void *&bp_history)=0
If a branch is not taken, because the BTB address is invalid or missing, this function sets the appro...

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