gem5  v22.0.0.1
Classes | Namespaces
generic_timer.hh File Reference
#include <cstdint>
#include <vector>
#include "arch/arm/isa_device.hh"
#include "arch/arm/system.hh"
#include "base/addr_range.hh"
#include "base/bitunion.hh"
#include "base/types.hh"
#include "dev/arm/base_gic.hh"
#include "dev/arm/generic_timer_miscregs_types.hh"
#include "sim/drain.hh"
#include "sim/eventq.hh"
#include "sim/serialize.hh"
#include "sim/sim_object.hh"

Go to the source code of this file.


class  gem5::SystemCounterListener
 Abstract class for elements whose events depend on the counting speed of the System Counter. More...
class  gem5::SystemCounter
 Global system counter. More...
class  gem5::ArchTimer
 Per-CPU architected timer. More...
class  gem5::ArchTimerKvm
class  gem5::GenericTimer
class  gem5::GenericTimer::CoreTimers
struct  gem5::GenericTimer::CoreTimers::EventStream
class  gem5::GenericTimerISA
class  gem5::GenericTimerFrame
class  gem5::GenericTimerMem


 Reference material can be found at the JEDEC website: UFS standard UFS HCI specification

Detailed Description

This module implements the global system counter and the local per-CPU architected timers as specified by the ARM Generic Timer extension: Arm ARM (ARM DDI 0487E.a) D11.1.2 - The system counter D11.2 - The AArch64 view of the Generic Timer G6.2 - The AArch32 view of the Generic Timer I2 - System Level Implementation of the Generic Timer

Definition in file generic_timer.hh.

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