gem5  v21.1.0.2
generic_timer.hh
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37 
38 #ifndef __DEV_ARM_GENERIC_TIMER_HH__
39 #define __DEV_ARM_GENERIC_TIMER_HH__
40 
41 #include <cstdint>
42 #include <vector>
43 
44 #include "arch/arm/isa_device.hh"
45 #include "arch/arm/system.hh"
46 #include "base/addr_range.hh"
47 #include "base/bitunion.hh"
48 #include "base/types.hh"
49 #include "dev/arm/base_gic.hh"
51 #include "sim/drain.hh"
52 #include "sim/eventq.hh"
53 #include "sim/serialize.hh"
54 #include "sim/sim_object.hh"
55 
64 
65 namespace gem5
66 {
67 
68 class Checkpoint;
69 struct SystemCounterParams;
70 struct GenericTimerParams;
71 struct GenericTimerFrameParams;
72 struct GenericTimerMemParams;
73 
77 {
78  public:
81  virtual void notify(void) = 0;
82 };
83 
86 class SystemCounter : public SimObject
87 {
88  protected:
90  bool _enabled;
92  uint32_t _freq;
94  uint64_t _value;
96  uint64_t _increment;
106 
109 
111  static constexpr size_t MAX_FREQ_ENTRIES = 1004;
112 
113  public:
114  SystemCounter(const SystemCounterParams &p);
115 
118  static void validateCounterRef(SystemCounter *sys_cnt);
119 
121  bool enabled() const { return _enabled; }
123  uint32_t freq() const { return _freq; }
125  uint64_t value();
127  uint64_t increment() const { return _increment; }
131  size_t activeFreqEntry() const { return _activeFreqEntry; }
133  Tick period() const { return _period; }
134 
136  void enable();
138  void disable();
139 
143  void freqUpdateSchedule(size_t new_freq_entry);
144 
146  void setValue(uint64_t new_value);
147 
149  void registerListener(SystemCounterListener *listener);
150 
152  Tick whenValue(uint64_t target_val);
153  Tick whenValue(uint64_t cur_val, uint64_t target_val) const;
154 
155  void serialize(CheckpointOut &cp) const override;
156  void unserialize(CheckpointIn &cp) override;
157 
158  private:
159  // Disable copying
160  SystemCounter(const SystemCounter &c);
161 
166  void freqUpdateCallback();
167 
169  void updateValue(void);
170 
172  void updateTick(void);
173 
175  void notifyListeners(void) const;
176 };
177 
180  public Serializable
181 {
182  protected:
184  BitUnion32(ArchTimerCtrl)
185  Bitfield<0> enable;
186  Bitfield<1> imask;
187  Bitfield<2> istatus;
188  EndBitUnion(ArchTimerCtrl)
189 
190 
191  const std::string _name;
192 
195 
197 
199 
201  ArchTimerCtrl _control;
203  uint64_t _counterLimit;
205  uint64_t _offset;
206 
211  void updateCounter();
212 
214  void counterLimitReached();
216 
217  virtual bool scheduleEvents() { return true; }
218 
219  public:
220  ArchTimer(const std::string &name,
221  SimObject &parent,
222  SystemCounter &sysctr,
223  ArmInterruptPin *interrupt);
224 
226  std::string name() const { return _name; }
227 
229  uint64_t compareValue() const { return _counterLimit; }
231  void setCompareValue(uint64_t val);
232 
234  uint32_t timerValue() const { return _counterLimit - value(); }
236  void setTimerValue(uint32_t val);
237 
239  uint32_t control() const { return _control; }
240  void setControl(uint32_t val);
241 
242  uint64_t offset() const { return _offset; }
243  void setOffset(uint64_t val);
244 
246  uint64_t value() const;
247  Tick whenValue(uint64_t target_val) {
248  return _systemCounter.whenValue(value(), target_val);
249  }
250 
251  void notify(void) override;
252 
253  // Serializable
254  void serialize(CheckpointOut &cp) const override;
255  void unserialize(CheckpointIn &cp) override;
256 
257  // Drainable
258  DrainState drain() override;
259  void drainResume() override;
260 
261  private:
262  // Disable copying
263  ArchTimer(const ArchTimer &t);
264 };
265 
266 class ArchTimerKvm : public ArchTimer
267 {
268  private:
270 
271  public:
272  ArchTimerKvm(const std::string &name,
273  ArmSystem &system,
274  SimObject &parent,
275  SystemCounter &sysctr,
276  ArmInterruptPin *interrupt)
277  : ArchTimer(name, parent, sysctr, interrupt), system(system) {}
278 
279  protected:
280  // For ArchTimer's in a GenericTimerISA with Kvm execution about
281  // to begin, skip rescheduling the event.
282  // Otherwise, we should reschedule the event (if necessary).
283  bool scheduleEvents() override {
284  return !system.validKvmEnvironment();
285  }
286 };
287 
288 class GenericTimer : public SimObject
289 {
290  public:
292 
293  GenericTimer(const Params &p);
294 
295  void serialize(CheckpointOut &cp) const override;
296  void unserialize(CheckpointIn &cp) override;
297 
298  public:
299  void setMiscReg(int misc_reg, unsigned cpu, RegVal val);
300  RegVal readMiscReg(int misc_reg, unsigned cpu);
301 
302  protected:
304  {
305  public:
306  CoreTimers(GenericTimer &_parent, ArmSystem &system, unsigned cpu,
307  ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS,
308  ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp);
309 
312 
314  uint32_t cntfrq;
315 
317  ArmISA::CNTKCTL cntkctl;
318 
320  ArmISA::CNTHCTL cnthctl;
321 
324 
329 
334 
335  // Event Stream. Events are generated based on a configurable
336  // transitionBit over the counter value. transitionTo indicates
337  // the transition direction (0->1 or 1->0)
338  struct EventStream
339  {
341  uint8_t transitionTo;
342  uint8_t transitionBit;
343 
344  uint64_t
345  eventTargetValue(uint64_t val) const
346  {
347  uint64_t bit_val = bits(val, transitionBit);
348  uint64_t ret_val = mbits(val, 63, transitionBit);
349  uint64_t incr_val = 1 << transitionBit;
350  if (bit_val == transitionTo)
351  incr_val *= 2;
352  return ret_val + incr_val;
353  }
354  };
355 
360  void eventStreamCallback() const;
361  void schedNextEvent(EventStream &ev_stream, ArchTimer &timer);
362 
363  void notify(void) override;
364 
365  void serialize(CheckpointOut &cp) const override;
366  void unserialize(CheckpointIn &cp) override;
367 
368  private:
369  // Disable copying
370  CoreTimers(const CoreTimers &c);
371  };
372 
373  CoreTimers &getTimers(int cpu_id);
374  void createTimers(unsigned cpus);
375 
378 
381 
382  protected: // Configuration
385 
386  void handleStream(CoreTimers::EventStream *ev_stream,
387  ArchTimer *timer, RegVal old_cnt_ctl, RegVal cnt_ctl);
388 };
389 
391 {
392  public:
393  GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
394  : parent(_parent), cpu(_cpu) {}
395 
396  void setMiscReg(int misc_reg, RegVal val) override;
397  RegVal readMiscReg(int misc_reg) override;
398 
399  protected:
401  unsigned cpu;
402 };
403 
405 {
406  public:
407  GenericTimerFrame(const GenericTimerFrameParams &p);
408 
409  void serialize(CheckpointOut &cp) const override;
410  void unserialize(CheckpointIn &cp) override;
411 
413  bool hasVirtualTimer() const;
414 
417  uint64_t getVirtOffset() const;
418 
421  void setVirtOffset(uint64_t new_offset);
422 
424  bool hasEl0View() const;
425 
427  uint8_t getAccessBits() const;
428 
430  void setAccessBits(uint8_t data);
431 
433  bool hasNonSecureAccess() const;
434 
437  void setNonSecureAccess();
438 
440  bool hasReadableVoff() const;
441 
442  protected:
443  AddrRangeList getAddrRanges() const override;
444  Tick read(PacketPtr pkt) override;
445  Tick write(PacketPtr pkt) override;
446 
447  private:
449  uint64_t timerRead(Addr addr, size_t size, bool is_sec, bool to_el0) const;
450  void timerWrite(Addr addr, size_t size, uint64_t data, bool is_sec,
451  bool to_el0);
454 
455  static const Addr TIMER_CNTPCT_LO = 0x00;
456  static const Addr TIMER_CNTPCT_HI = 0x04;
457  static const Addr TIMER_CNTVCT_LO = 0x08;
458  static const Addr TIMER_CNTVCT_HI = 0x0c;
459  static const Addr TIMER_CNTFRQ = 0x10;
460  static const Addr TIMER_CNTEL0ACR = 0x14;
461  static const Addr TIMER_CNTVOFF_LO = 0x18;
462  static const Addr TIMER_CNTVOFF_HI = 0x1c;
463  static const Addr TIMER_CNTP_CVAL_LO = 0x20;
464  static const Addr TIMER_CNTP_CVAL_HI = 0x24;
465  static const Addr TIMER_CNTP_TVAL = 0x28;
466  static const Addr TIMER_CNTP_CTL = 0x2c;
467  static const Addr TIMER_CNTV_CVAL_LO = 0x30;
468  static const Addr TIMER_CNTV_CVAL_HI = 0x34;
469  static const Addr TIMER_CNTV_TVAL = 0x38;
470  static const Addr TIMER_CNTV_CTL = 0x3c;
471 
474 
477 
481 
483  BitUnion8(AccessBits)
484  Bitfield<5> rwpt;
485  Bitfield<4> rwvt;
486  Bitfield<3> rvoff;
487  Bitfield<2> rfrq;
488  Bitfield<1> rvct;
489  Bitfield<0> rpct;
490  EndBitUnion(AccessBits)
491  AccessBits accessBits;
492 
493  // Reports access properties of the CNTEL0Base register frame elements
494  BitUnion16(AccessBitsEl0)
495  Bitfield<9> pten;
496  Bitfield<8> vten;
497  Bitfield<1> vcten;
498  Bitfield<0> pcten;
499  EndBitUnion(AccessBitsEl0)
500  AccessBitsEl0 accessBitsEl0;
501 
504 
506 };
507 
509 {
510  public:
511  GenericTimerMem(const GenericTimerMemParams &p);
512 
515  static void validateFrameRange(const AddrRange &range);
516 
520  static bool validateAccessPerm(ArmSystem &sys, bool is_sec);
521 
522  protected:
523  AddrRangeList getAddrRanges() const override;
524  Tick read(PacketPtr pkt) override;
525  Tick write(PacketPtr pkt) override;
526 
527  private:
529  uint64_t counterCtrlRead(Addr addr, size_t size, bool is_sec) const;
530  void counterCtrlWrite(Addr addr, size_t size, uint64_t data, bool is_sec);
532 
533  BitUnion32(CNTCR)
534  Bitfield<17,8> fcreq;
535  Bitfield<2> scen;
536  Bitfield<1> hdbg;
537  Bitfield<0> en;
538  EndBitUnion(CNTCR)
539 
540  BitUnion32(CNTSR)
541  Bitfield<31,8> fcack;
542  EndBitUnion(CNTSR)
543 
544  static const Addr COUNTER_CTRL_CNTCR = 0x00;
545  static const Addr COUNTER_CTRL_CNTSR = 0x04;
546  static const Addr COUNTER_CTRL_CNTCV_LO = 0x08;
547  static const Addr COUNTER_CTRL_CNTCV_HI = 0x0c;
548  static const Addr COUNTER_CTRL_CNTSCR = 0x10;
549  static const Addr COUNTER_CTRL_CNTID = 0x1c;
550  static const Addr COUNTER_CTRL_CNTFID = 0x20;
551 
553  uint64_t counterStatusRead(Addr addr, size_t size) const;
554  void counterStatusWrite(Addr addr, size_t size, uint64_t data);
556 
557  static const Addr COUNTER_STATUS_CNTCV_LO = 0x00;
558  static const Addr COUNTER_STATUS_CNTCV_HI = 0x04;
559 
561  uint64_t timerCtrlRead(Addr addr, size_t size, bool is_sec) const;
562  void timerCtrlWrite(Addr addr, size_t size, uint64_t data, bool is_sec);
564 
566  uint32_t cnttidr;
567 
568  static const Addr TIMER_CTRL_CNTFRQ = 0x00;
569  static const Addr TIMER_CTRL_CNTNSAR = 0x04;
570  static const Addr TIMER_CTRL_CNTTIDR = 0x08;
571  static const Addr TIMER_CTRL_CNTACR = 0x40;
572  static const Addr TIMER_CTRL_CNTVOFF_LO = 0x80;
573  static const Addr TIMER_CTRL_CNTVOFF_HI = 0x84;
574 
577 
580 
582  static constexpr size_t MAX_TIMER_FRAMES = 8;
583 
586 
588 };
589 
590 } // namespace gem5
591 
592 #endif // __DEV_ARM_GENERIC_TIMER_HH__
gem5::GenericTimerMem::COUNTER_STATUS_CNTCV_LO
static const Addr COUNTER_STATUS_CNTCV_LO
Definition: generic_timer.hh:557
gem5::SystemCounter::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: generic_timer.cc:233
isa_device.hh
gem5::GenericTimer::CoreTimers::CoreTimers
CoreTimers(GenericTimer &_parent, ArmSystem &system, unsigned cpu, ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS, ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp)
Definition: generic_timer.cc:726
generic_timer_miscregs_types.hh
gem5::ArchTimer::imask
Bitfield< 1 > imask
Definition: generic_timer.hh:186
gem5::GenericTimerMem::counterCtrlWrite
void counterCtrlWrite(Addr addr, size_t size, uint64_t data, bool is_sec)
Definition: generic_timer.cc:1389
gem5::SystemCounter::period
Tick period() const
Returns the counter period.
Definition: generic_timer.hh:133
gem5::GenericTimer::CoreTimers::parent
GenericTimer & parent
Generic Timer parent reference.
Definition: generic_timer.hh:311
gem5::SystemCounter::notifyListeners
void notifyListeners(void) const
Notifies counting speed changes to listeners.
Definition: generic_timer.cc:206
gem5::GenericTimer::CoreTimers::irqPhysNS
const ArmInterruptPin * irqPhysNS
Definition: generic_timer.hh:326
gem5::GenericTimerFrame::timerRange
const AddrRange timerRange
Definition: generic_timer.hh:452
gem5::GenericTimer::CoreTimers::physS
ArchTimerKvm physS
Definition: generic_timer.hh:330
gem5::GenericTimer::CoreTimers::virtEventStreamCallback
void virtEventStreamCallback()
Definition: generic_timer.cc:770
gem5::GenericTimerFrame::hasNonSecureAccess
bool hasNonSecureAccess() const
Indicates if non-secure accesses are allowed to this frame.
Definition: generic_timer.cc:956
gem5::GenericTimerMem::GenericTimerMem
GenericTimerMem(const GenericTimerMemParams &p)
Definition: generic_timer.cc:1248
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArchTimer::_control
ArchTimerCtrl _control
Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
Definition: generic_timer.hh:201
data
const char data[]
Definition: circlebuf.test.cc:48
serialize.hh
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
gem5::SystemCounter::_increment
uint64_t _increment
Value increment in each counter cycle.
Definition: generic_timer.hh:96
gem5::GenericTimerFrame::timerEl0Range
AddrRange timerEl0Range
Definition: generic_timer.hh:453
gem5::GenericTimerFrame::TIMER_CNTV_CVAL_LO
static const Addr TIMER_CNTV_CVAL_LO
Definition: generic_timer.hh:467
gem5::GenericTimer::GenericTimer
GenericTimer(const Params &p)
Definition: generic_timer.cc:405
gem5::GenericTimerFrame::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: generic_timer.cc:914
gem5::GenericTimerFrame::TIMER_CNTP_CVAL_LO
static const Addr TIMER_CNTP_CVAL_LO
Definition: generic_timer.hh:463
gem5::X86ISA::vector
Bitfield< 15, 8 > vector
Definition: intmessage.hh:48
gem5::GenericTimerFrame::EndBitUnion
EndBitUnion(AccessBits) AccessBits accessBits
gem5::GenericTimerFrame::vten
Bitfield< 8 > vten
Definition: generic_timer.hh:496
gem5::GenericTimerMem::TIMER_CTRL_CNTTIDR
static const Addr TIMER_CTRL_CNTTIDR
Definition: generic_timer.hh:570
gem5::GenericTimerMem::hdbg
Bitfield< 1 > hdbg
Definition: generic_timer.hh:536
gem5::ArchTimer::name
std::string name() const
Returns the timer name.
Definition: generic_timer.hh:226
gem5::SystemCounter::freqUpdateCallback
void freqUpdateCallback()
Callback for the frequency update.
Definition: generic_timer.cc:186
gem5::GenericTimerFrame::TIMER_CNTVOFF_LO
static const Addr TIMER_CNTVOFF_LO
Definition: generic_timer.hh:461
gem5::GenericTimerISA::GenericTimerISA
GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
Definition: generic_timer.hh:393
gem5::GenericTimerMem::COUNTER_CTRL_CNTCV_LO
static const Addr COUNTER_CTRL_CNTCV_LO
Definition: generic_timer.hh:546
gem5::GenericTimerFrame::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: generic_timer.cc:980
gem5::GenericTimerISA::parent
GenericTimer & parent
Definition: generic_timer.hh:400
gem5::GenericTimerMem::counterStatusRange
const AddrRange counterStatusRange
Definition: generic_timer.hh:555
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArchTimer::ArchTimer
ArchTimer(const std::string &name, SimObject &parent, SystemCounter &sysctr, ArmInterruptPin *interrupt)
Definition: generic_timer.cc:255
base_gic.hh
gem5::GenericTimerMem::COUNTER_CTRL_CNTFID
static const Addr COUNTER_CTRL_CNTFID
Definition: generic_timer.hh:550
gem5::GenericTimerFrame::system
ArmSystem & system
Definition: generic_timer.hh:505
gem5::GenericTimerFrame::TIMER_CNTP_TVAL
static const Addr TIMER_CNTP_TVAL
Definition: generic_timer.hh:465
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::GenericTimerFrame::rpct
Bitfield< 0 > rpct
Definition: generic_timer.hh:489
gem5::GenericTimerFrame::BitUnion16
BitUnion16(AccessBitsEl0) Bitfield< 9 > pten
gem5::GenericTimerFrame::TIMER_CNTVOFF_HI
static const Addr TIMER_CNTVOFF_HI
Definition: generic_timer.hh:462
gem5::ArchTimer::scheduleEvents
virtual bool scheduleEvents()
Definition: generic_timer.hh:217
gem5::GenericTimerFrame::TIMER_CNTV_CVAL_HI
static const Addr TIMER_CNTV_CVAL_HI
Definition: generic_timer.hh:468
gem5::GenericTimerMem::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: generic_timer.cc:1292
gem5::GenericTimer::CoreTimers::irqPhysS
const ArmInterruptPin * irqPhysS
Definition: generic_timer.hh:325
gem5::ArchTimer::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: generic_timer.cc:377
gem5::GenericTimerMem::counterCtrlRead
uint64_t counterCtrlRead(Addr addr, size_t size, bool is_sec) const
CNTControlBase (System counter control frame)
Definition: generic_timer.cc:1351
gem5::ArchTimer::updateCounter
void updateCounter()
Timer settings or the offset has changed, re-evaluate trigger condition and raise interrupt if necess...
Definition: generic_timer.cc:286
gem5::GenericTimerMem::counterStatusRead
uint64_t counterStatusRead(Addr addr, size_t size) const
CNTReadBase (System counter status frame)
Definition: generic_timer.cc:1463
gem5::ArchTimer::setOffset
void setOffset(uint64_t val)
Definition: generic_timer.cc:350
std::vector< uint32_t >
gem5::SystemCounter::_enabled
bool _enabled
Indicates if the counter is enabled.
Definition: generic_timer.hh:90
gem5::GenericTimerFrame::timerWrite
void timerWrite(Addr addr, size_t size, uint64_t data, bool is_sec, bool to_el0)
Definition: generic_timer.cc:1153
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::GenericTimerMem::fcack
fcack
Definition: generic_timer.hh:541
gem5::GenericTimerFrame::TIMER_CNTPCT_HI
static const Addr TIMER_CNTPCT_HI
Definition: generic_timer.hh:456
gem5::GenericTimer::CoreTimers::physNS
ArchTimerKvm physNS
Definition: generic_timer.hh:331
gem5::ArchTimer::BitUnion32
BitUnion32(ArchTimerCtrl) Bitfield< 0 > enable
Control register.
system.hh
gem5::SystemCounter::registerListener
void registerListener(SystemCounterListener *listener)
Called from System Counter Listeners to register.
Definition: generic_timer.cc:200
gem5::GenericTimer::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: generic_timer.cc:417
gem5::SystemCounter::_period
Tick _period
Cached copy of the counter period (inverse of the frequency).
Definition: generic_timer.hh:102
gem5::GenericTimer::CoreTimers::virtEvStream
EventStream virtEvStream
Definition: generic_timer.hh:357
gem5::GenericTimerFrame::addrRanges
AddrRangeList addrRanges
All MMIO ranges GenericTimerFrame responds to.
Definition: generic_timer.hh:473
gem5::GenericTimerFrame::setVirtOffset
void setVirtOffset(uint64_t new_offset)
Sets the virtual offset for this frame's virtual timer after a write to CNTVOFF.
Definition: generic_timer.cc:932
gem5::GenericTimerFrame::TIMER_CNTVCT_LO
static const Addr TIMER_CNTVCT_LO
Definition: generic_timer.hh:457
gem5::GenericTimerMem::TIMER_CTRL_CNTVOFF_HI
static const Addr TIMER_CTRL_CNTVOFF_HI
Definition: generic_timer.hh:573
gem5::ArchTimer::control
uint32_t control() const
Sets the control register.
Definition: generic_timer.hh:239
gem5::GenericTimerMem::scen
Bitfield< 2 > scen
Definition: generic_timer.hh:535
gem5::GenericTimerMem::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: generic_timer.cc:1298
gem5::GenericTimer::PARAMS
PARAMS(GenericTimer)
gem5::ArchTimerKvm::system
ArmSystem & system
Definition: generic_timer.hh:269
gem5::GenericTimerMem::COUNTER_CTRL_CNTSR
static const Addr COUNTER_CTRL_CNTSR
Definition: generic_timer.hh:545
gem5::GenericTimerFrame::TIMER_CNTPCT_LO
static const Addr TIMER_CNTPCT_LO
Definition: generic_timer.hh:455
gem5::GenericTimerFrame::TIMER_CNTVCT_HI
static const Addr TIMER_CNTVCT_HI
Definition: generic_timer.hh:458
gem5::GenericTimer::CoreTimers::irqHyp
const ArmInterruptPin * irqHyp
Definition: generic_timer.hh:328
gem5::GenericTimerFrame::BitUnion8
BitUnion8(AccessBits) Bitfield< 5 > rwpt
Reports access properties of the CNTBase register frame elements.
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::GenericTimerISA::cpu
unsigned cpu
Definition: generic_timer.hh:401
gem5::ArchTimer::setControl
void setControl(uint32_t val)
Definition: generic_timer.cc:322
gem5::GenericTimerMem::addrRanges
const AddrRangeList addrRanges
All MMIO ranges GenericTimerMem responds to.
Definition: generic_timer.hh:576
gem5::GenericTimerFrame::rvct
Bitfield< 1 > rvct
Definition: generic_timer.hh:488
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::GenericTimer::CoreTimers::EventStream
Definition: generic_timer.hh:338
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::GenericTimerMem::COUNTER_STATUS_CNTCV_HI
static const Addr COUNTER_STATUS_CNTCV_HI
Definition: generic_timer.hh:558
gem5::GenericTimerMem::counterCtrlRange
const AddrRange counterCtrlRange
Definition: generic_timer.hh:531
gem5::GenericTimerMem::systemCounter
SystemCounter & systemCounter
System counter reference.
Definition: generic_timer.hh:579
gem5::GenericTimer::CoreTimers::cnthctl
ArmISA::CNTHCTL cnthctl
Hypervisor control register.
Definition: generic_timer.hh:320
gem5::GenericTimer::CoreTimers::EventStream::eventTargetValue
uint64_t eventTargetValue(uint64_t val) const
Definition: generic_timer.hh:345
gem5::SystemCounter::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: generic_timer.cc:213
gem5::SystemCounter::whenValue
Tick whenValue(uint64_t target_val)
Returns the tick at which a certain counter value is reached.
Definition: generic_timer.cc:156
gem5::SystemCounter::_freq
uint32_t _freq
Counter frequency (as specified by CNTFRQ).
Definition: generic_timer.hh:92
gem5::GenericTimer::getTimers
CoreTimers & getTimers(int cpu_id)
Definition: generic_timer.cc:459
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::GenericTimerFrame::TIMER_CNTEL0ACR
static const Addr TIMER_CNTEL0ACR
Definition: generic_timer.hh:460
gem5::SystemCounterListener
Abstract class for elements whose events depend on the counting speed of the System Counter.
Definition: generic_timer.hh:76
gem5::ArchTimer::offset
uint64_t offset() const
Definition: generic_timer.hh:242
gem5::X86ISA::enable
Bitfield< 11 > enable
Definition: misc.hh:1057
gem5::SystemCounter::activeFreqEntry
size_t activeFreqEntry() const
Returns the currently active frequency table entry.
Definition: generic_timer.hh:131
sim_object.hh
gem5::GenericTimerFrame::GenericTimerFrame
GenericTimerFrame(const GenericTimerFrameParams &p)
Definition: generic_timer.cc:877
gem5::GenericTimerFrame::hasReadableVoff
bool hasReadableVoff() const
Indicates if CNTVOFF is readable for this frame.
Definition: generic_timer.cc:968
gem5::GenericTimer::CoreTimers::EventStream::event
EventFunctionWrapper event
Definition: generic_timer.hh:340
gem5::ArchTimer::_systemCounter
SystemCounter & _systemCounter
Definition: generic_timer.hh:196
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::GenericTimerISA::readMiscReg
RegVal readMiscReg(int misc_reg) override
Read a system register belonging to this device.
Definition: generic_timer.cc:870
EndBitUnion
EndBitUnion(PciCommandRegister) union PCIConfig
Definition: pcireg.h:65
gem5::GenericTimer::CoreTimers::notify
void notify(void) override
Called from the SystemCounter when a change in counting speed occurred Events should be rescheduled p...
Definition: generic_timer.cc:792
gem5::SystemCounter::freq
uint32_t freq() const
Returns the counter frequency.
Definition: generic_timer.hh:123
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::GenericTimerMem::counterStatusWrite
void counterStatusWrite(Addr addr, size_t size, uint64_t data)
Definition: generic_timer.cc:1476
gem5::SystemCounter::_activeFreqEntry
size_t _activeFreqEntry
Currently selected entry in the table, its contents should match _freq.
Definition: generic_timer.hh:100
gem5::GenericTimerMem::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: generic_timer.cc:1325
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PioDevice::sys
System * sys
Definition: io_device.hh:105
gem5::ArchTimer::istatus
Bitfield< 2 > istatus
Definition: generic_timer.hh:187
gem5::GenericTimer::CoreTimers::hyp
ArchTimerKvm hyp
Definition: generic_timer.hh:333
bitunion.hh
gem5::GenericTimerFrame::TIMER_CNTV_CTL
static const Addr TIMER_CNTV_CTL
Definition: generic_timer.hh:470
gem5::GenericTimerFrame::TIMER_CNTP_CTL
static const Addr TIMER_CNTP_CTL
Definition: generic_timer.hh:466
gem5::GenericTimerMem::frames
std::vector< GenericTimerFrame * > frames
Timer frame references.
Definition: generic_timer.hh:585
gem5::GenericTimer
Definition: generic_timer.hh:288
gem5::GenericTimer::CoreTimers::threadContext
ThreadContext * threadContext
Thread (HW) context associated to this PE implementation.
Definition: generic_timer.hh:323
gem5::GenericTimerFrame::hasEl0View
bool hasEl0View() const
Indicates if this frame implements a second EL0 view.
Definition: generic_timer.cc:938
gem5::ArchTimer::counterLimitReached
void counterLimitReached()
Called when the upcounter reaches the programmed value.
Definition: generic_timer.cc:268
gem5::ArchTimer::whenValue
Tick whenValue(uint64_t target_val)
Definition: generic_timer.hh:247
gem5::GenericTimerFrame::rvoff
Bitfield< 3 > rvoff
Definition: generic_timer.hh:486
gem5::SystemCounter::setValue
void setValue(uint64_t new_value)
Sets the value explicitly from writes to CNTCR.CNTCV.
Definition: generic_timer.cc:128
gem5::GenericTimerMem::en
Bitfield< 0 > en
Definition: generic_timer.hh:537
gem5::SystemCounter::increment
uint64_t increment() const
Returns the value increment.
Definition: generic_timer.hh:127
gem5::GenericTimerMem::validateAccessPerm
static bool validateAccessPerm(ArmSystem &sys, bool is_sec)
Validates an MMIO access permissions.
Definition: generic_timer.cc:1286
gem5::ArchTimer::_parent
EndBitUnion(ArchTimerCtrl) const std SimObject & _parent
Name of this timer.
Definition: generic_timer.hh:188
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::GenericTimer::CoreTimers::physEvStream
EventStream physEvStream
Definition: generic_timer.hh:356
gem5::ArchTimerKvm
Definition: generic_timer.hh:266
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::GenericTimer::readMiscReg
RegVal readMiscReg(int misc_reg, unsigned cpu)
Definition: generic_timer.cc:641
gem5::SystemCounter::updateTick
void updateTick(void)
Updates the update tick, normalizes to the lower cycle start tick.
Definition: generic_timer.cc:162
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
gem5::ArmISA::c
Bitfield< 29 > c
Definition: misc_types.hh:53
gem5::GenericTimer::CoreTimers::EventStream::transitionBit
uint8_t transitionBit
Definition: generic_timer.hh:342
gem5::ArchTimer::_counterLimitReachedEvent
EventFunctionWrapper _counterLimitReachedEvent
Definition: generic_timer.hh:215
gem5::GenericTimerFrame::TIMER_CNTV_TVAL
static const Addr TIMER_CNTV_TVAL
Definition: generic_timer.hh:469
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GenericTimerMem::validateFrameRange
static void validateFrameRange(const AddrRange &range)
Validates a Generic Timer register frame address range.
Definition: generic_timer.cc:1277
gem5::GenericTimer::system
ArmSystem & system
ARM system containing this timer.
Definition: generic_timer.hh:384
gem5::GenericTimerFrame::nonSecureAccess
bool nonSecureAccess
Reports whether non-secure accesses are allowed to this frame.
Definition: generic_timer.hh:503
gem5::GenericTimerMem::timerCtrlRange
const AddrRange timerCtrlRange
Definition: generic_timer.hh:563
addr_range.hh
gem5::GenericTimerFrame::vcten
Bitfield< 1 > vcten
Definition: generic_timer.hh:497
gem5::GenericTimerFrame::setAccessBits
void setAccessBits(uint8_t data)
Updates the access bits after a write to CNTCTLBase.CNTACR.
Definition: generic_timer.cc:950
gem5::ArchTimer::_offset
uint64_t _offset
Offset relative to the physical timer (CNTVOFF)
Definition: generic_timer.hh:205
gem5::GenericTimerMem::COUNTER_CTRL_CNTSCR
static const Addr COUNTER_CTRL_CNTSCR
Definition: generic_timer.hh:548
gem5::ArchTimer::setTimerValue
void setTimerValue(uint32_t val)
Sets the TimerValue view of the timer.
Definition: generic_timer.cc:316
gem5::GenericTimerMem::TIMER_CTRL_CNTNSAR
static const Addr TIMER_CTRL_CNTNSAR
Definition: generic_timer.hh:569
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::SystemCounter::freqTable
std::vector< uint32_t > & freqTable()
Returns a reference to the frequency modes table.
Definition: generic_timer.hh:129
gem5::GenericTimerMem::cnttidr
uint32_t cnttidr
ID register for reporting features of implemented timer frames.
Definition: generic_timer.hh:566
gem5::GenericTimerFrame::timerRead
uint64_t timerRead(Addr addr, size_t size, bool is_sec, bool to_el0) const
CNTBase/CNTEL0Base (Memory-mapped timer frame)
Definition: generic_timer.cc:1041
gem5::GenericTimer::CoreTimers::virt
ArchTimerKvm virt
Definition: generic_timer.hh:332
gem5::GenericTimerFrame::setNonSecureAccess
void setNonSecureAccess()
Allows non-secure accesses after an enabling write to CNTCTLBase.CNTNSAR.
Definition: generic_timer.cc:962
gem5::SystemCounter::_nextFreqEntry
size_t _nextFreqEntry
Definition: generic_timer.hh:164
gem5::ArmSystem
Definition: system.hh:62
gem5::SystemCounter::_listeners
std::vector< SystemCounterListener * > _listeners
Listeners to changes in counting speed.
Definition: generic_timer.hh:108
gem5::GenericTimerMem::timerCtrlWrite
void timerCtrlWrite(Addr addr, size_t size, uint64_t data, bool is_sec)
Definition: generic_timer.cc:1534
gem5::ArchTimer::value
uint64_t value() const
Returns the value of the counter which this timer relies on.
Definition: generic_timer.cc:357
gem5::GenericTimerFrame::rfrq
Bitfield< 2 > rfrq
Definition: generic_timer.hh:487
gem5::GenericTimer::CoreTimers::cntkctl
ArmISA::CNTKCTL cntkctl
Kernel control register.
Definition: generic_timer.hh:317
gem5::GenericTimerFrame::physTimer
ArchTimer physTimer
Physical and virtual timers.
Definition: generic_timer.hh:479
gem5::SystemCounter::_freqTable
std::vector< uint32_t > _freqTable
Frequency modes table with all possible frequencies for the counter.
Definition: generic_timer.hh:98
gem5::SystemCounter::value
uint64_t value()
Updates and returns the counter value.
Definition: generic_timer.cc:109
gem5::SystemCounter::updateValue
void updateValue(void)
Updates the counter value.
Definition: generic_timer.cc:117
gem5::SystemCounter::_value
uint64_t _value
Counter value (as specified in CNTCV).
Definition: generic_timer.hh:94
gem5::SystemCounter::MAX_FREQ_ENTRIES
static constexpr size_t MAX_FREQ_ENTRIES
Maximum architectural number of frequency table entries.
Definition: generic_timer.hh:111
gem5::SystemCounter::SystemCounter
SystemCounter(const SystemCounterParams &p)
Definition: generic_timer.cc:62
gem5::GenericTimerMem::TIMER_CTRL_CNTFRQ
static const Addr TIMER_CTRL_CNTFRQ
Definition: generic_timer.hh:568
gem5::GenericTimerFrame::systemCounter
SystemCounter & systemCounter
System counter reference.
Definition: generic_timer.hh:476
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
types.hh
gem5::GenericTimerMem::COUNTER_CTRL_CNTID
static const Addr COUNTER_CTRL_CNTID
Definition: generic_timer.hh:549
gem5::GenericTimer::setMiscReg
void setMiscReg(int misc_reg, unsigned cpu, RegVal val)
Definition: generic_timer.cc:515
gem5::ArchTimer::_interrupt
ArmInterruptPin *const _interrupt
Definition: generic_timer.hh:198
gem5::GenericTimer::systemCounter
SystemCounter & systemCounter
System counter reference.
Definition: generic_timer.hh:377
gem5::SystemCounter::validateCounterRef
static void validateCounterRef(SystemCounter *sys_cnt)
Validates a System Counter reference.
Definition: generic_timer.cc:86
gem5::ArchTimerKvm::ArchTimerKvm
ArchTimerKvm(const std::string &name, ArmSystem &system, SimObject &parent, SystemCounter &sysctr, ArmInterruptPin *interrupt)
Definition: generic_timer.hh:272
gem5::GenericTimerMem::system
ArmSystem & system
Definition: generic_timer.hh:587
gem5::SystemCounter::enabled
bool enabled() const
Indicates if the counter is enabled.
Definition: generic_timer.hh:121
gem5::GenericTimerFrame::TIMER_CNTFRQ
static const Addr TIMER_CNTFRQ
Definition: generic_timer.hh:459
gem5::GenericTimerFrame::virtTimer
ArchTimer virtTimer
Definition: generic_timer.hh:480
gem5::GenericTimer::CoreTimers::cntfrq
uint32_t cntfrq
System counter frequency as visible from this core.
Definition: generic_timer.hh:314
gem5::GenericTimerFrame::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: generic_timer.cc:974
gem5::Drainable
Interface for objects that might require draining before checkpointing.
Definition: drain.hh:234
gem5::SystemCounter::disable
void disable()
Disables the counter after a CNTCR.EN == 0.
Definition: generic_timer.cc:101
gem5::SystemCounter::_freqUpdateEvent
EventFunctionWrapper _freqUpdateEvent
Frequency update event handling.
Definition: generic_timer.hh:163
gem5::GenericTimer::CoreTimers::irqVirt
const ArmInterruptPin * irqVirt
Definition: generic_timer.hh:327
gem5::SystemCounter::freqUpdateSchedule
void freqUpdateSchedule(size_t new_freq_entry)
Schedules a counter frequency update after a CNTCR.FCREQ == 1 This complies with frequency transition...
Definition: generic_timer.cc:168
gem5::GenericTimerMem
Definition: generic_timer.hh:508
gem5::System::validKvmEnvironment
bool validKvmEnvironment() const
Verify gem5 configuration will support KVM emulation.
Definition: system.cc:337
gem5::GenericTimer::CoreTimers::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: generic_timer.cc:799
gem5::GenericTimerMem::fcreq
fcreq
Definition: generic_timer.hh:534
gem5::GenericTimer::CoreTimers::eventStreamCallback
void eventStreamCallback() const
Definition: generic_timer.cc:777
gem5::GenericTimerMem::EndBitUnion
EndBitUnion(CNTCR) BitUnion32(CNTSR) Bitfield< 31
gem5::ArchTimer::timerValue
uint32_t timerValue() const
Returns the TimerValue view of the timer.
Definition: generic_timer.hh:234
gem5::ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:200
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::GenericTimerMem::MAX_TIMER_FRAMES
static constexpr size_t MAX_TIMER_FRAMES
Maximum architectural number of memory-mapped timer frames.
Definition: generic_timer.hh:582
gem5::ArchTimerKvm::scheduleEvents
bool scheduleEvents() override
Definition: generic_timer.hh:283
drain.hh
gem5::GenericTimerFrame::rwvt
Bitfield< 4 > rwvt
Definition: generic_timer.hh:485
gem5::GenericTimerFrame::TIMER_CNTP_CVAL_HI
static const Addr TIMER_CNTP_CVAL_HI
Definition: generic_timer.hh:464
gem5::GenericTimerMem::TIMER_CTRL_CNTACR
static const Addr TIMER_CTRL_CNTACR
Definition: generic_timer.hh:571
gem5::ArchTimer
Per-CPU architected timer.
Definition: generic_timer.hh:179
gem5::GenericTimer::CoreTimers::schedNextEvent
void schedNextEvent(EventStream &ev_stream, ArchTimer &timer)
Definition: generic_timer.cc:784
gem5::ArchTimer::_counterLimit
uint64_t _counterLimit
Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
Definition: generic_timer.hh:203
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
std::list< AddrRange >
gem5::GenericTimer::CoreTimers::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: generic_timer.cc:830
gem5::ArchTimer::notify
void notify(void) override
Called from the SystemCounter when a change in counting speed occurred Events should be rescheduled p...
Definition: generic_timer.cc:363
gem5::GenericTimerMem::TIMER_CTRL_CNTVOFF_LO
static const Addr TIMER_CTRL_CNTVOFF_LO
Definition: generic_timer.hh:572
gem5::GenericTimerFrame::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: generic_timer.cc:1011
gem5::SystemCounter
Global system counter.
Definition: generic_timer.hh:86
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SystemCounterListener::notify
virtual void notify(void)=0
Called from the SystemCounter when a change in counting speed occurred Events should be rescheduled p...
gem5::GenericTimerMem::BitUnion32
BitUnion32(CNTCR) Bitfield< 17
gem5::GenericTimerISA
Definition: generic_timer.hh:390
gem5::GenericTimerFrame
Definition: generic_timer.hh:404
gem5::ArchTimer::setCompareValue
void setCompareValue(uint64_t val)
Sets the CompareValue view of the timer.
Definition: generic_timer.cc:309
gem5::GenericTimerFrame::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: generic_timer.cc:902
gem5::ArchTimer::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: generic_timer.cc:400
gem5::GenericTimerISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Write to a system register belonging to this device.
Definition: generic_timer.cc:863
gem5::ArchTimer::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: generic_timer.cc:369
gem5::GenericTimer::timers
std::vector< std::unique_ptr< CoreTimers > > timers
Per-CPU physical architected timers.
Definition: generic_timer.hh:380
gem5::GenericTimer::handleStream
void handleStream(CoreTimers::EventStream *ev_stream, ArchTimer *timer, RegVal old_cnt_ctl, RegVal cnt_ctl)
Definition: generic_timer.cc:489
gem5::GenericTimerFrame::hasVirtualTimer
bool hasVirtualTimer() const
Indicates if this frame implements a virtual timer.
gem5::GenericTimer::createTimers
void createTimers(unsigned cpus)
Definition: generic_timer.cc:468
gem5::GenericTimerMem::COUNTER_CTRL_CNTCV_HI
static const Addr COUNTER_CTRL_CNTCV_HI
Definition: generic_timer.hh:547
gem5::GenericTimerFrame::pcten
Bitfield< 0 > pcten
Definition: generic_timer.hh:498
gem5::GenericTimer::CoreTimers::physEventStreamCallback
void physEventStreamCallback()
Definition: generic_timer.cc:763
gem5::ArchTimer::compareValue
uint64_t compareValue() const
Returns the CompareValue view of the timer.
Definition: generic_timer.hh:229
gem5::GenericTimer::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: generic_timer.cc:428
gem5::SystemCounter::enable
void enable()
Enables the counter after a CNTCR.EN == 1.
Definition: generic_timer.cc:93
gem5::GenericTimer::CoreTimers::EventStream::transitionTo
uint8_t transitionTo
Definition: generic_timer.hh:341
gem5::GenericTimerMem::timerCtrlRead
uint64_t timerCtrlRead(Addr addr, size_t size, bool is_sec) const
CNTCTLBase (Memory-mapped timer global control frame)
Definition: generic_timer.cc:1490
gem5::GenericTimerFrame::getAccessBits
uint8_t getAccessBits() const
Returns the access bits for this frame.
Definition: generic_timer.cc:944
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::SystemCounter::_updateTick
Tick _updateTick
Counter cycle start Tick when the counter status affecting its value has been updated.
Definition: generic_timer.hh:105
gem5::GenericTimer::CoreTimers
Definition: generic_timer.hh:303
gem5::GenericTimerFrame::getVirtOffset
uint64_t getVirtOffset() const
Returns the virtual offset for this frame if a virtual timer is implemented.
Definition: generic_timer.cc:926
gem5::ArchTimer::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: generic_timer.cc:391
eventq.hh

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