gem5  v21.1.0.2
intelmp.hh
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37 
38 #ifndef __ARCH_X86_BIOS_INTELMP_HH__
39 #define __ARCH_X86_BIOS_INTELMP_HH__
40 
41 #include <string>
42 #include <vector>
43 
44 #include "base/bitfield.hh"
45 #include "base/compiler.hh"
46 #include "enums/X86IntelMPAddressType.hh"
47 #include "enums/X86IntelMPInterruptType.hh"
48 #include "enums/X86IntelMPPolarity.hh"
49 #include "enums/X86IntelMPRangeList.hh"
50 #include "enums/X86IntelMPTriggerMode.hh"
51 #include "sim/sim_object.hh"
52 
53 namespace gem5
54 {
55 
56 class PortProxy;
57 
58 // Config entry types
59 struct X86IntelMPBaseConfigEntryParams;
60 struct X86IntelMPExtConfigEntryParams;
61 
62 // General table structures
63 struct X86IntelMPConfigTableParams;
64 struct X86IntelMPFloatingPointerParams;
65 
66 // Base entry types
67 struct X86IntelMPBusParams;
68 struct X86IntelMPIOAPICParams;
69 struct X86IntelMPIOIntAssignmentParams;
70 struct X86IntelMPLocalIntAssignmentParams;
71 struct X86IntelMPProcessorParams;
72 
73 // Extended entry types
74 struct X86IntelMPAddrSpaceMappingParams;
75 struct X86IntelMPBusHierarchyParams;
76 struct X86IntelMPCompatAddrSpaceModParams;
77 
78 template<class T>
79 uint8_t writeOutField(PortProxy& proxy, Addr addr, T val);
80 
81 uint8_t writeOutString(PortProxy& proxy, Addr addr, std::string str,
82  int length);
83 
84 namespace X86ISA
85 {
86 
87 GEM5_DEPRECATED_NAMESPACE(IntelMP, intelmp);
88 namespace intelmp
89 {
90 
91 class FloatingPointer : public SimObject
92 {
93  protected:
94  typedef X86IntelMPFloatingPointerParams Params;
95 
96  uint32_t tableAddr;
97  uint8_t specRev;
98  uint8_t defaultConfig;
100 
101  static const char signature[];
102 
103  public:
104 
105  Addr writeOut(PortProxy& proxy, Addr addr);
106 
108  {
109  return tableAddr;
110  }
111 
113  {
114  tableAddr = addr;
115  }
116 
117  FloatingPointer(const Params &p);
118 };
119 
121 {
122  protected:
123  typedef X86IntelMPBaseConfigEntryParams Params;
124 
125  uint8_t type;
126 
127  public:
128 
129  virtual Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
130 
131  BaseConfigEntry(const Params &p, uint8_t _type);
132 };
133 
134 class ExtConfigEntry : public SimObject
135 {
136  protected:
137  typedef X86IntelMPExtConfigEntryParams Params;
138 
139  uint8_t type;
140  uint8_t length;
141 
142  public:
143 
144  virtual Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
145 
146  ExtConfigEntry(const Params &p, uint8_t _type, uint8_t _length);
147 };
148 
149 class ConfigTable : public SimObject
150 {
151  protected:
152  typedef X86IntelMPConfigTableParams Params;
153 
154  static const char signature[];
155 
156  uint8_t specRev;
157  std::string oemID;
158  std::string productID;
159  uint32_t oemTableAddr;
160  uint16_t oemTableSize;
161  uint32_t localApic;
162 
165 
166  public:
167  Addr writeOut(PortProxy& proxy, Addr addr);
168 
169  ConfigTable(const Params &p);
170 };
171 
173 {
174  protected:
175  typedef X86IntelMPProcessorParams Params;
176 
177  uint8_t localApicID;
179  uint8_t cpuFlags;
180  uint32_t cpuSignature;
181  uint32_t featureFlags;
182 
183  public:
184  Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
185 
186  Processor(const Params &p);
187 };
188 
189 class Bus : public BaseConfigEntry
190 {
191  protected:
192  typedef X86IntelMPBusParams Params;
193 
194  uint8_t busID;
195  std::string busType;
196 
197  public:
198  Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
199 
200  Bus(const Params &p);
201 };
202 
203 class IOAPIC : public BaseConfigEntry
204 {
205  protected:
206  typedef X86IntelMPIOAPICParams Params;
207 
208  uint8_t id;
209  uint8_t version;
210  uint8_t flags;
211  uint32_t address;
212 
213  public:
214  Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
215 
216  IOAPIC(const Params &p);
217 };
218 
220 {
221  protected:
222  uint8_t interruptType;
223 
224  uint16_t flags;
225 
226  uint8_t sourceBusID;
227  uint8_t sourceBusIRQ;
228 
229  uint8_t destApicID;
230  uint8_t destApicIntIn;
231 
232  public:
233  Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
234 
235  IntAssignment(const X86IntelMPBaseConfigEntryParams &p,
236  enums::X86IntelMPInterruptType _interruptType,
237  enums::X86IntelMPPolarity polarity,
238  enums::X86IntelMPTriggerMode trigger,
239  uint8_t _type,
240  uint8_t _sourceBusID, uint8_t _sourceBusIRQ,
241  uint8_t _destApicID, uint8_t _destApicIntIn) :
242  BaseConfigEntry(p, _type),
243  interruptType(_interruptType), flags(0),
244  sourceBusID(_sourceBusID), sourceBusIRQ(_sourceBusIRQ),
245  destApicID(_destApicID), destApicIntIn(_destApicIntIn)
246  {
247  replaceBits(flags, 1, 0, polarity);
248  replaceBits(flags, 3, 2, trigger);
249  }
250 };
251 
253 {
254  protected:
255  typedef X86IntelMPIOIntAssignmentParams Params;
256 
257  public:
258  IOIntAssignment(const Params &p);
259 };
260 
262 {
263  protected:
264  typedef X86IntelMPLocalIntAssignmentParams Params;
265 
266  public:
267  LocalIntAssignment(const Params &p);
268 };
269 
271 {
272  protected:
273  typedef X86IntelMPAddrSpaceMappingParams Params;
274 
275  uint8_t busID;
276  uint8_t addrType;
277  uint64_t addr;
278  uint64_t addrLength;
279 
280  public:
281  Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
282 
283  AddrSpaceMapping(const Params &p);
284 };
285 
287 {
288  protected:
289  typedef X86IntelMPBusHierarchyParams Params;
290 
291  uint8_t busID;
292  uint8_t info;
293  uint8_t parentBus;
294 
295  public:
296  Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
297 
298  BusHierarchy(const Params &p);
299 };
300 
302 {
303  protected:
304  typedef X86IntelMPCompatAddrSpaceModParams Params;
305 
306  uint8_t busID;
307  uint8_t mod;
308  uint32_t rangeList;
309 
310  public:
311  Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
312 
313  CompatAddrSpaceMod(const Params &p);
314 };
315 
316 } // namespace intelmp
317 } // namespace X86ISA
318 } // namespace gem5
319 
320 #endif
gem5::X86ISA::intelmp::FloatingPointer
Definition: intelmp.hh:91
gem5::X86ISA::intelmp::AddrSpaceMapping
Definition: intelmp.hh:270
gem5::X86ISA::intelmp::IntAssignment::sourceBusIRQ
uint8_t sourceBusIRQ
Definition: intelmp.hh:227
gem5::X86ISA::intelmp::ConfigTable::specRev
uint8_t specRev
Definition: intelmp.hh:156
gem5::X86ISA::intelmp::ConfigTable::oemTableSize
uint16_t oemTableSize
Definition: intelmp.hh:160
gem5::X86ISA::intelmp::BusHierarchy::Params
X86IntelMPBusHierarchyParams Params
Definition: intelmp.hh:289
gem5::X86ISA::intelmp::AddrSpaceMapping::writeOut
Addr writeOut(PortProxy &proxy, Addr addr, uint8_t &checkSum)
Definition: intelmp.cc:341
gem5::X86ISA::intelmp::Bus::busID
uint8_t busID
Definition: intelmp.hh:194
gem5::X86ISA::intelmp::Processor::cpuSignature
uint32_t cpuSignature
Definition: intelmp.hh:180
gem5::X86ISA::intelmp::ConfigTable::localApic
uint32_t localApic
Definition: intelmp.hh:161
gem5::X86ISA::intelmp::CompatAddrSpaceMod::writeOut
Addr writeOut(PortProxy &proxy, Addr addr, uint8_t &checkSum)
Definition: intelmp.cc:382
gem5::X86ISA::intelmp::IOAPIC::IOAPIC
IOAPIC(const Params &p)
Definition: intelmp.cc:307
gem5::X86ISA::intelmp::IOAPIC::writeOut
Addr writeOut(PortProxy &proxy, Addr addr, uint8_t &checkSum)
Definition: intelmp.cc:296
gem5::X86ISA::intelmp::BusHierarchy::info
uint8_t info
Definition: intelmp.hh:292
gem5::X86ISA::intelmp::CompatAddrSpaceMod::CompatAddrSpaceMod
CompatAddrSpaceMod(const Params &p)
Definition: intelmp.cc:392
gem5::X86ISA::intelmp::AddrSpaceMapping::AddrSpaceMapping
AddrSpaceMapping(const Params &p)
Definition: intelmp.cc:352
gem5::X86ISA::intelmp::IOAPIC::flags
uint8_t flags
Definition: intelmp.hh:210
gem5::X86ISA::intelmp::ExtConfigEntry::writeOut
virtual Addr writeOut(PortProxy &proxy, Addr addr, uint8_t &checkSum)
Definition: intelmp.cc:168
gem5::X86ISA::intelmp::IntAssignment::sourceBusID
uint8_t sourceBusID
Definition: intelmp.hh:226
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::X86ISA::intelmp::LocalIntAssignment::Params
X86IntelMPLocalIntAssignmentParams Params
Definition: intelmp.hh:264
gem5::X86ISA::intelmp::IntAssignment::destApicID
uint8_t destApicID
Definition: intelmp.hh:229
gem5::writeOutField
uint8_t writeOutField(PortProxy &proxy, Addr addr, T val)
Definition: intelmp.cc:72
gem5::X86ISA::intelmp::IOIntAssignment::Params
X86IntelMPIOIntAssignmentParams Params
Definition: intelmp.hh:255
gem5::X86ISA::intelmp::FloatingPointer::specRev
uint8_t specRev
Definition: intelmp.hh:97
gem5::X86ISA::intelmp::BusHierarchy
Definition: intelmp.hh:286
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::X86ISA::intelmp::BaseConfigEntry
Definition: intelmp.hh:120
gem5::X86ISA::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(IntelMP, intelmp)
gem5::X86ISA::intelmp::AddrSpaceMapping::addrLength
uint64_t addrLength
Definition: intelmp.hh:278
gem5::X86ISA::intelmp::IntAssignment::interruptType
uint8_t interruptType
Definition: intelmp.hh:222
gem5::X86ISA::intelmp::Processor::cpuFlags
uint8_t cpuFlags
Definition: intelmp.hh:179
std::vector
STL vector class.
Definition: stl.hh:37
gem5::X86ISA::intelmp::Processor::featureFlags
uint32_t featureFlags
Definition: intelmp.hh:181
gem5::X86ISA::intelmp::LocalIntAssignment
Definition: intelmp.hh:261
gem5::X86ISA::intelmp::ExtConfigEntry::ExtConfigEntry
ExtConfigEntry(const Params &p, uint8_t _type, uint8_t _length)
Definition: intelmp.cc:178
gem5::X86ISA::intelmp::ConfigTable::writeOut
Addr writeOut(PortProxy &proxy, Addr addr)
Definition: intelmp.cc:186
gem5::X86ISA::intelmp::ConfigTable
Definition: intelmp.hh:149
gem5::X86ISA::intelmp::ExtConfigEntry::length
uint8_t length
Definition: intelmp.hh:140
gem5::X86ISA::intelmp::ConfigTable::oemTableAddr
uint32_t oemTableAddr
Definition: intelmp.hh:159
gem5::X86ISA::intelmp::BaseConfigEntry::Params
X86IntelMPBaseConfigEntryParams Params
Definition: intelmp.hh:123
gem5::X86ISA::intelmp::FloatingPointer::Params
X86IntelMPFloatingPointerParams Params
Definition: intelmp.hh:94
gem5::X86ISA::intelmp::ConfigTable::extEntries
std::vector< ExtConfigEntry * > extEntries
Definition: intelmp.hh:164
gem5::X86ISA::intelmp::Processor::writeOut
Addr writeOut(PortProxy &proxy, Addr addr, uint8_t &checkSum)
Definition: intelmp.cc:251
gem5::X86ISA::intelmp::FloatingPointer::tableAddr
uint32_t tableAddr
Definition: intelmp.hh:96
gem5::X86ISA::intelmp::BusHierarchy::parentBus
uint8_t parentBus
Definition: intelmp.hh:293
gem5::X86ISA::intelmp::IntAssignment::destApicIntIn
uint8_t destApicIntIn
Definition: intelmp.hh:230
gem5::X86ISA::intelmp::FloatingPointer::defaultConfig
uint8_t defaultConfig
Definition: intelmp.hh:98
bitfield.hh
sim_object.hh
gem5::X86ISA::intelmp::ExtConfigEntry::type
uint8_t type
Definition: intelmp.hh:139
gem5::X86ISA::intelmp::BusHierarchy::busID
uint8_t busID
Definition: intelmp.hh:291
gem5::X86ISA::intelmp::ConfigTable::signature
static const char signature[]
Definition: intelmp.hh:154
gem5::X86ISA::intelmp::AddrSpaceMapping::addr
uint64_t addr
Definition: intelmp.hh:277
gem5::X86ISA::intelmp::FloatingPointer::setTableAddr
void setTableAddr(Addr addr)
Definition: intelmp.hh:112
gem5::X86ISA::intelmp::CompatAddrSpaceMod::busID
uint8_t busID
Definition: intelmp.hh:306
gem5::X86ISA::intelmp::Processor::Processor
Processor(const Params &p)
Definition: intelmp.cc:267
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::X86ISA::intelmp::ConfigTable::productID
std::string productID
Definition: intelmp.hh:158
gem5::X86ISA::intelmp::BusHierarchy::BusHierarchy
BusHierarchy(const Params &p)
Definition: intelmp.cc:373
gem5::X86ISA::intelmp::FloatingPointer::signature
static const char signature[]
Definition: intelmp.hh:101
gem5::X86ISA::intelmp::BaseConfigEntry::writeOut
virtual Addr writeOut(PortProxy &proxy, Addr addr, uint8_t &checkSum)
Definition: intelmp.cc:154
gem5::X86ISA::intelmp::ExtConfigEntry::Params
X86IntelMPExtConfigEntryParams Params
Definition: intelmp.hh:137
gem5::X86ISA::intelmp::ConfigTable::ConfigTable
ConfigTable(const Params &p)
Definition: intelmp.cc:243
gem5::X86ISA::intelmp::BaseConfigEntry::type
uint8_t type
Definition: intelmp.hh:125
gem5::X86ISA::intelmp::IOIntAssignment::IOIntAssignment
IOIntAssignment(const Params &p)
Definition: intelmp.cc:328
compiler.hh
gem5::X86ISA::intelmp::ExtConfigEntry
Definition: intelmp.hh:134
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::X86ISA::intelmp::Bus::writeOut
Addr writeOut(PortProxy &proxy, Addr addr, uint8_t &checkSum)
Definition: intelmp.cc:282
gem5::X86ISA::intelmp::ConfigTable::Params
X86IntelMPConfigTableParams Params
Definition: intelmp.hh:152
gem5::X86ISA::intelmp::BaseConfigEntry::BaseConfigEntry
BaseConfigEntry(const Params &p, uint8_t _type)
Definition: intelmp.cc:162
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::intelmp::Processor::Params
X86IntelMPProcessorParams Params
Definition: intelmp.hh:175
gem5::X86ISA::intelmp::CompatAddrSpaceMod::rangeList
uint32_t rangeList
Definition: intelmp.hh:308
gem5::X86ISA::intelmp::Bus::Bus
Bus(const Params &p)
Definition: intelmp.cc:291
gem5::X86ISA::intelmp::IOAPIC::address
uint32_t address
Definition: intelmp.hh:211
gem5::X86ISA::intelmp::CompatAddrSpaceMod
Definition: intelmp.hh:301
gem5::X86ISA::intelmp::Processor::localApicVersion
uint8_t localApicVersion
Definition: intelmp.hh:178
gem5::X86ISA::intelmp::ConfigTable::oemID
std::string oemID
Definition: intelmp.hh:157
gem5::X86ISA::intelmp::IOAPIC::Params
X86IntelMPIOAPICParams Params
Definition: intelmp.hh:206
gem5::X86ISA::intelmp::AddrSpaceMapping::addrType
uint8_t addrType
Definition: intelmp.hh:276
gem5::X86ISA::intelmp::Processor::localApicID
uint8_t localApicID
Definition: intelmp.hh:177
gem5::X86ISA::intelmp::CompatAddrSpaceMod::Params
X86IntelMPCompatAddrSpaceModParams Params
Definition: intelmp.hh:304
gem5::X86ISA::intelmp::BusHierarchy::writeOut
Addr writeOut(PortProxy &proxy, Addr addr, uint8_t &checkSum)
Definition: intelmp.cc:359
gem5::X86ISA::intelmp::IOIntAssignment
Definition: intelmp.hh:252
gem5::writeOutString
uint8_t writeOutString(PortProxy &proxy, Addr addr, std::string str, int length)
Definition: intelmp.cc:86
gem5::X86ISA::intelmp::LocalIntAssignment::LocalIntAssignment
LocalIntAssignment(const Params &p)
Definition: intelmp.cc:334
gem5::X86ISA::intelmp::IntAssignment
Definition: intelmp.hh:219
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::X86ISA::intelmp::IOAPIC::id
uint8_t id
Definition: intelmp.hh:208
gem5::X86ISA::intelmp::AddrSpaceMapping::busID
uint8_t busID
Definition: intelmp.hh:275
gem5::X86ISA::intelmp::FloatingPointer::imcrPresent
bool imcrPresent
Definition: intelmp.hh:99
gem5::X86ISA::intelmp::FloatingPointer::getTableAddr
Addr getTableAddr()
Definition: intelmp.hh:107
gem5::X86ISA::intelmp::IntAssignment::IntAssignment
IntAssignment(const X86IntelMPBaseConfigEntryParams &p, enums::X86IntelMPInterruptType _interruptType, enums::X86IntelMPPolarity polarity, enums::X86IntelMPTriggerMode trigger, uint8_t _type, uint8_t _sourceBusID, uint8_t _sourceBusIRQ, uint8_t _destApicID, uint8_t _destApicIntIn)
Definition: intelmp.hh:235
gem5::X86ISA::intelmp::IOAPIC
Definition: intelmp.hh:203
gem5::X86ISA::intelmp::Processor
Definition: intelmp.hh:172
gem5::X86ISA::intelmp::FloatingPointer::FloatingPointer
FloatingPointer(const Params &p)
Definition: intelmp.cc:148
gem5::X86ISA::intelmp::IntAssignment::writeOut
Addr writeOut(PortProxy &proxy, Addr addr, uint8_t &checkSum)
Definition: intelmp.cc:315
gem5::X86ISA::intelmp::Bus::busType
std::string busType
Definition: intelmp.hh:195
gem5::X86ISA::intelmp::Bus
Definition: intelmp.hh:189
gem5::X86ISA::intelmp::ConfigTable::baseEntries
std::vector< BaseConfigEntry * > baseEntries
Definition: intelmp.hh:163
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::intelmp::AddrSpaceMapping::Params
X86IntelMPAddrSpaceMappingParams Params
Definition: intelmp.hh:273
gem5::X86ISA::intelmp::IntAssignment::flags
uint16_t flags
Definition: intelmp.hh:224
gem5::X86ISA::intelmp::Bus::Params
X86IntelMPBusParams Params
Definition: intelmp.hh:192
gem5::X86ISA::intelmp::IOAPIC::version
uint8_t version
Definition: intelmp.hh:209
gem5::X86ISA::trigger
Bitfield< 21 > trigger
Definition: intmessage.hh:52
gem5::X86ISA::intelmp::FloatingPointer::writeOut
Addr writeOut(PortProxy &proxy, Addr addr)
Definition: intelmp.cc:109
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::X86ISA::intelmp::CompatAddrSpaceMod::mod
uint8_t mod
Definition: intelmp.hh:307

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