gem5  v22.0.0.1
decoder.hh
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28 
29 #ifndef __ARCH_MIPS_DECODER_HH__
30 #define __ARCH_MIPS_DECODER_HH__
31 
33 #include "arch/generic/decoder.hh"
34 #include "arch/mips/types.hh"
35 #include "base/logging.hh"
36 #include "base/types.hh"
37 #include "cpu/static_inst.hh"
38 #include "debug/Decode.hh"
39 #include "params/MipsDecoder.hh"
40 
41 namespace gem5
42 {
43 
44 namespace MipsISA
45 {
46 
47 class ISA;
48 class Decoder : public InstDecoder
49 {
50  protected:
51  //The extended machine instruction being generated
53  uint32_t machInst;
54 
55  public:
56  Decoder(const MipsDecoderParams &p) : InstDecoder(p, &machInst)
57  {}
58 
59  //Use this to give data to the decoder. This should be used
60  //when there is control flow.
61  void
62  moreBytes(const PCStateBase &pc, Addr fetchPC) override
63  {
64  emi = letoh(machInst);
65  instDone = true;
66  }
67 
68  protected:
72 
74 
80  {
81  StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
82  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
83  si->getName(), mach_inst);
84  return si;
85  }
86 
87  public:
89  decode(PCStateBase &next_pc) override
90  {
91  if (!instDone)
92  return NULL;
93  instDone = false;
94  return decode(emi, next_pc.instAddr());
95  }
96 };
97 
98 } // namespace MipsISA
99 } // namespace gem5
100 
101 #endif // __ARCH_MIPS_DECODER_HH__
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::MipsISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:70
types.hh
decode_cache.hh
gem5::MipsISA::Decoder
Definition: decoder.hh:48
gem5::GenericISA::BasicDecodeCache
Definition: decode_cache.hh:43
gem5::RefCountingPtr< StaticInst >
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::MipsISA::Decoder::moreBytes
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition: decoder.hh:62
decoder.hh
gem5::InstDecoder
Definition: decoder.hh:42
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::MipsISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.hh:79
gem5::MipsISA::Decoder::machInst
uint32_t machInst
Definition: decoder.hh:53
static_inst.hh
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:825
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::InstDecoder::instDone
bool instDone
Definition: decoder.hh:49
types.hh
gem5::MipsISA::Decoder::Decoder
Decoder(const MipsDecoderParams &p)
Definition: decoder.hh:56
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
logging.hh
gem5::MipsISA::Decoder::decode
StaticInstPtr decode(PCStateBase &next_pc) override
Decode an instruction or fetch it from the code cache.
Definition: decoder.hh:89
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::MipsISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:52
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::MipsISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)

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