decoder.hh

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#ifndef __ARCH_MIPS_DECODER_HH__
#define __ARCH_MIPS_DECODER_HH__
 
#include "arch/generic/decode_cache.hh"
#include "arch/generic/decoder.hh"
#include "arch/mips/types.hh"
#include "base/logging.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "debug/Decode.hh"
#include "params/MipsDecoder.hh"
 
namespace gem5
{
 
class BaseISA;
 
namespace MipsISA
{
 
class Decoder : public InstDecoder
{
  protected:
    //The extended machine instruction being generated
    ExtMachInst emi;
    uint32_t machInst;
 
  public:
    Decoder(const MipsDecoderParams &p) : InstDecoder(p, &machInst)
    {}
 
    //Use this to give data to the decoder. This should be used
    //when there is control flow.
    void
    moreBytes(const PCStateBase &pc, Addr fetchPC) override
    {
        emi = letoh(machInst);
        instDone = true;
    }
 
  protected:
    static GenericISA::BasicDecodeCache<Decoder, ExtMachInst> defaultCache;
    friend class GenericISA::BasicDecodeCache<Decoder, ExtMachInst>;
 
    StaticInstPtr decodeInst(ExtMachInst mach_inst);
 
    StaticInstPtr
    decode(ExtMachInst mach_inst, Addr addr)
    {
        StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
        DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
                si->getName(), mach_inst);
        return si;
    }
 
  public:
    StaticInstPtr
    decode(PCStateBase &next_pc) override
    {
        if (!instDone)
            return NULL;
        instDone = false;
        return decode(emi, next_pc.instAddr());
    }
};
 
} // namespace MipsISA
} // namespace gem5
 
#endif // __ARCH_MIPS_DECODER_HH__