gem5  v21.1.0.2
decoder.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012 Google
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #ifndef __ARCH_MIPS_DECODER_HH__
30 #define __ARCH_MIPS_DECODER_HH__
31 
33 #include "arch/generic/decoder.hh"
34 #include "arch/mips/types.hh"
35 #include "base/logging.hh"
36 #include "base/types.hh"
37 #include "cpu/static_inst.hh"
38 #include "debug/Decode.hh"
39 
40 namespace gem5
41 {
42 
43 namespace MipsISA
44 {
45 
46 class ISA;
47 class Decoder : public InstDecoder
48 {
49  protected:
50  //The extended machine instruction being generated
52  uint32_t machInst;
53  bool instDone;
54 
55  public:
56  Decoder(ISA* isa = nullptr) : InstDecoder(&machInst), instDone(false)
57  {}
58 
59  void
61  {
62  }
63 
64  void
66  {
67  instDone = false;
68  }
69 
70  //Use this to give data to the decoder. This should be used
71  //when there is control flow.
72  void
73  moreBytes(const PCState &pc, Addr fetchPC)
74  {
75  emi = letoh(machInst);
76  instDone = true;
77  }
78 
79  bool
81  {
82  return true;
83  }
84 
85  bool
87  {
88  return instDone;
89  }
90 
91  void takeOverFrom(Decoder *old) {}
92 
93  protected:
97 
99 
105  {
106  StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
107  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
108  si->getName(), mach_inst);
109  return si;
110  }
111 
112  public:
115  {
116  if (!instDone)
117  return NULL;
118  instDone = false;
119  return decode(emi, nextPC.instAddr());
120  }
121 };
122 
123 } // namespace MipsISA
124 } // namespace gem5
125 
126 #endif // __ARCH_MIPS_DECODER_HH__
gem5::MipsISA::Decoder::instReady
bool instReady()
Definition: decoder.hh:86
gem5::MipsISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:95
types.hh
decode_cache.hh
gem5::MipsISA::Decoder
Definition: decoder.hh:47
gem5::GenericISA::BasicDecodeCache
Definition: decode_cache.hh:43
gem5::MipsISA::Decoder::takeOverFrom
void takeOverFrom(Decoder *old)
Definition: decoder.hh:91
gem5::GenericISA::DelaySlotPCState< 4 >
gem5::RefCountingPtr< StaticInst >
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::MipsISA::Decoder::Decoder
Decoder(ISA *isa=nullptr)
Definition: decoder.hh:56
decoder.hh
gem5::MipsISA::Decoder::reset
void reset()
Definition: decoder.hh:65
gem5::InstDecoder
Definition: decoder.hh:39
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::MipsISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.hh:104
gem5::MipsISA::Decoder::machInst
uint32_t machInst
Definition: decoder.hh:52
static_inst.hh
gem5::MipsISA::Decoder::moreBytes
void moreBytes(const PCState &pc, Addr fetchPC)
Definition: decoder.hh:73
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:772
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::MipsISA::Decoder::instDone
bool instDone
Definition: decoder.hh:53
types.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
logging.hh
gem5::GenericISA::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address the bytes of this instruction came from.
Definition: types.hh:73
gem5::MipsISA::ISA
Definition: isa.hh:54
gem5::MipsISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:51
gem5::MipsISA::Decoder::process
void process()
Definition: decoder.hh:60
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MipsISA::Decoder::decode
StaticInstPtr decode(MipsISA::PCState &nextPC)
Definition: decoder.hh:114
gem5::MipsISA::Decoder::needMoreBytes
bool needMoreBytes()
Definition: decoder.hh:80
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::MipsISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)

Generated on Tue Sep 21 2021 12:24:21 for gem5 by doxygen 1.8.17