gem5 v24.0.0.0
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decoder.hh
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1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
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6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
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9 * redistributions in binary form must reproduce the above copyright
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11 * documentation and/or other materials provided with the distribution;
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14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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27 */
28
29#ifndef __ARCH_MIPS_DECODER_HH__
30#define __ARCH_MIPS_DECODER_HH__
31
34#include "arch/mips/types.hh"
35#include "base/logging.hh"
36#include "base/types.hh"
37#include "cpu/static_inst.hh"
38#include "debug/Decode.hh"
39#include "params/MipsDecoder.hh"
40
41namespace gem5
42{
43
44class BaseISA;
45
46namespace MipsISA
47{
48
49class Decoder : public InstDecoder
50{
51 protected:
52 //The extended machine instruction being generated
54 uint32_t machInst;
55
56 public:
57 Decoder(const MipsDecoderParams &p) : InstDecoder(p, &machInst)
58 {}
59
60 //Use this to give data to the decoder. This should be used
61 //when there is control flow.
62 void
63 moreBytes(const PCStateBase &pc, Addr fetchPC) override
64 {
66 instDone = true;
67 }
68
69 protected:
73
75
81 {
82 StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
83 DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
84 si->getName(), mach_inst);
85 return si;
86 }
87
88 public:
90 decode(PCStateBase &next_pc) override
91 {
92 if (!instDone)
93 return NULL;
94 instDone = false;
95 return decode(emi, next_pc.instAddr());
96 }
97};
98
99} // namespace MipsISA
100} // namespace gem5
101
102#endif // __ARCH_MIPS_DECODER_HH__
#define DPRINTF(x,...)
Definition trace.hh:210
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
StaticInstPtr decode(PCStateBase &next_pc) override
Decode an instruction or fetch it from the code cache.
Definition decoder.hh:90
Decoder(const MipsDecoderParams &p)
Definition decoder.hh:57
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition decoder.hh:63
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition decoder.hh:71
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition decoder.hh:80
StaticInstPtr decodeInst(ExtMachInst mach_inst)
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition pcstate.hh:108
Bitfield< 6 > si
Bitfield< 4 > pc
Bitfield< 0 > p
uint64_t ExtMachInst
Definition types.hh:43
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
T letoh(T value)
Definition byteswap.hh:173
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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