46 using namespace ArmISA;
52 printMnemonic(
ss,
"",
false);
62 printMnemonic(
ss,
"",
false);
63 printIntReg(
ss, dest);
75 printMnemonic(
ss,
"",
false);
76 printIntReg(
ss, dest);
98 (misc_reg.
crn << 10) |
99 (misc_reg.
op1 << 14) |
100 (misc_reg.
op2 << 17) |
101 (misc_reg.
op0 << 20);
116 return std::make_shared<SupervisorTrap>(getEMI(),
iss,
ec);
118 return std::make_shared<HypervisorTrap>(getEMI(),
iss,
ec);
120 return std::make_shared<SecureMonitorTrap>(getEMI(),
iss,
ec);
133 return (
imm & 0x1) << 22;
135 return (
imm & 0x1) << 23;
137 panic(
"Not a valid PSTATE field register\n");
145 std::stringstream
ss;
147 printMiscReg(
ss, dest);
157 std::stringstream
ss;
159 printMiscReg(
ss, dest);
161 printIntReg(
ss, op1);
169 return _iss(misc_reg, op1);
176 std::stringstream
ss;
178 printIntReg(
ss, dest);
180 printMiscReg(
ss, op1);
188 return _iss(misc_reg, dest);
206 return csprintf(
"%-10s (implementation defined)", fullMnemonic.c_str());
212 return _iss(miscReg, intReg);
219 std::stringstream
ss;
221 printIntReg(
ss, dest);
254 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
264 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
274 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
284 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
293 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
305 if (hcr.tge && hcr.e2h) {
310 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
311 TLBIVMALL tlbiOp(target_el, secure,
false);
319 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
331 if (hcr.tge && hcr.e2h) {
336 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
337 TLBIVMALL tlbiOp(target_el, secure,
false);
346 static_cast<Addr>(
bits(value, 43, 0)) << 12,
356 static_cast<Addr>(
bits(value, 43, 0)) << 12,
365 static_cast<Addr>(
bits(value, 43, 0)) << 12,
375 static_cast<Addr>(
bits(value, 43, 0)) << 12,
387 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
391 auto asid = asid_16bits ?
bits(value, 63, 48) :
395 static_cast<Addr>(
bits(value, 43, 0)) << 12,
400 static_cast<Addr>(
bits(value, 43, 0)) << 12,
412 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
416 auto asid = asid_16bits ?
bits(value, 63, 48) :
420 static_cast<Addr>(
bits(value, 43, 0)) << 12,
425 static_cast<Addr>(
bits(value, 43, 0)) << 12,
437 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
441 auto asid = asid_16bits ?
bits(value, 63, 48) :
445 static_cast<Addr>(
bits(value, 43, 0)) << 12,
450 static_cast<Addr>(
bits(value, 43, 0)) << 12,
462 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
466 auto asid = asid_16bits ?
bits(value, 63, 48) :
470 static_cast<Addr>(
bits(value, 43, 0)) << 12,
475 static_cast<Addr>(
bits(value, 43, 0)) << 12,
485 auto asid = asid_16bits ?
bits(value, 63, 48) :
491 if (hcr.tge && hcr.e2h) {
496 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
497 TLBIMVA tlbiOp(target_el, secure,
498 static_cast<Addr>(
bits(value, 43, 0)) << 12,
508 auto asid = asid_16bits ?
bits(value, 63, 48) :
514 if (hcr.tge && hcr.e2h) {
519 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
520 TLBIMVA tlbiOp(target_el, secure,
521 static_cast<Addr>(
bits(value, 43, 0)) << 12,
531 auto asid = asid_16bits ?
bits(value, 63, 48) :
537 if (hcr.tge && hcr.e2h) {
542 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
543 TLBIMVA tlbiOp(target_el, secure,
544 static_cast<Addr>(
bits(value, 43, 0)) << 12,
553 auto asid = asid_16bits ?
bits(value, 63, 48) :
559 if (hcr.tge && hcr.e2h) {
564 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
565 TLBIMVA tlbiOp(target_el, secure,
566 static_cast<Addr>(
bits(value, 43, 0)) << 12,
576 auto asid = asid_16bits ?
bits(value, 63, 48) :
582 if (hcr.tge && hcr.e2h) {
587 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
596 auto asid = asid_16bits ?
bits(value, 63, 48) :
602 if (hcr.tge && hcr.e2h) {
607 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
620 if (hcr.tge && hcr.e2h) {
625 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
627 static_cast<Addr>(
bits(value, 43, 0)) << 12,
641 if (hcr.tge && hcr.e2h) {
646 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
648 static_cast<Addr>(
bits(value, 43, 0)) << 12,
662 if (hcr.tge && hcr.e2h) {
667 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
669 static_cast<Addr>(
bits(value, 43, 0)) << 12,
684 if (hcr.tge && hcr.e2h) {
689 bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
691 static_cast<Addr>(
bits(value, 43, 0)) << 12,
704 bool secure = release->has(ArmExtension::SECURITY) &&
705 !scr.ns && !
bits(value, 63);
710 static_cast<Addr>(
bits(value, top_bit, 0)) << 12,
724 bool secure = release->has(ArmExtension::SECURITY) &&
725 !scr.ns && !
bits(value, 63);
728 static_cast<Addr>(
bits(value, 35, 0)) << 12,
742 bool secure = release->has(ArmExtension::SECURITY) &&
743 !scr.ns && !
bits(value, 63);
748 static_cast<Addr>(
bits(value, top_bit, 0)) << 12,
762 bool secure = release->has(ArmExtension::SECURITY) &&
763 !scr.ns && !
bits(value, 63);
766 static_cast<Addr>(
bits(value, 35, 0)) << 12,
774 panic(
"Invalid TLBI\n");
const ArmRelease * getRelease() const
Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions.
TLB Invalidate by ASID match.
TLB Invalidate by Intermediate Physical Address.
TLB Invalidate by VA, All ASID.
void broadcast(ThreadContext *tc)
Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
RegVal miscRegImm() const
Returns the "register view" of the immediate field.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
uint32_t iss() const override
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
uint32_t _iss(const ArmISA::MiscRegNum64 &misc_reg, RegIndex int_index) const
Fault generateTrap(ArmISA::ExceptionLevel el) const
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
uint32_t iss() const override
uint32_t iss() const override
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal readMiscReg(RegIndex misc_reg)=0
virtual BaseISA * getIsaPtr() const =0
void performTlbi(ExecContext *xc, ArmISA::MiscRegIndex idx, RegVal value) const
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
#define panic(...)
This implements a cprintf based panic() function.
MiscRegNum64 encodeAArch64SysReg(MiscRegIndex misc_reg)
Fault checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
bool EL2Enabled(ThreadContext *tc)
@ MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Bitfield< 27, 25 > encoding
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
std::string csprintf(const char *format, const Args &...args)
void ccprintf(cp::Print &print)
The file contains the definition of a set of TLB Invalidate Instructions.