gem5  v22.0.0.2
misc64.cc
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1 /*
2  * Copyright (c) 2011-2013,2017-2021 Arm Limited
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4  *
5  * The license below extends only to copyright in the software and shall
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36  */
37 
38 #include "arch/arm/insts/misc64.hh"
39 #include "arch/arm/isa.hh"
40 
41 #include "arch/arm/tlbi_op.hh"
42 
43 namespace gem5
44 {
45 
46 using namespace ArmISA;
47 
48 std::string
50 {
51  std::stringstream ss;
52  printMnemonic(ss, "", false);
53  ccprintf(ss, "#0x%x", imm);
54  return ss.str();
55 }
56 
57 std::string
59  Addr pc, const loader::SymbolTable *symtab) const
60 {
61  std::stringstream ss;
62  printMnemonic(ss, "", false);
63  printIntReg(ss, dest);
64  ss << ", ";
65  printIntReg(ss, op1);
66  ccprintf(ss, ", #%d, #%d", imm1, imm2);
67  return ss.str();
68 }
69 
70 std::string
72  Addr pc, const loader::SymbolTable *symtab) const
73 {
74  std::stringstream ss;
75  printMnemonic(ss, "", false);
76  printIntReg(ss, dest);
77  ss << ", ";
78  printIntReg(ss, op1);
79  ss << ", ";
80  printIntReg(ss, op2);
81  ccprintf(ss, ", #%d", imm);
82  return ss.str();
83 }
84 
85 std::string
87  Addr pc, const loader::SymbolTable *symtab) const
88 {
89  return csprintf("%-10s (inst %#08x)", "unknown", encoding());
90 }
91 
92 Fault
94  ExceptionLevel el, uint32_t immediate) const
95 {
97 
98  // Check for traps to supervisor (FP/SIMD regs)
99  if (el <= EL1 && checkEL1Trap(tc, misc_reg, el, ec, immediate)) {
100  return std::make_shared<SupervisorTrap>(machInst, immediate, ec);
101  }
102 
103  // Check for traps to hypervisor
104  if ((ArmSystem::haveEL(tc, EL2) && el <= EL2) &&
105  checkEL2Trap(tc, misc_reg, el, ec, immediate)) {
106  return std::make_shared<HypervisorTrap>(machInst, immediate, ec);
107  }
108 
109  // Check for traps to secure monitor
110  if ((ArmSystem::haveEL(tc, EL3) && el <= EL3) &&
111  checkEL3Trap(tc, misc_reg, el, ec, immediate)) {
112  return std::make_shared<SecureMonitorTrap>(machInst, immediate, ec);
113  }
114 
115  return NoFault;
116 }
117 
118 bool
121  uint32_t &immediate) const
122 {
123  const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
124  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
125  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
126  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
127 
128  bool trap_to_sup = false;
129  switch (misc_reg) {
130  case MISCREG_DAIF:
131  trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0;
132  trap_to_sup = trap_to_sup ||
133  (el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma);
134  break;
135  case MISCREG_DC_ZVA_Xt:
136  // In syscall-emulation mode, this test is skipped and DCZVA is always
137  // allowed at EL0
138  trap_to_sup = el == EL0 && !sctlr.dze && FullSystem;
139  break;
140  case MISCREG_DC_CIVAC_Xt:
141  case MISCREG_DC_CVAC_Xt:
142  trap_to_sup = el == EL0 && !sctlr.uci;
143  break;
144  case MISCREG_FPCR:
145  case MISCREG_FPSR:
146  case MISCREG_FPEXC32_EL2:
147  if ((el == EL0 && cpacr.fpen != 0x3) ||
148  (el == EL1 && !(cpacr.fpen & 0x1))) {
149  trap_to_sup = true;
151  immediate = 0x1E00000;
152  }
153  break;
154  case MISCREG_DC_CVAU_Xt:
155  trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
156  el == EL0;
157  break;
158  case MISCREG_CTR_EL0:
159  trap_to_sup = el == EL0 && !sctlr.uct &&
160  (!hcr.tge || (!scr.ns && !scr.eel2));
161  break;
162  case MISCREG_MDCCSR_EL0:
163  {
164  DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
165  trap_to_sup = el == EL0 && mdscr.tdcc &&
166  (hcr.tge == 0x0 || ( scr.ns == 0x0));
167  }
168  break;
169  case MISCREG_ZCR_EL1:
170  trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0);
171  break;
172  // Generic Timer
174  trap_to_sup = el == EL0 &&
175  isGenericTimerSystemAccessTrapEL1(misc_reg, tc);
176  break;
177  default:
178  break;
179  }
180  return trap_to_sup;
181 }
182 
183 bool
186  uint32_t &immediate) const
187 {
188  const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
189  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
190  const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
191  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
192  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
193  const HDCR mdcr = tc->readMiscReg(MISCREG_MDCR_EL3);
194 
195  bool trap_to_hyp = false;
196 
197  switch (misc_reg) {
199  trap_to_hyp = EL2Enabled(tc) && hcr.tidcp && el == EL1;
200  break;
201  // GICv3 regs
203  {
204  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
205  if (isa->haveGICv3CpuIfc())
206  trap_to_hyp = EL2Enabled(tc) && hcr.fmo && el == EL1;
207  }
208  break;
211  {
212  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
213  if (isa->haveGICv3CpuIfc())
214  trap_to_hyp = EL2Enabled(tc) && hcr.imo && el == EL1;
215  }
216  break;
217  case MISCREG_FPCR:
218  case MISCREG_FPSR:
219  case MISCREG_FPEXC32_EL2:
220  {
221  bool from_el2 = (el == EL2) && (scr.ns || scr.eel2) &&
222  ELIs64(tc,EL2) &&
223  ((!hcr.e2h && cptr.tfp) ||
224  (hcr.e2h && (cptr.fpen == 0x0 ||
225  cptr.fpen == 0xa)));
226  bool from_el1 = (el == EL1) && hcr.nv &&
227  (!hcr.e2h || (hcr.e2h && !hcr.tge));
228  trap_to_hyp = from_el2 || from_el1;
230  immediate = 0x1E00000;
231  }
232  break;
233  case MISCREG_CPACR_EL1:
234  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && cptr.tcpac;
235  break;
236  case MISCREG_SCTLR_EL1:
237  case MISCREG_TTBR0_EL1:
238  case MISCREG_TTBR1_EL1:
239  case MISCREG_TCR_EL1:
240  case MISCREG_ESR_EL1:
241  case MISCREG_FAR_EL1:
242  case MISCREG_AFSR0_EL1:
243  case MISCREG_AFSR1_EL1:
244  case MISCREG_MAIR_EL1:
245  case MISCREG_AMAIR_EL1:
247  {
248  bool tvm = miscRead? hcr.trvm: hcr.tvm;
249  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && tvm;
250  }
251  break;
252  case MISCREG_CPACR_EL12:
253  case MISCREG_SCTLR_EL12:
254  case MISCREG_TTBR0_EL12:
255  case MISCREG_TTBR1_EL12:
256  case MISCREG_TCR_EL12:
257  case MISCREG_ESR_EL12:
258  case MISCREG_FAR_EL12:
259  case MISCREG_AFSR0_EL12:
260  case MISCREG_AFSR1_EL12:
261  case MISCREG_MAIR_EL12:
262  case MISCREG_AMAIR_EL12:
264  case MISCREG_SPSR_EL12:
265  case MISCREG_ELR_EL12:
266  case MISCREG_VBAR_EL12:
267  trap_to_hyp = EL2Enabled(tc) && (el == EL1) &&
268  (hcr.nv && (hcr.nv1 || !hcr.nv2));
269  break;
276 // case MISCREG_TLBI_RVAE1:
277 // case MISCREG_TLBI_RVAAE1:
278 // case MISCREG_TLBI_RVALE1:
279 // case MISCREG_TLBI_RVAALE1:
286 // case MISCREG_TLBI_RVAE1IS:
287 // case MISCREG_TLBI_RVAAE1IS:
288 // case MISCREG_TLBI_RVALE1IS:
289 // case MISCREG_TLBI_RVAALE1IS:
290 // case MISCREG_TLBI_VMALLE1OS:
291 // case MISCREG_TLBI_VAE1OS:
292 // case MISCREG_TLBI_ASIDE1OS:
293 // case MISCREG_TLBI_VAAE1OS:
294 // case MISCREG_TLBI_VALE1OS:
295 // case MISCREG_TLBI_VAALE1OS:
296 // case MISCREG_TLBI_RVAE1OS:
297 // case MISCREG_TLBI_RVAAE1OS:
298 // case MISCREG_TLBI_RVALE1OS:
299 // case MISCREG_TLBI_RVAALE1OS:
300  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.ttlb;
301  break;
302  case MISCREG_IC_IVAU_Xt:
303  case MISCREG_ICIALLU:
304  case MISCREG_ICIALLUIS:
305  trap_to_hyp = (el == EL1) && EL2Enabled(tc) && hcr.tpu;
306  break;
307  case MISCREG_DC_CVAU_Xt:
308  {
309  const bool el2_en = EL2Enabled(tc);
310  if (el == EL0 && el2_en) {
311  const bool in_host = hcr.e2h && hcr.tge;
312  const bool general_trap = el2_en && !in_host && hcr.tge &&
313  !sctlr.uci;
314  const bool tpu_trap = el2_en && !in_host && hcr.tpu;
315  const bool host_trap = el2_en && in_host && !sctlr2.uci;
316  trap_to_hyp = general_trap || tpu_trap || host_trap;
317  }
318  else if (el == EL1 && el2_en) {
319  trap_to_hyp = hcr.tpu;
320  }
321  }
322  break;
323  case MISCREG_DC_IVAC_Xt:
324  trap_to_hyp = EL2Enabled(tc) && el == EL1 && hcr.tpc;
325  break;
326  case MISCREG_DC_CVAC_Xt:
327 // case MISCREG_DC_CVAP_Xt:
328  case MISCREG_DC_CIVAC_Xt:
329  {
330  const bool el2_en = EL2Enabled(tc);
331  if (el == EL0 && el2_en) {
332 
333  const bool in_host = hcr.e2h && hcr.tge;
334  const bool general_trap = el2_en && !in_host && hcr.tge &&
335  !sctlr.uci;
336  const bool tpc_trap = el2_en && !in_host && hcr.tpc;
337  const bool host_trap = el2_en && in_host && !sctlr2.uci;
338  trap_to_hyp = general_trap || tpc_trap || host_trap;
339  } else if (el == EL1 && el2_en) {
340  trap_to_hyp = hcr.tpc;
341  }
342  }
343  break;
344  case MISCREG_DC_ISW_Xt:
345  case MISCREG_DC_CSW_Xt:
346  case MISCREG_DC_CISW_Xt:
347  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.tsw;
348  break;
349  case MISCREG_ACTLR_EL1:
350  trap_to_hyp = EL2Enabled (tc) && (el == EL1) && hcr.tacr;
351  break;
362  trap_to_hyp = EL2Enabled(tc) && el == EL1 && !hcr.apk;
363  break;
364  case MISCREG_ID_PFR0_EL1:
365  case MISCREG_ID_PFR1_EL1:
366  //case MISCREG_ID_PFR2_EL1:
367  case MISCREG_ID_DFR0_EL1:
368  case MISCREG_ID_AFR0_EL1:
381  case MISCREG_MVFR0_EL1:
382  case MISCREG_MVFR1_EL1:
383  case MISCREG_MVFR2_EL1:
395  trap_to_hyp = EL2Enabled(tc) && el == EL1 && hcr.tid3;
396  break;
397  case MISCREG_CTR_EL0:
398  {
399  const bool el2_en = EL2Enabled(tc);
400  if (el == EL0 && el2_en) {
401  const bool in_host = hcr.e2h && hcr.tge;
402  const bool general_trap = el2_en && !in_host && hcr.tge &&
403  !sctlr.uct;
404  const bool tid_trap = el2_en && !in_host && hcr.tid2;
405  const bool host_trap = el2_en && in_host && !sctlr2.uct;
406  trap_to_hyp = general_trap || tid_trap || host_trap;
407  } else if (el == EL1 && el2_en) {
408  trap_to_hyp = hcr.tid2;
409  }
410  }
411  break;
412  case MISCREG_CCSIDR_EL1:
413 // case MISCREG_CCSIDR2_EL1:
414  case MISCREG_CLIDR_EL1:
415  case MISCREG_CSSELR_EL1:
416  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.tid2;
417  break;
418  case MISCREG_AIDR_EL1:
419  case MISCREG_REVIDR_EL1:
420  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.tid1;
421  break;
422  // Generic Timer
424  trap_to_hyp = EL2Enabled(tc) && el <= EL1 &&
425  isGenericTimerSystemAccessTrapEL2(misc_reg, tc);
426  break;
427  case MISCREG_DAIF:
428  trap_to_hyp = EL2Enabled(tc) && el == EL0 &&
429  (hcr.tge && (hcr.e2h || !sctlr.uma));
430  break;
431  case MISCREG_SPSR_EL1:
432  case MISCREG_ELR_EL1:
433  case MISCREG_VBAR_EL1:
434  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv1 && !hcr.nv2;
435  break;
436  case MISCREG_HCR_EL2:
437  case MISCREG_HSTR_EL2:
438  case MISCREG_SP_EL1:
439  case MISCREG_TPIDR_EL2:
440  case MISCREG_VTCR_EL2:
441  case MISCREG_VTTBR_EL2:
442  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv && !hcr.nv2;
443  break;
444 // case MISCREG_AT_S1E1WP_Xt:
445 // case MISCREG_AT_S1E1RP_Xt:
446  case MISCREG_AT_S1E1R_Xt:
447  case MISCREG_AT_S1E1W_Xt:
448  case MISCREG_AT_S1E0W_Xt:
449  case MISCREG_AT_S1E0R_Xt:
450  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.at;
451  break;
452  case MISCREG_ACTLR_EL2:
453  case MISCREG_AFSR0_EL2:
454  case MISCREG_AFSR1_EL2:
455  case MISCREG_AMAIR_EL2:
457  case MISCREG_CPTR_EL2:
458  case MISCREG_DACR32_EL2:
459  case MISCREG_ESR_EL2:
460  case MISCREG_FAR_EL2:
461  case MISCREG_HACR_EL2:
462  case MISCREG_HPFAR_EL2:
463  case MISCREG_MAIR_EL2:
464 // case MISCREG_RMR_EL2:
465  case MISCREG_SCTLR_EL2:
466  case MISCREG_TCR_EL2:
467  case MISCREG_TTBR0_EL2:
468  case MISCREG_TTBR1_EL2:
469  case MISCREG_VBAR_EL2:
470  case MISCREG_VMPIDR_EL2:
471  case MISCREG_VPIDR_EL2:
472  case MISCREG_TLBI_ALLE1:
474 // case MISCREG_TLBI_ALLE1OS:
475  case MISCREG_TLBI_ALLE2:
477 // case MISCREG_TLBI_ALLE2OS:
480 // case MISCREG_TLBI_IPAS2E1OS:
483 // case MISCREG_TLBI_IPAS2LE1OS:
484 // case MISCREG_TLBI_RIPAS2E1:
485 // case MISCREG_TLBI_RIPAS2E1IS:
486 // case MISCREG_TLBI_RIPAS2E1OS:
487 // case MISCREG_TLBI_RIPAS2LE1:
488 // case MISCREG_TLBI_RIPAS2LE1IS:
489 // case MISCREG_TLBI_RIPAS2LE1OS:
490 // case MISCREG_TLBI_RVAE2:
491 // case MISCREG_TLBI_RVAE2IS:
492 // case MISCREG_TLBI_RVAE2OS:
493 // case MISCREG_TLBI_RVALE2:
494 // case MISCREG_TLBI_RVALE2IS:
495 // case MISCREG_TLBI_RVALE2OS:
498 // case MISCREG_TLBI_VAE2OS:
501 // case MISCREG_TLBI_VALE2OS:
504 // case MISCREG_TLBI_VMALLS12E1OS:
505  case MISCREG_AT_S1E2W_Xt:
506  case MISCREG_AT_S1E2R_Xt:
511  case MISCREG_SPSR_UND:
512  case MISCREG_SPSR_IRQ:
513  case MISCREG_SPSR_FIQ:
514  case MISCREG_SPSR_ABT:
515  case MISCREG_SPSR_EL2:
516  case MISCREG_ELR_EL2:
517  case MISCREG_IFSR32_EL2:
519  case MISCREG_MDCR_EL2:
520  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv;
521  break;
522 // case MISCREG_VSTTBR_EL2:
523 // case MISCREG_VSTCR_EL2:
524 // trap_to_hyp = (el == EL1) && !scr.ns && scr.eel2 && ELIs64(tc,EL2)
525 // && !hcr.nv2 && hcr.nv && (!hcr.e2h|| (hcr.e2h && !hcr.tge));
526 // break;
527 
528  //case MISCREG_LORC_EL1:
529  //case MISCREG_LOREA_EL1:
530  //case MISCREG_LORID_EL1:
531  //case MISCREG_LORN_EL1:
532  //case MISCREG_LORSA_EL1:
533  // trap_to_hyp = (el == EL1) && (scr.ns || scr.eel2) && ELIs64(tc,EL2)
534  // && hcr.tlor && (!hcr.e2h || (hcr.e2h && !hcr.tge));
535  // break;
536 
537  case MISCREG_DC_ZVA_Xt:
538  {
539  const bool el2_en = EL2Enabled(tc);
540  if (el == EL0 && el2_en) {
541  const bool in_host = hcr.e2h && hcr.tge;
542  const bool general_trap = el2_en && !in_host && hcr.tge &&
543  !sctlr.dze;
544  const bool tdz_trap = el2_en && !in_host && hcr.tdz;
545  const bool host_trap = el2_en && in_host && !sctlr2.dze;
546  trap_to_hyp = general_trap || tdz_trap || host_trap;
547  } else if (el == EL1 && el2_en) {
548  trap_to_hyp = hcr.tdz;
549  }
550  }
551  break;
552  case MISCREG_DBGBVR0_EL1:
553  case MISCREG_DBGBVR1_EL1:
554  case MISCREG_DBGBVR2_EL1:
555  case MISCREG_DBGBVR3_EL1:
556  case MISCREG_DBGBVR4_EL1:
557  case MISCREG_DBGBVR5_EL1:
558  case MISCREG_DBGBVR6_EL1:
559  case MISCREG_DBGBVR7_EL1:
560  case MISCREG_DBGBVR8_EL1:
561  case MISCREG_DBGBVR9_EL1:
568  case MISCREG_DBGBCR0_EL1:
569  case MISCREG_DBGBCR1_EL1:
570  case MISCREG_DBGBCR2_EL1:
571  case MISCREG_DBGBCR3_EL1:
572  case MISCREG_DBGBCR4_EL1:
573  case MISCREG_DBGBCR5_EL1:
574  case MISCREG_DBGBCR6_EL1:
575  case MISCREG_DBGBCR7_EL1:
576  case MISCREG_DBGBCR8_EL1:
577  case MISCREG_DBGBCR9_EL1:
584  case MISCREG_DBGWVR0_EL1:
585  case MISCREG_DBGWVR1_EL1:
586  case MISCREG_DBGWVR2_EL1:
587  case MISCREG_DBGWVR3_EL1:
588  case MISCREG_DBGWVR4_EL1:
589  case MISCREG_DBGWVR5_EL1:
590  case MISCREG_DBGWVR6_EL1:
591  case MISCREG_DBGWVR7_EL1:
592  case MISCREG_DBGWVR8_EL1:
593  case MISCREG_DBGWVR9_EL1:
600  case MISCREG_DBGWCR0_EL1:
601  case MISCREG_DBGWCR1_EL1:
602  case MISCREG_DBGWCR2_EL1:
603  case MISCREG_DBGWCR3_EL1:
604  case MISCREG_DBGWCR4_EL1:
605  case MISCREG_DBGWCR5_EL1:
606  case MISCREG_DBGWCR6_EL1:
607  case MISCREG_DBGWCR7_EL1:
608  case MISCREG_DBGWCR8_EL1:
609  case MISCREG_DBGWCR9_EL1:
616  case MISCREG_MDCCINT_EL1:
617  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && mdcr.tda;
618  break;
619  case MISCREG_ZCR_EL1:
620  {
621  bool from_el1 = (el == EL1) && EL2Enabled(tc) &&
622  ELIs64(tc, EL2) && ((!hcr.e2h && cptr.tz) ||
623  (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
624  bool from_el2 = (el == EL2) && ((!hcr.e2h && cptr.tz) ||
625  (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
626  trap_to_hyp = from_el1 || from_el2;
627  }
628  ec = EC_TRAPPED_SVE;
629  immediate = 0;
630  break;
631  case MISCREG_ZCR_EL2:
632  {
633  bool from_el1 = (el == EL1) && EL2Enabled(tc) && hcr.nv;
634  bool from_el2 = (el == EL2) && ((!hcr.e2h && cptr.tz) ||
635  (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
636  trap_to_hyp = from_el1 || from_el2;
638  }
639  immediate = 0;
640  break;
641  default:
642  break;
643  }
644  return trap_to_hyp;
645 }
646 
647 bool
648 MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
650  uint32_t &immediate) const
651 {
652  const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3);
653  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
654  const HDCR mdcr = tc->readMiscReg(MISCREG_MDCR_EL3);
655  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
656  bool trap_to_mon = false;
657 
658  switch (misc_reg) {
659  // FP/SIMD regs
660  case MISCREG_FPCR:
661  case MISCREG_FPSR:
662  case MISCREG_FPEXC32_EL2:
663  trap_to_mon = cptr.tfp && ELIs64(tc, EL3);
665  immediate = 0x1E00000;
666  break;
667  // CPACR, CPTR
668  case MISCREG_CPACR_EL12:
669  trap_to_mon = ((el == EL2 && cptr.tcpac && ELIs64(tc, EL3)) ||
670  (el == EL1 && cptr.tcpac && ELIs64(tc, EL3) &&
671  (!hcr.nv2 || hcr.nv1 || !hcr.nv))) ;
672  break;
673  case MISCREG_CPACR_EL1:
674  trap_to_mon = el <= EL2 && cptr.tcpac && ELIs64(tc, EL3);
675  break;
676  case MISCREG_CPTR_EL2:
677  if (el == EL2) {
678  trap_to_mon = cptr.tcpac;
679  }
680  break;
681 // case MISCREG_LORC_EL1:
682 // case MISCREG_LOREA_EL1:
683 // case MISCREG_LORID_EL1:
684 // case MISCREG_LORN_EL1:
685 // case MISCREG_LORSA_EL1:
686 // trap_to_mon = (el <= EL2) && scr.ns && ELIs64(tc,EL3)
687 // && hcr.tlor && (!hcr.e2h || (hcr.e2h && !hcr.tge));
688 // break;
689  case MISCREG_MDCCSR_EL0:
690  trap_to_mon = (el <= EL2) && ELIs64(tc, EL3) && mdcr.tda == 0x1;
691  break;
702  trap_to_mon = (el == EL1 || el == EL2) && scr.apk == 0 &&
703  ELIs64(tc, EL3);
704  break;
705  // Generic Timer
707  trap_to_mon = el == EL1 &&
708  isGenericTimerSystemAccessTrapEL3(misc_reg, tc);
709  break;
710  case MISCREG_DBGBVR0_EL1:
711  case MISCREG_DBGBVR1_EL1:
712  case MISCREG_DBGBVR2_EL1:
713  case MISCREG_DBGBVR3_EL1:
714  case MISCREG_DBGBVR4_EL1:
715  case MISCREG_DBGBVR5_EL1:
716  case MISCREG_DBGBVR6_EL1:
717  case MISCREG_DBGBVR7_EL1:
718  case MISCREG_DBGBVR8_EL1:
719  case MISCREG_DBGBVR9_EL1:
726  case MISCREG_DBGBCR0_EL1:
727  case MISCREG_DBGBCR1_EL1:
728  case MISCREG_DBGBCR2_EL1:
729  case MISCREG_DBGBCR3_EL1:
730  case MISCREG_DBGBCR4_EL1:
731  case MISCREG_DBGBCR5_EL1:
732  case MISCREG_DBGBCR6_EL1:
733  case MISCREG_DBGBCR7_EL1:
734  case MISCREG_DBGBCR8_EL1:
735  case MISCREG_DBGBCR9_EL1:
743  case MISCREG_DBGWVR0_EL1:
744  case MISCREG_DBGWVR1_EL1:
745  case MISCREG_DBGWVR2_EL1:
746  case MISCREG_DBGWVR3_EL1:
747  case MISCREG_DBGWVR4_EL1:
748  case MISCREG_DBGWVR5_EL1:
749  case MISCREG_DBGWVR6_EL1:
750  case MISCREG_DBGWVR7_EL1:
751  case MISCREG_DBGWVR8_EL1:
752  case MISCREG_DBGWVR9_EL1:
759  case MISCREG_DBGWCR0_EL1:
760  case MISCREG_DBGWCR1_EL1:
761  case MISCREG_DBGWCR2_EL1:
762  case MISCREG_DBGWCR3_EL1:
763  case MISCREG_DBGWCR4_EL1:
764  case MISCREG_DBGWCR5_EL1:
765  case MISCREG_DBGWCR6_EL1:
766  case MISCREG_DBGWCR7_EL1:
767  case MISCREG_DBGWCR8_EL1:
768  case MISCREG_DBGWCR9_EL1:
775  case MISCREG_MDCCINT_EL1:
776  case MISCREG_MDCR_EL2:
777  trap_to_mon = ELIs64(tc, EL3) && mdcr.tda && (el == EL2);
778  break;
779  case MISCREG_ZCR_EL1:
780  trap_to_mon = !cptr.ez && ((el == EL3) ||
781  ((el <= EL2) && ArmSystem::haveEL(tc,EL3) && ELIs64(tc, EL3)));
782  ec = EC_TRAPPED_SVE;
783  immediate = 0;
784  break;
785  case MISCREG_ZCR_EL2:
786  trap_to_mon = !cptr.ez && ((el == EL3) ||
787  ((el == EL2) && ArmSystem::haveEL(tc,EL3) && ELIs64(tc, EL3)));
788  ec = EC_TRAPPED_SVE;
789  immediate = 0;
790  break;
791  case MISCREG_ZCR_EL3:
792  trap_to_mon = !cptr.ez && (el == EL3);
793  ec = EC_TRAPPED_SVE;
794  immediate = 0;
795  break;
796  default:
797  break;
798  }
799  return trap_to_mon;
800 }
801 
802 RegVal
803 MiscRegImmOp64::miscRegImm() const
804 {
805  switch (dest) {
806  case MISCREG_SPSEL:
807  return imm & 0x1;
808  case MISCREG_PAN:
809  return (imm & 0x1) << 22;
810  case MISCREG_UAO:
811  return (imm & 0x1) << 23;
812  default:
813  panic("Not a valid PSTATE field register\n");
814  }
815 }
816 
817 std::string
818 MiscRegImmOp64::generateDisassembly(
819  Addr pc, const loader::SymbolTable *symtab) const
820 {
821  std::stringstream ss;
822  printMnemonic(ss);
823  printMiscReg(ss, dest);
824  ss << ", ";
825  ccprintf(ss, "#0x%x", imm);
826  return ss.str();
827 }
828 
829 std::string
830 MiscRegRegImmOp64::generateDisassembly(
831  Addr pc, const loader::SymbolTable *symtab) const
832 {
833  std::stringstream ss;
834  printMnemonic(ss);
835  printMiscReg(ss, dest);
836  ss << ", ";
837  printIntReg(ss, op1);
838  return ss.str();
839 }
840 
841 std::string
842 RegMiscRegImmOp64::generateDisassembly(
843  Addr pc, const loader::SymbolTable *symtab) const
844 {
845  std::stringstream ss;
846  printMnemonic(ss);
847  printIntReg(ss, dest);
848  ss << ", ";
849  printMiscReg(ss, op1);
850  return ss.str();
851 }
852 
853 Fault
854 MiscRegImplDefined64::execute(ExecContext *xc,
855  Trace::InstRecord *traceData) const
856 {
857  auto tc = xc->tcBase();
858  const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
859  const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
860 
861  Fault fault = trap(tc, miscReg, el, imm);
862 
863  if (fault != NoFault) {
864  return fault;
865 
866  } else if (warning) {
867  warn_once("\tinstruction '%s' unimplemented\n", fullMnemonic.c_str());
868  return NoFault;
869 
870  } else {
871  return std::make_shared<UndefinedInstruction>(machInst, false,
872  mnemonic);
873  }
874 }
875 
876 std::string
877 MiscRegImplDefined64::generateDisassembly(
878  Addr pc, const loader::SymbolTable *symtab) const
879 {
880  return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
881 }
882 
883 std::string
884 RegNone::generateDisassembly(
885  Addr pc, const loader::SymbolTable *symtab) const
886 {
887  std::stringstream ss;
888  printMnemonic(ss);
889  printIntReg(ss, dest);
890  return ss.str();
891 }
892 
893 void
894 TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
895 {
896  ThreadContext* tc = xc->tcBase();
897  auto isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
898  auto release = isa->getRelease();
899 
900  bool asid_16bits = ArmSystem::haveLargeAsid64(tc);
901 
902  switch (dest_idx) {
903  // AArch64 TLB Invalidate All, EL3
904  case MISCREG_TLBI_ALLE3:
905  {
906  TLBIALLEL tlbiOp(EL3, true);
907  tlbiOp(tc);
908  return;
909  }
910  // AArch64 TLB Invalidate All, EL3, Inner Shareable
912  {
913  TLBIALLEL tlbiOp(EL3, true);
914  tlbiOp.broadcast(tc);
915  return;
916  }
917  // AArch64 TLB Invalidate All, EL2
918  case MISCREG_TLBI_ALLE2:
919  {
920  SCR scr = tc->readMiscReg(MISCREG_SCR);
921 
922  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
923  TLBIALLEL tlbiOp(EL2, secure);
924  tlbiOp(tc);
925  return;
926  }
927  // AArch64 TLB Invalidate All, EL2, Inner Shareable
929  {
930  SCR scr = tc->readMiscReg(MISCREG_SCR);
931 
932  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
933  TLBIALLEL tlbiOp(EL2, secure);
934  tlbiOp.broadcast(tc);
935  return;
936  }
937  // AArch64 TLB Invalidate All, EL1
938  case MISCREG_TLBI_ALLE1:
939  {
940  SCR scr = tc->readMiscReg(MISCREG_SCR);
941 
942  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
943  TLBIALLEL tlbiOp(EL1, secure);
944  tlbiOp(tc);
945  return;
946  }
947  // AArch64 TLB Invalidate All, EL1, Inner Shareable
949  {
950  SCR scr = tc->readMiscReg(MISCREG_SCR);
951 
952  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
953  TLBIALLEL tlbiOp(EL1, secure);
954  tlbiOp.broadcast(tc);
955  return;
956  }
958  {
959  SCR scr = tc->readMiscReg(MISCREG_SCR);
960 
961  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
962  TLBIVMALL tlbiOp(EL1, secure, true);
963  tlbiOp(tc);
964  return;
965  }
967  {
968  SCR scr = tc->readMiscReg(MISCREG_SCR);
969 
970  ExceptionLevel target_el = EL1;
971  if (EL2Enabled(tc)) {
972  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
973  if (hcr.tge && hcr.e2h) {
974  target_el = EL2;
975  }
976  }
977 
978  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
979  TLBIVMALL tlbiOp(target_el, secure, false);
980  tlbiOp(tc);
981  return;
982  }
984  {
985  SCR scr = tc->readMiscReg(MISCREG_SCR);
986 
987  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
988  TLBIVMALL tlbiOp(EL1, secure, true);
989  tlbiOp.broadcast(tc);
990  return;
991  }
993  {
994  SCR scr = tc->readMiscReg(MISCREG_SCR);
995 
996  ExceptionLevel target_el = EL1;
997  if (EL2Enabled(tc)) {
998  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
999  if (hcr.tge && hcr.e2h) {
1000  target_el = EL2;
1001  }
1002  }
1003 
1004  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1005  TLBIVMALL tlbiOp(target_el, secure, false);
1006  tlbiOp.broadcast(tc);
1007  return;
1008  }
1009  // VAEx(IS) and VALEx(IS) are the same because TLBs
1010  // only store entries
1011  // from the last level of translation table walks
1012  // AArch64 TLB Invalidate by VA, EL3
1013  case MISCREG_TLBI_VAE3_Xt:
1014  case MISCREG_TLBI_VALE3_Xt:
1015  {
1016 
1017  TLBIMVAA tlbiOp(EL3, true,
1018  static_cast<Addr>(bits(value, 43, 0)) << 12);
1019  tlbiOp(tc);
1020  return;
1021  }
1022  // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1025  {
1026  TLBIMVAA tlbiOp(EL3, true,
1027  static_cast<Addr>(bits(value, 43, 0)) << 12);
1028 
1029  tlbiOp.broadcast(tc);
1030  return;
1031  }
1032  // AArch64 TLB Invalidate by VA, EL2
1033  case MISCREG_TLBI_VAE2_Xt:
1034  case MISCREG_TLBI_VALE2_Xt:
1035  {
1036  SCR scr = tc->readMiscReg(MISCREG_SCR);
1037  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1038 
1039  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1040 
1041  if (hcr.e2h) {
1042  // The asid will only be used when e2h == 1
1043  auto asid = asid_16bits ? bits(value, 63, 48) :
1044  bits(value, 55, 48);
1045 
1046  TLBIMVA tlbiOp(EL2, secure,
1047  static_cast<Addr>(bits(value, 43, 0)) << 12,
1048  asid);
1049  tlbiOp(tc);
1050  } else {
1051  TLBIMVAA tlbiOp(EL2, secure,
1052  static_cast<Addr>(bits(value, 43, 0)) << 12);
1053  tlbiOp(tc);
1054  }
1055  return;
1056  }
1057  // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1060  {
1061  SCR scr = tc->readMiscReg(MISCREG_SCR);
1062  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1063 
1064  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1065 
1066  if (hcr.e2h) {
1067  // The asid will only be used when e2h == 1
1068  auto asid = asid_16bits ? bits(value, 63, 48) :
1069  bits(value, 55, 48);
1070 
1071  TLBIMVA tlbiOp(EL2, secure,
1072  static_cast<Addr>(bits(value, 43, 0)) << 12,
1073  asid);
1074  tlbiOp.broadcast(tc);
1075  } else {
1076  TLBIMVAA tlbiOp(EL2, secure,
1077  static_cast<Addr>(bits(value, 43, 0)) << 12);
1078  tlbiOp.broadcast(tc);
1079  }
1080  return;
1081  }
1082  // AArch64 TLB Invalidate by VA, EL1
1083  case MISCREG_TLBI_VAE1_Xt:
1084  case MISCREG_TLBI_VALE1_Xt:
1085  {
1086  SCR scr = tc->readMiscReg(MISCREG_SCR);
1087  auto asid = asid_16bits ? bits(value, 63, 48) :
1088  bits(value, 55, 48);
1089 
1090  ExceptionLevel target_el = EL1;
1091  if (EL2Enabled(tc)) {
1092  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1093  if (hcr.tge && hcr.e2h) {
1094  target_el = EL2;
1095  }
1096  }
1097 
1098  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1099  TLBIMVA tlbiOp(target_el, secure,
1100  static_cast<Addr>(bits(value, 43, 0)) << 12,
1101  asid);
1102 
1103  tlbiOp(tc);
1104  return;
1105  }
1106  // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1109  {
1110  SCR scr = tc->readMiscReg(MISCREG_SCR);
1111  auto asid = asid_16bits ? bits(value, 63, 48) :
1112  bits(value, 55, 48);
1113 
1114  ExceptionLevel target_el = EL1;
1115  if (EL2Enabled(tc)) {
1116  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1117  if (hcr.tge && hcr.e2h) {
1118  target_el = EL2;
1119  }
1120  }
1121 
1122  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1123  TLBIMVA tlbiOp(target_el, secure,
1124  static_cast<Addr>(bits(value, 43, 0)) << 12,
1125  asid);
1126 
1127  tlbiOp.broadcast(tc);
1128  return;
1129  }
1130  // AArch64 TLB Invalidate by ASID, EL1
1132  {
1133  SCR scr = tc->readMiscReg(MISCREG_SCR);
1134  auto asid = asid_16bits ? bits(value, 63, 48) :
1135  bits(value, 55, 48);
1136 
1137  ExceptionLevel target_el = EL1;
1138  if (EL2Enabled(tc)) {
1139  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1140  if (hcr.tge && hcr.e2h) {
1141  target_el = EL2;
1142  }
1143  }
1144 
1145  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1146  TLBIASID tlbiOp(target_el, secure, asid);
1147  tlbiOp(tc);
1148  return;
1149  }
1150  // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1152  {
1153  SCR scr = tc->readMiscReg(MISCREG_SCR);
1154  auto asid = asid_16bits ? bits(value, 63, 48) :
1155  bits(value, 55, 48);
1156 
1157  ExceptionLevel target_el = EL1;
1158  if (EL2Enabled(tc)) {
1159  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1160  if (hcr.tge && hcr.e2h) {
1161  target_el = EL2;
1162  }
1163  }
1164 
1165  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1166  TLBIASID tlbiOp(target_el, secure, asid);
1167  tlbiOp.broadcast(tc);
1168  return;
1169  }
1170  // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1171  // entries from the last level of translation table walks
1172  // AArch64 TLB Invalidate by VA, All ASID, EL1
1173  case MISCREG_TLBI_VAAE1_Xt:
1175  {
1176  SCR scr = tc->readMiscReg(MISCREG_SCR);
1177 
1178  ExceptionLevel target_el = EL1;
1179  if (EL2Enabled(tc)) {
1180  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1181  if (hcr.tge && hcr.e2h) {
1182  target_el = EL2;
1183  }
1184  }
1185 
1186  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1187  TLBIMVAA tlbiOp(target_el, secure,
1188  static_cast<Addr>(bits(value, 43, 0)) << 12);
1189 
1190  tlbiOp(tc);
1191  return;
1192  }
1193  // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1196  {
1197  SCR scr = tc->readMiscReg(MISCREG_SCR);
1198 
1199  ExceptionLevel target_el = EL1;
1200  if (EL2Enabled(tc)) {
1201  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1202  if (hcr.tge && hcr.e2h) {
1203  target_el = EL2;
1204  }
1205  }
1206 
1207  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1208  TLBIMVAA tlbiOp(target_el, secure,
1209  static_cast<Addr>(bits(value, 43, 0)) << 12);
1210 
1211  tlbiOp.broadcast(tc);
1212  return;
1213  }
1214  // AArch64 TLB Invalidate by Intermediate Physical Address,
1215  // Stage 2, EL1
1218  {
1219  SCR scr = tc->readMiscReg(MISCREG_SCR);
1220 
1221  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1222  TLBIIPA tlbiOp(EL1, secure,
1223  static_cast<Addr>(bits(value, 35, 0)) << 12);
1224 
1225  tlbiOp(tc);
1226  return;
1227  }
1228  // AArch64 TLB Invalidate by Intermediate Physical Address,
1229  // Stage 2, EL1, Inner Shareable
1232  {
1233  SCR scr = tc->readMiscReg(MISCREG_SCR);
1234 
1235  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1236  TLBIIPA tlbiOp(EL1, secure,
1237  static_cast<Addr>(bits(value, 35, 0)) << 12);
1238 
1239  tlbiOp.broadcast(tc);
1240  return;
1241  }
1242  default:
1243  panic("Invalid TLBI\n");
1244  }
1245 }
1246 
1247 } // namespace gem5
gem5::ArmISA::MISCREG_APDAKeyLo_EL1
@ MISCREG_APDAKeyLo_EL1
Definition: misc.hh:827
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: misc.hh:576
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:650
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:589
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: misc.hh:484
gem5::ArmISA::MISCREG_DBGWVR8_EL1
@ MISCREG_DBGWVR8_EL1
Definition: misc.hh:499
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: misc.hh:729
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:675
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::ArmISA::MISCREG_AMAIR_EL12
@ MISCREG_AMAIR_EL12
Definition: misc.hh:730
gem5::ArmISA::TLBIALLEL
Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions.
Definition: tlbi_op.hh:162
gem5::MiscRegOp64::checkEL1Trap
bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:119
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:273
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:597
gem5::ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: misc.hh:705
gem5::ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition: misc.hh:492
gem5::ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition: misc.hh:665
gem5::MiscRegOp64::checkEL2Trap
bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:184
gem5::ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition: misc.hh:670
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:682
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: misc.hh:521
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: misc.hh:298
gem5::ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition: misc.hh:591
gem5::ArmISA::MISCREG_IFSR32_EL2
@ MISCREG_IFSR32_EL2
Definition: misc.hh:642
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:510
gem5::ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition: misc.hh:550
gem5::ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:216
gem5::ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:702
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:676
gem5::ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition: misc.hh:578
gem5::ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition: misc.hh:574
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:478
gem5::ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition: misc.hh:553
gem5::ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition: misc.hh:668
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:605
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: misc.hh:490
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::MISCREG_FAR_EL12
@ MISCREG_FAR_EL12
Definition: misc.hh:651
gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:691
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition: misc.hh:590
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:588
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:476
gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:688
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::MISCREG_APDAKeyHi_EL1
@ MISCREG_APDAKeyHi_EL1
Definition: misc.hh:826
gem5::ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition: misc.hh:667
gem5::ArmISA::asid
asid
Definition: misc_types.hh:618
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:594
gem5::ArmISA::isGenericTimerSystemAccessTrapEL1
bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:883
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:519
gem5::ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition: misc.hh:664
gem5::ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition: misc.hh:557
gem5::ArmISA::MISCREG_DBGWVR14_EL1
@ MISCREG_DBGWVR14_EL1
Definition: misc.hh:505
gem5::ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition: misc.hh:494
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:692
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: misc.hh:621
gem5::ArmISA::MISCREG_APDBKeyLo_EL1
@ MISCREG_APDBKeyLo_EL1
Definition: misc.hh:829
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:600
gem5::ArmISA::isGenericTimerSystemAccessTrapEL2
bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:943
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:741
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:697
gem5::ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:703
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: misc.hh:644
gem5::ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition: misc.hh:547
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:645
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:663
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:516
gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: misc.hh:696
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:517
gem5::ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition: misc.hh:504
gem5::ArmISA::MISCREG_APIAKeyLo_EL1
@ MISCREG_APIAKeyLo_EL1
Definition: misc.hh:833
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:483
gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: misc.hh:683
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:746
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:567
gem5::ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition: misc.hh:460
gem5::ArmISA::MISCREG_ICC_SGI1R_EL1
@ MISCREG_ICC_SGI1R_EL1
Definition: misc.hh:861
gem5::ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition: misc.hh:554
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition: misc.hh:555
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:488
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition: misc.hh:556
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:487
gem5::ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition: misc.hh:502
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: misc.hh:727
gem5::ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: misc.hh:689
gem5::ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition: misc.hh:616
gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:680
gem5::ArmISA::encoding
Bitfield< 27, 25 > encoding
Definition: types.hh:90
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:565
gem5::ImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:49
gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: misc.hh:707
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:512
gem5::ArmISA::MISCREG_DBGBVR15_EL1
@ MISCREG_DBGBVR15_EL1
Definition: misc.hh:474
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:704
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:545
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:607
gem5::ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:701
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:513
gem5::ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition: misc.hh:544
gem5::ArmISA::MISCREG_DBGWVR9_EL1
@ MISCREG_DBGWVR9_EL1
Definition: misc.hh:500
gem5::ArmISA::ec
ec
Definition: misc_types.hh:670
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: misc.hh:731
gem5::ArmISA::MISCREG_APIBKeyHi_EL1
@ MISCREG_APIBKeyHi_EL1
Definition: misc.hh:834
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:459
gem5::ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition: misc.hh:601
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: misc.hh:522
gem5::ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition: misc.hh:543
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:615
misc64.hh
gem5::ArmISA::MISCREG_DBGBVR14_EL1
@ MISCREG_DBGBVR14_EL1
Definition: misc.hh:473
gem5::ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition: misc.hh:464
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:563
gem5::ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition: misc.hh:581
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:509
gem5::ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition: misc.hh:584
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:580
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:823
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition: misc.hh:549
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:596
gem5::ArmISA::MISCREG_TCR_EL12
@ MISCREG_TCR_EL12
Definition: misc.hh:603
gem5::ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition: misc.hh:454
gem5::ArmISA::MISCREG_CONTEXTIDR_EL12
@ MISCREG_CONTEXTIDR_EL12
Definition: misc.hh:747
gem5::ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition: misc.hh:463
gem5::ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition: misc.hh:493
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition: misc.hh:542
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: misc.hh:732
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:281
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:661
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:585
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:566
isa.hh
gem5::ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition: misc.hh:469
gem5::ArmISA::EC_TRAPPED_MSR_MRS_64
@ EC_TRAPPED_MSR_MRS_64
Definition: types.hh:324
gem5::MiscRegOp64::trap
Fault trap(ThreadContext *tc, ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, uint32_t immediate) const
Definition: misc64.cc:93
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:511
gem5::ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition: misc.hh:491
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: misc.hh:293
gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1
@ MISCREG_ICC_ASGI1R_EL1
Definition: misc.hh:862
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:508
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:583
gem5::ArmISA::MISCREG_DBGVCR32_EL2
@ MISCREG_DBGVCR32_EL2
Definition: misc.hh:527
gem5::ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition: misc.hh:560
gem5::ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition: misc.hh:552
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:264
gem5::ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: misc.hh:618
tlbi_op.hh
gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:681
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:626
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:666
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: misc.hh:628
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:662
gem5::ArmISA::MISCREG_ID_ISAR6_EL1
@ MISCREG_ID_ISAR6_EL1
Definition: misc.hh:558
gem5::ArmISA::MISCREG_APIBKeyLo_EL1
@ MISCREG_APIBKeyLo_EL1
Definition: misc.hh:835
gem5::ArmISA::MISCREG_APIAKeyHi_EL1
@ MISCREG_APIAKeyHi_EL1
Definition: misc.hh:832
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::RegRegRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:71
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:479
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition: misc.hh:461
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:564
gem5::ArmISA::MISCREG_APDBKeyHi_EL1
@ MISCREG_APDBKeyHi_EL1
Definition: misc.hh:828
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:571
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:613
gem5::ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition: misc.hh:575
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_APGAKeyLo_EL1
@ MISCREG_APGAKeyLo_EL1
Definition: misc.hh:831
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:475
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
warning
const char * warning
Definition: remote_gdb.cc:202
gem5::ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: misc.hh:643
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:673
gem5::ArmISA::TLBIIPA
TLB Invalidate by Intermediate Physical Address.
Definition: tlbi_op.hh:341
gem5::ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition: misc.hh:639
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:672
gem5::ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition: misc.hh:751
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:300
gem5::ArmISA::MISCREG_DBGWVR12_EL1
@ MISCREG_DBGWVR12_EL1
Definition: misc.hh:503
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: misc.hh:699
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:482
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:480
gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: misc.hh:684
gem5::ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition: misc.hh:546
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: misc.hh:485
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:789
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:507
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:518
gem5::ArmISA::MISCREG_APGAKeyHi_EL1
@ MISCREG_APGAKeyHi_EL1
Definition: misc.hh:830
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
gem5::ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition: misc.hh:468
gem5::ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: misc.hh:1092
gem5::ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition: misc.hh:498
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::MISCREG_ICC_SGI0R_EL1
@ MISCREG_ICC_SGI0R_EL1
Definition: misc.hh:863
gem5::ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: misc.hh:1059
gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: misc.hh:687
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: misc.hh:606
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:60
gem5::ArmISA::isGenericTimerSystemAccessTrapEL3
bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:1118
gem5::ArmISA::TLBIOp::broadcast
void broadcast(ThreadContext *tc)
Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
Definition: tlbi_op.hh:73
gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:690
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:477
gem5::ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition: misc.hh:467
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:514
gem5::ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:296
gem5::UnknownOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:86
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::TLBIVMALL
Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.
Definition: tlbi_op.hh:188
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:244
gem5::ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition: misc.hh:548
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:627
gem5::ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition: misc.hh:495
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:579
gem5::ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition: misc.hh:728
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: misc.hh:708
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:481
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::MISCREG_DBGWVR15_EL1
@ MISCREG_DBGWVR15_EL1
Definition: misc.hh:506
gem5::ArmISA::EC_TRAPPED_SIMD_FP
@ EC_TRAPPED_SIMD_FP
Definition: types.hh:310
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:623
gem5::ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: misc.hh:1056
gem5::ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition: misc.hh:466
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: misc.hh:636
gem5::ArmISA::MISCREG_AFSR0_EL12
@ MISCREG_AFSR0_EL12
Definition: misc.hh:637
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:818
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:622
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition: misc.hh:658
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:754
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition: misc.hh:669
gem5::ArmISA::MISCREG_DBGBVR6_EL1
@ MISCREG_DBGBVR6_EL1
Definition: misc.hh:465
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:674
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:587
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: misc.hh:638
gem5::ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:695
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:598
gem5::ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition: misc.hh:1076
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:486
gem5::ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: misc.hh:710
gem5::ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: misc.hh:700
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: misc.hh:1057
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:652
gem5::ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:685
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:515
gem5::ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition: misc.hh:471
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:562
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: misc.hh:653
gem5::ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: misc.hh:686
gem5::ArmISA::MISCREG_FPEXC32_EL2
@ MISCREG_FPEXC32_EL2
Definition: misc.hh:646
gem5::ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition: misc.hh:599
gem5::ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition: misc.hh:582
gem5::ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition: misc.hh:572
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:640
gem5::ArmISA::ISA::getRelease
const ArmRelease * getRelease() const
Definition: isa.hh:641
gem5::ArmISA::MISCREG_DACR32_EL2
@ MISCREG_DACR32_EL2
Definition: misc.hh:612
gem5::ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: misc.hh:679
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:737
gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: misc.hh:706
gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:698
gem5::ArmISA::EC_TRAPPED_SVE
@ EC_TRAPPED_SVE
Definition: types.hh:325
gem5::ArmISA::MISCREG_DBGWVR6_EL1
@ MISCREG_DBGWVR6_EL1
Definition: misc.hh:497
gem5::ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition: misc.hh:641
gem5::RegRegImmImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:58
gem5::ArmISA::MISCREG_ID_MMFR4_EL1
@ MISCREG_ID_MMFR4_EL1
Definition: misc.hh:551
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:456
gem5::ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition: misc.hh:501
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:489
gem5::ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition: misc.hh:738
gem5::ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition: misc.hh:659
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:568
gem5::ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition: misc.hh:573
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:660
gem5::ArmISA::MISCREG_DBGBVR13_EL1
@ MISCREG_DBGBVR13_EL1
Definition: misc.hh:472
gem5::ArmISA::MISCREG_UAO
@ MISCREG_UAO
Definition: misc.hh:1093
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:821
gem5::ArmISA::MISCREG_SPSR_EL12
@ MISCREG_SPSR_EL12
Definition: misc.hh:614
gem5::ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition: misc.hh:559
gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:694
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:602
gem5::ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition: misc.hh:462
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:693
gem5::ArmISA::MISCREG_DBGBVR11_EL1
@ MISCREG_DBGBVR11_EL1
Definition: misc.hh:470
gem5::ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition: misc.hh:523
gem5::ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: misc.hh:709
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:671
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:520
gem5::ArmISA::tvm
Bitfield< 26 > tvm
Definition: misc_types.hh:258
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition: misc.hh:496

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