misc64.cc

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/*
 * Copyright (c) 2011-2013,2017-2024 Arm Limited
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 *
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
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 * terms below provided that you ensure that this notice is replicated
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 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include "arch/arm/insts/misc64.hh"
#include "arch/arm/isa.hh"
 
#include "arch/arm/tlbi_op.hh"
#include "debug/MiscRegs.hh"
 
namespace gem5
{
 
using namespace ArmISA;
 
std::string
ImmOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    ccprintf(ss, "#0x%x", imm);
    return ss.str();
}
 
std::string
RegOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    printIntReg(ss, op1);
    return ss.str();
}
 
std::string
RegImmImmOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    printIntReg(ss, op1);
    ccprintf(ss, "#0x%x", imm1);
    ss << ", ";
    ccprintf(ss, "#0x%x", imm2);
    return ss.str();
}
 
std::string
RegRegImmImmOp64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    printIntReg(ss, dest);
    ss << ", ";
    printIntReg(ss, op1);
    ccprintf(ss, ", #%d, #%d", imm1, imm2);
    return ss.str();
}
 
std::string
RegRegRegImmOp64::generateDisassembly(
    Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    printIntReg(ss, dest);
    ss << ", ";
    printIntReg(ss, op1);
    ss << ", ";
    printIntReg(ss, op2);
    ccprintf(ss, ", #%d", imm);
    return ss.str();
}
 
std::string
UnknownOp64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    return csprintf("%-10s (inst %#08x)", "unknown", encoding());
}
 
uint32_t
MiscRegOp64::_iss(const MiscRegNum64 &misc_reg, RegIndex int_index) const
{
    return _miscRead |
        (misc_reg.crm << 1) |
        (int_index << 5) |
        (misc_reg.crn << 10) |
        (misc_reg.op1 << 14) |
        (misc_reg.op2 << 17) |
        (misc_reg.op0 << 20);
}
 
Fault
MiscRegOp64::generateTrap(ExceptionLevel el) const
{
    return generateTrap(el, ExceptionClass::TRAPPED_MSR_MRS_64, iss());
}
 
RegVal
MiscRegImmOp64::miscRegImm() const
{
    switch (dest) {
      case MISCREG_SPSEL:
        return imm & 0x1;
      case MISCREG_PAN:
        return (imm & 0x1) << 22;
      case MISCREG_UAO:
        return (imm & 0x1) << 23;
      default:
        panic("Not a valid PSTATE field register\n");
    }
}
 
std::string
MiscRegImmOp64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss);
    printMiscReg(ss, dest);
    ss << ", ";
    ccprintf(ss, "#0x%x", imm);
    return ss.str();
}
 
std::string
MiscRegRegImmOp64::generateDisassembly(
    Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss);
    printMiscReg(ss, dest);
    ss << ", ";
    printIntReg(ss, op1);
    return ss.str();
}
 
uint32_t
MiscRegRegImmOp64::iss() const
{
    const auto misc_reg = encodeAArch64SysReg(dest);
    assert(misc_reg.has_value());
    return _iss(misc_reg.value(), op1);
}
 
std::string
RegMiscRegImmOp64::generateDisassembly(
    Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss);
    printIntReg(ss, dest);
    ss << ", ";
    printMiscReg(ss, op1);
    return ss.str();
}
 
uint32_t
RegMiscRegImmOp64::iss() const
{
    const auto misc_reg = encodeAArch64SysReg(op1);
    assert(misc_reg.has_value());
    return _iss(misc_reg.value(), dest);
}
 
Fault
MiscRegImplDefined64::execute(ExecContext *xc,
                              trace::InstRecord *traceData) const
{
    auto tc = xc->tcBase();
    const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 
    return checkFaultAccessAArch64SysReg(
        MISCREG_IMPDEF_UNIMPL, cpsr, tc, *this);
}
 
std::string
MiscRegImplDefined64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
}
 
uint32_t
MiscRegImplDefined64::iss() const
{
    return _iss(miscReg, intReg);
}
 
std::string
RegNone::generateDisassembly(
    Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss);
    printIntReg(ss, dest);
    return ss.str();
}
 
void
TlbiOp64::tlbiAll(ThreadContext *tc, RegVal value,
    SecurityState ss, TranslationRegime regime, bool shareable,
    TlbiAttr attrs)
{
    TLBIALLEL tlbi_op(regime, ss, attrs);
    if (shareable) {
        tlbi_op.broadcast(tc);
    } else {
        tlbi_op(tc);
    }
}
 
void
TlbiOp64::tlbiVmall(ThreadContext *tc, RegVal value,
    SecurityState ss, TranslationRegime regime, bool shareable,
    bool stage2, TlbiAttr attrs)
{
    TLBIVMALL tlbi_op(regime, ss, stage2, attrs);
    if (shareable) {
        tlbi_op.broadcast(tc);
    } else {
        tlbi_op(tc);
    }
}
 
void
TlbiOp64::tlbiVa(ThreadContext *tc, RegVal value,
    SecurityState ss, TranslationRegime regime, bool shareable,
    bool last_level, TlbiAttr attrs)
{
    if (MMU::hasUnprivRegime(regime)) {
        // The asid will only be used when e2h == 1
        bool asid_16bits = ArmSystem::haveLargeAsid64(tc);
        auto asid = asid_16bits ? bits(value, 63, 48) :
                                  bits(value, 55, 48);
 
        TLBIMVA tlbi_op(regime, ss, static_cast<Addr>(bits(value, 43, 0)) << 12,
                        asid, last_level, attrs);
        if (shareable) {
            tlbi_op.broadcast(tc);
        } else {
            tlbi_op(tc);
        }
    } else {
        TLBIMVAA tlbi_op(regime, ss,
            static_cast<Addr>(bits(value, 43, 0)) << 12, last_level,
            attrs);
        if (shareable) {
            tlbi_op.broadcast(tc);
        } else {
            tlbi_op(tc);
        }
    }
}
 
void
TlbiOp64::tlbiVaa(ThreadContext *tc, RegVal value,
    SecurityState ss, TranslationRegime regime, bool shareable,
    bool last_level, TlbiAttr attrs)
{
    TLBIMVAA tlbi_op(regime, ss,
        static_cast<Addr>(bits(value, 43, 0)) << 12, last_level,
        attrs);
    if (shareable) {
        tlbi_op.broadcast(tc);
    } else {
        tlbi_op(tc);
    }
}
 
void
TlbiOp64::tlbiAsid(ThreadContext *tc, RegVal value,
    SecurityState ss, TranslationRegime regime, bool shareable,
    TlbiAttr attrs)
{
    bool asid_16bits = ArmSystem::haveLargeAsid64(tc);
    auto asid = asid_16bits ? bits(value, 63, 48) :
                              bits(value, 55, 48);
 
    TLBIASID tlbi_op(regime, ss, asid, attrs);
    if (shareable) {
        tlbi_op.broadcast(tc);
    } else {
        tlbi_op(tc);
    }
}
 
void
TlbiOp64::tlbiIpaS2(ThreadContext *tc, RegVal value,
    SecurityState ss, TranslationRegime regime, bool shareable,
    bool last_level, TlbiAttr attrs)
{
    if (EL2Enabled(tc)) {
        TLBIIPA tlbi_op(tc, TranslationRegime::EL10, ss, value,
            last_level, attrs);
 
        if (shareable) {
            tlbi_op.broadcast(tc);
        } else {
            tlbi_op(tc);
        }
    }
}
 
void
TlbiOp64::tlbiRvaa(ThreadContext *tc, RegVal value,
    SecurityState ss, TranslationRegime regime, bool shareable,
    bool last_level, TlbiAttr attrs)
{
    TLBIRMVAA tlbi_op(regime, ss, value, last_level, attrs);
    if (shareable) {
        tlbi_op.broadcast(tc);
    } else {
        tlbi_op(tc);
    }
}
 
void
TlbiOp64::tlbiRva(ThreadContext *tc, RegVal value,
    SecurityState ss, TranslationRegime regime, bool shareable, bool last_level,
    TlbiAttr attrs)
{
    if (MMU::hasUnprivRegime(regime)) {
        // The asid will only be used when e2h == 1
        bool asid_16bits = ArmSystem::haveLargeAsid64(tc);
        auto asid = asid_16bits ? bits(value, 63, 48) :
                                  bits(value, 55, 48);
 
        TLBIRMVA tlbi_op(regime, ss, value, asid, last_level, attrs);
        if (shareable) {
            tlbi_op.broadcast(tc);
        } else {
            tlbi_op(tc);
        }
    } else {
        tlbiRvaa(tc, value, ss, regime, shareable, last_level, attrs);
    }
}
 
void
TlbiOp64::tlbiRipaS2(ThreadContext *tc, RegVal value,
    SecurityState ss, TranslationRegime regime, bool shareable,
    bool last_level, TlbiAttr attrs)
{
    if (EL2Enabled(tc)) {
        TLBIRIPA tlbi_op(tc, TranslationRegime::EL10, ss, value,
            last_level, attrs);
 
        if (shareable) {
            tlbi_op.broadcast(tc);
        } else {
            tlbi_op(tc);
        }
    }
}
 
bool
TlbiOp64::fnxsAttrs(ThreadContext *tc)
{
    HCRX hcrx = tc->readMiscRegNoEffect(MISCREG_HCRX_EL2);
    return currEL(tc) == EL1 &&
        HaveExt(tc, ArmExtension::FEAT_XS) &&
        HaveExt(tc, ArmExtension::FEAT_HCX) &&
        isHcrxEL2Enabled(tc) && hcrx.fnxs;
}
 
std::unordered_map<MiscRegIndex, TlbiOp64::TlbiFunc> TlbiOp64::tlbiOps = {
    { MISCREG_TLBI_ALLE3, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                false); // shareable
        }
    },
 
    { MISCREG_TLBI_ALLE3NXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                false, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_ALLE3IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                true); // shareable
        }
    },
 
    { MISCREG_TLBI_ALLE3ISNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_ALLE3OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                true); // shareable
        }
    },
 
    { MISCREG_TLBI_ALLE3OSNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_ALLE2, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                false); // shareable
        }
    },
 
    { MISCREG_TLBI_ALLE2NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                false, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_ALLE2IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true); // shareable
        }
    },
 
    { MISCREG_TLBI_ALLE2ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_ALLE2OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true); // shareable
        }
    },
 
    { MISCREG_TLBI_ALLE2OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_ALLE1, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false); // shareable
        }
    },
 
    { MISCREG_TLBI_ALLE1NXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_ALLE1IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true); // shareable
        }
    },
 
    { MISCREG_TLBI_ALLE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_ALLE1OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true); // shareable
        }
    },
 
    { MISCREG_TLBI_ALLE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiAll(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_VMALLE1, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                false, // stage2
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VMALLE1NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                false, // stage2
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VMALLE1IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // stage2
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VMALLE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // stage2
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VMALLE1OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // stage2
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VMALLE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // stage2
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VMALLS12E1, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                true); // stage2
        }
    },
 
    { MISCREG_TLBI_VMALLS12E1NXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                true, // stage2
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VMALLS12E1IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true); // stage2
        }
    },
 
    { MISCREG_TLBI_VMALLS12E1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true, // stage2
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VMALLS12E1OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true); // stage2
        }
    },
 
    { MISCREG_TLBI_VMALLS12E1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVmall(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true, // stage2
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_VAE3, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                false, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_VAE3NXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                false, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_VAE3IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_VAE3ISNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAE3OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_VAE3OSNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3,            // regime
                true,           // shareable
                false,         // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_VALE3, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                false, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_VALE3NXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3,            // regime
                false,          // shareable
                true,          // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_VALE3IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_VALE3ISNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3,            // regime
                true,           // shareable
                true,          // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_VALE3OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure, // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_VALE3OSNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                SecurityState::Secure,           // secure
                TranslationRegime::EL3,            // regime
                true,           // shareable
                true,          // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAE2, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                false, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_VAE2NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime,               // regime
                false,             // shareable
                false,            // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAE2IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, EL2), // secure
                TranslationRegime::EL2, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_VAE2ISNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, EL2), // secure
                TranslationRegime::EL2,               // regime
                true,              // shareable
                false,            // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_VAE2OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc,EL2), // secure
                TranslationRegime::EL2, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_VAE2OSNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc,EL2), // secure
                TranslationRegime::EL2,               // regime
                true,              // shareable
                false,            // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_VALE2, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                false, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_VALE2NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime,               // regime
                false,             // shareable
                true,            // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VALE2IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_VALE2ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime,               // regime
                true,             // shareable
                true,            // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VALE2OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_VALE2OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime,               // regime
                true,             // shareable
                true,            // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAE1, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VAE1NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAE1IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VAE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAE1OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VAE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VALE1, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                false, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VALE1NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VALE1IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VALE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VALE1OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VALE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiVa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_ASIDE1, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiAsid(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_ASIDE1NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiAsid(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_ASIDE1IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiAsid(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_ASIDE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiAsid(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_ASIDE1OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiAsid(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_ASIDE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiAsid(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAAE1, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VAAE1NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                false, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAAE1IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VAAE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAAE1OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VAAE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAALE1, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VAALE1NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                true, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAALE1IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VAALE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_VAALE1OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_VAALE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiVaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_IPAS2E1, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                false); // last level
        }
    },
 
    { MISCREG_TLBI_IPAS2E1NXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                false, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_IPAS2E1IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                false); // last level
        }
    },
 
    { MISCREG_TLBI_IPAS2E1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                false, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_IPAS2E1OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                false); // last level
        }
    },
 
    { MISCREG_TLBI_IPAS2E1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                false, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_IPAS2LE1, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                true); // last level
        }
    },
 
    { MISCREG_TLBI_IPAS2LE1NXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                true, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_IPAS2LE1IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true); // last level
        }
    },
 
    { MISCREG_TLBI_IPAS2LE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_IPAS2LE1OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true); // last level
        }
    },
 
    { MISCREG_TLBI_IPAS2LE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiIpaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true, // last level
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_RVAE1, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE1NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE1IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE1OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAAE1, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAAE1NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAAE1IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAAE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_RVAAE1OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAAE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE1, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE1NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE1IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE1OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAALE1, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAALE1NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
            HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
            bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
                hcr.fb && !hcr.tge;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                shareable, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAALE1IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAALE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAALE1OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            const TlbiAttr attrs = fnxsAttrs(tc) ?
                TlbiAttr::ExcludeXS : TlbiAttr::None;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                attrs); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAALE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL0) ?
                TranslationRegime::EL20 : TranslationRegime::EL10;
 
            TlbiOp64::tlbiRvaa(tc, value,
                securityStateAtEL(tc, translationEl(regime)), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RIPAS2E1, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_RIPAS2E1NXS, [](ThreadContext *tc, RegVal value)
        {
            tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
 
    { MISCREG_TLBI_RIPAS2E1IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_RIPAS2E1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RIPAS2E1OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_RIPAS2E1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RIPAS2E1OS, [](ThreadContext *tc, RegVal value)
        {
            tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_RIPAS2E1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RIPAS2LE1, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_RIPAS2LE1NXS, [](ThreadContext *tc, RegVal value)
        {
            tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                false, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RIPAS2LE1IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_RIPAS2LE1ISNXS, [](ThreadContext *tc, RegVal value)
        {
            tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RIPAS2LE1OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_RIPAS2LE1OSNXS, [](ThreadContext *tc, RegVal value)
        {
            tlbiRipaS2(tc, value,
                securityStateAtEL(tc, EL1), // secure
                TranslationRegime::EL10, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE2, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                false, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_RVAE2NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                false, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE2IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_RVAE2ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE2OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_RVAE2OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE2, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                false, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_RVALE2NXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                false, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE2IS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_RVALE2ISNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE2OS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_RVALE2OSNXS, [](ThreadContext *tc, RegVal value)
        {
            const TranslationRegime regime = ELIsInHost(tc, EL2) ?
                TranslationRegime::EL20 : TranslationRegime::EL2;
 
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL2), // secure
                regime, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE3, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                false, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_RVAE3NXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                false, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE3IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_RVAE3ISNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVAE3OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                false); // last level only
        }
    },
 
    { MISCREG_TLBI_RVAE3OSNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                false, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE3, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                false, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_RVALE3NXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                false, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE3IS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_RVALE3ISNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
 
    { MISCREG_TLBI_RVALE3OS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                true); // last level only
        }
    },
 
    { MISCREG_TLBI_RVALE3OSNXS, [](ThreadContext *tc, RegVal value)
        {
            TlbiOp64::tlbiRva(tc, value,
                securityStateAtEL(tc, EL3), // secure
                TranslationRegime::EL3, // regime
                true, // shareable
                true, // last level only
                TlbiAttr::ExcludeXS); // attrs
        }
    },
};
 
void
TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
{
    ThreadContext* tc = xc->tcBase();
 
    if (auto it = tlbiOps.find(dest_idx); it != tlbiOps.end()) {
        it->second(tc, value);
    } else {
        panic("Invalid TLBI\n");
    }
}
 
std::pair<Fault, uint64_t>
AtOp64::performAt(ExecContext *xc, MiscRegIndex dest_idx, RegVal val) const
{
    ThreadContext* tc = xc->tcBase();
 
    switch (dest_idx) {
      case MISCREG_AT_S1E1R_Xt:
        return addressTranslation64(tc, MMU::S1E1Tran, BaseMMU::Read, 0, val);
      case MISCREG_AT_S1E1W_Xt:
        return addressTranslation64(tc, MMU::S1E1Tran, BaseMMU::Write, 0, val);
      case MISCREG_AT_S1E0R_Xt:
        return addressTranslation64(tc, MMU::S1E0Tran, BaseMMU::Read,
            MMU::UserMode, val);
      case MISCREG_AT_S1E0W_Xt:
        return addressTranslation64(tc, MMU::S1E0Tran, BaseMMU::Write,
            MMU::UserMode, val);
      case MISCREG_AT_S1E2R_Xt:
        return addressTranslation64(tc, MMU::S1E2Tran, BaseMMU::Read, 0, val);
      case MISCREG_AT_S1E2W_Xt:
        return addressTranslation64(tc, MMU::S1E2Tran, BaseMMU::Write, 0, val);
      case MISCREG_AT_S12E1R_Xt:
        return addressTranslation64(tc, MMU::S12E1Tran, BaseMMU::Read, 0, val);
      case MISCREG_AT_S12E1W_Xt:
        return addressTranslation64(tc, MMU::S12E1Tran, BaseMMU::Write,
            0, val);
      case MISCREG_AT_S12E0R_Xt:
        return addressTranslation64(tc, MMU::S12E0Tran, BaseMMU::Read,
            MMU::UserMode, val);
      case MISCREG_AT_S12E0W_Xt:
        return addressTranslation64(tc, MMU::S12E0Tran, BaseMMU::Write,
            MMU::UserMode, val);
      case MISCREG_AT_S1E3R_Xt:
        return addressTranslation64(tc, MMU::S1E3Tran, BaseMMU::Read, 0, val);
      case MISCREG_AT_S1E3W_Xt:
        return addressTranslation64(tc, MMU::S1E3Tran, BaseMMU::Write, 0, val);
      default:
        return std::make_pair(NoFault, 0);
    }
 
    return std::make_pair(NoFault, 0);
}
 
std::pair<Fault, uint64_t>
AtOp64::addressTranslation64(ThreadContext* tc,
    ArmISA::MMU::ArmTranslationType tran_type,
    BaseMMU::Mode mode, Request::Flags flags, RegVal val) const
{
    // If we're in timing mode then doing the translation in
    // functional mode then we're slightly distorting performance
    // results obtained from simulations. The translation should be
    // done in the same mode the core is running in. NOTE: This
    // can't be an atomic translation because that causes problems
    // with unexpected atomic snoop requests.
    warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
 
    auto req = std::make_shared<Request>(
        val, 0, flags,  Request::funcRequestorId,
        tc->pcState().instAddr(), tc->contextId());
 
    Fault fault = getMMUPtr(tc)->translateFunctional(
        req, tc, mode, tran_type);
 
    PAR par = 0;
    bool raise_fault = false;
    if (fault == NoFault) {
        Addr paddr = req->getPaddr();
        uint64_t attr = getMMUPtr(tc)->getAttr();
        // clear LAPE bit from attribute.
        attr &= ~ uint64_t(0x800);
        uint64_t attr1 = attr >> 56;
        if (!(attr1 >> 4) || attr1 == 0x44) {
            attr |= 0x100;
            attr &= ~ uint64_t(0x80);
        }
        par = (paddr & mask(47, 12)) | attr;
        DPRINTF(MiscRegs, "AT: Translated addr %#x: PAR_EL1: %#x\n",
                val, par);
    } else {
        ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
        arm_fault->update(tc);
        // Set fault bit and FSR
        FSR fsr = arm_fault->getFsr(tc);
 
        arm_fault->annotate(ArmFault::CM, 1);   // CM
        arm_fault->annotate(ArmFault::WnR, 1);  // Force WnR as 1
 
        par.f = 1; // F bit
        par.fst = fsr.status; // FST
        par.ptw = (arm_fault->iss() >> 7) & 0x1; // S1PTW
        par.s = arm_fault->isStage2() ? 1 : 0; // S
        // set RES1 bit [11].
        par |= 0x800;
 
        // Only raise fault for external abort and stage 2 fault,
        // see R~NHWXL~ in Arm-ARM.
        raise_fault = arm_fault->isExternalAbort() || par.ptw;
 
        DPRINTF(MiscRegs, "AT: Translated addr %#x fault fsr %#x: PAR: %#x\n",
                val, fsr, par);
    }
 
    // Fault filter.
    if (fault != NoFault && !raise_fault) {
        fault = NoFault;
    }
 
    return std::make_pair(fault, par);
}
 
} // namespace gem5