gem5  v21.1.0.2
misc64.cc
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1 /*
2  * Copyright (c) 2011-2013,2017-2020 ARM Limited
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4  *
5  * The license below extends only to copyright in the software and shall
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23  * this software without specific prior written permission.
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25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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36  */
37 
38 #include "arch/arm/insts/misc64.hh"
39 #include "arch/arm/isa.hh"
40 
41 namespace gem5
42 {
43 
44 using namespace ArmISA;
45 
46 std::string
48 {
49  std::stringstream ss;
50  printMnemonic(ss, "", false);
51  ccprintf(ss, "#0x%x", imm);
52  return ss.str();
53 }
54 
55 std::string
57  Addr pc, const loader::SymbolTable *symtab) const
58 {
59  std::stringstream ss;
60  printMnemonic(ss, "", false);
61  printIntReg(ss, dest);
62  ss << ", ";
63  printIntReg(ss, op1);
64  ccprintf(ss, ", #%d, #%d", imm1, imm2);
65  return ss.str();
66 }
67 
68 std::string
70  Addr pc, const loader::SymbolTable *symtab) const
71 {
72  std::stringstream ss;
73  printMnemonic(ss, "", false);
74  printIntReg(ss, dest);
75  ss << ", ";
76  printIntReg(ss, op1);
77  ss << ", ";
78  printIntReg(ss, op2);
79  ccprintf(ss, ", #%d", imm);
80  return ss.str();
81 }
82 
83 std::string
85  Addr pc, const loader::SymbolTable *symtab) const
86 {
87  return csprintf("%-10s (inst %#08x)", "unknown", encoding());
88 }
89 
90 Fault
92  ExceptionLevel el, uint32_t immediate) const
93 {
95 
96  // Check for traps to supervisor (FP/SIMD regs)
97  if (el <= EL1 && checkEL1Trap(tc, misc_reg, el, ec, immediate)) {
98  return std::make_shared<SupervisorTrap>(machInst, immediate, ec);
99  }
100 
101  // Check for traps to hypervisor
102  if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
103  checkEL2Trap(tc, misc_reg, el, ec, immediate)) {
104  return std::make_shared<HypervisorTrap>(machInst, immediate, ec);
105  }
106 
107  // Check for traps to secure monitor
108  if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
109  checkEL3Trap(tc, misc_reg, el, ec, immediate)) {
110  return std::make_shared<SecureMonitorTrap>(machInst, immediate, ec);
111  }
112 
113  return NoFault;
114 }
115 
116 bool
119  uint32_t &immediate) const
120 {
121  const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
122  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
123  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
124  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
125 
126  bool trap_to_sup = false;
127  switch (misc_reg) {
128  case MISCREG_DAIF:
129  trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0;
130  trap_to_sup = trap_to_sup ||
131  (el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma);
132  break;
133  case MISCREG_DC_ZVA_Xt:
134  // In syscall-emulation mode, this test is skipped and DCZVA is always
135  // allowed at EL0
136  trap_to_sup = el == EL0 && !sctlr.dze && FullSystem;
137  break;
138  case MISCREG_DC_CIVAC_Xt:
139  case MISCREG_DC_CVAC_Xt:
140  trap_to_sup = el == EL0 && !sctlr.uci;
141  break;
142  case MISCREG_FPCR:
143  case MISCREG_FPSR:
144  case MISCREG_FPEXC32_EL2:
145  if ((el == EL0 && cpacr.fpen != 0x3) ||
146  (el == EL1 && !(cpacr.fpen & 0x1))) {
147  trap_to_sup = true;
149  immediate = 0x1E00000;
150  }
151  break;
152  case MISCREG_DC_CVAU_Xt:
153  trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
154  el == EL0;
155  break;
156  case MISCREG_CTR_EL0:
157  trap_to_sup = el == EL0 && !sctlr.uct &&
158  (!hcr.tge || (!scr.ns && !scr.eel2));
159  break;
160  case MISCREG_MDCCSR_EL0:
161  {
162  DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
163  trap_to_sup = el == EL0 && mdscr.tdcc &&
164  (hcr.tge == 0x0 || ( scr.ns == 0x0));
165  }
166  break;
167  case MISCREG_ZCR_EL1:
168  trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0);
169  break;
170  // Generic Timer
172  trap_to_sup = el == EL0 &&
173  isGenericTimerSystemAccessTrapEL1(misc_reg, tc);
174  break;
175  default:
176  break;
177  }
178  return trap_to_sup;
179 }
180 
181 bool
184  uint32_t &immediate) const
185 {
186  const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
187  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
188  const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
189  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
190  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
191  const HDCR mdcr = tc->readMiscReg(MISCREG_MDCR_EL3);
192 
193  bool trap_to_hyp = false;
194 
195  switch (misc_reg) {
197  trap_to_hyp = EL2Enabled(tc) && hcr.tidcp && el == EL1;
198  break;
199  // GICv3 regs
201  {
202  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
203  if (isa->haveGICv3CpuIfc())
204  trap_to_hyp = EL2Enabled(tc) && hcr.fmo && el == EL1;
205  }
206  break;
209  {
210  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
211  if (isa->haveGICv3CpuIfc())
212  trap_to_hyp = EL2Enabled(tc) && hcr.imo && el == EL1;
213  }
214  break;
215  case MISCREG_FPCR:
216  case MISCREG_FPSR:
217  case MISCREG_FPEXC32_EL2:
218  {
219  bool from_el2 = (el == EL2) && (scr.ns || scr.eel2) &&
220  ELIs64(tc,EL2) &&
221  ((!hcr.e2h && cptr.tfp) ||
222  (hcr.e2h && (cptr.fpen == 0x0 ||
223  cptr.fpen == 0xa)));
224  bool from_el1 = (el == EL1) && hcr.nv &&
225  (!hcr.e2h || (hcr.e2h && !hcr.tge));
226  trap_to_hyp = from_el2 || from_el1;
228  immediate = 0x1E00000;
229  }
230  break;
231  case MISCREG_CPACR_EL1:
232  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && cptr.tcpac;
233  break;
234  case MISCREG_SCTLR_EL1:
235  case MISCREG_TTBR0_EL1:
236  case MISCREG_TTBR1_EL1:
237  case MISCREG_TCR_EL1:
238  case MISCREG_ESR_EL1:
239  case MISCREG_FAR_EL1:
240  case MISCREG_AFSR0_EL1:
241  case MISCREG_AFSR1_EL1:
242  case MISCREG_MAIR_EL1:
243  case MISCREG_AMAIR_EL1:
245  {
246  bool tvm = miscRead? hcr.trvm: hcr.tvm;
247  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && tvm;
248  }
249  break;
250  case MISCREG_CPACR_EL12:
251  case MISCREG_SCTLR_EL12:
252  case MISCREG_TTBR0_EL12:
253  case MISCREG_TTBR1_EL12:
254  case MISCREG_TCR_EL12:
255  case MISCREG_ESR_EL12:
256  case MISCREG_FAR_EL12:
257  case MISCREG_AFSR0_EL12:
258  case MISCREG_AFSR1_EL12:
259  case MISCREG_MAIR_EL12:
260  case MISCREG_AMAIR_EL12:
262  case MISCREG_SPSR_EL12:
263  case MISCREG_ELR_EL12:
264  case MISCREG_VBAR_EL12:
265  trap_to_hyp = EL2Enabled(tc) && (el == EL1) &&
266  (hcr.nv && (hcr.nv1 || !hcr.nv2));
267  break;
274 // case MISCREG_TLBI_RVAE1:
275 // case MISCREG_TLBI_RVAAE1:
276 // case MISCREG_TLBI_RVALE1:
277 // case MISCREG_TLBI_RVAALE1:
284 // case MISCREG_TLBI_RVAE1IS:
285 // case MISCREG_TLBI_RVAAE1IS:
286 // case MISCREG_TLBI_RVALE1IS:
287 // case MISCREG_TLBI_RVAALE1IS:
288 // case MISCREG_TLBI_VMALLE1OS:
289 // case MISCREG_TLBI_VAE1OS:
290 // case MISCREG_TLBI_ASIDE1OS:
291 // case MISCREG_TLBI_VAAE1OS:
292 // case MISCREG_TLBI_VALE1OS:
293 // case MISCREG_TLBI_VAALE1OS:
294 // case MISCREG_TLBI_RVAE1OS:
295 // case MISCREG_TLBI_RVAAE1OS:
296 // case MISCREG_TLBI_RVALE1OS:
297 // case MISCREG_TLBI_RVAALE1OS:
298  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.ttlb;
299  break;
300  case MISCREG_IC_IVAU_Xt:
301  case MISCREG_ICIALLU:
302  case MISCREG_ICIALLUIS:
303  trap_to_hyp = (el == EL1) && EL2Enabled(tc) && hcr.tpu;
304  break;
305  case MISCREG_DC_CVAU_Xt:
306  {
307  const bool el2_en = EL2Enabled(tc);
308  if (el == EL0 && el2_en) {
309  const bool in_host = hcr.e2h && hcr.tge;
310  const bool general_trap = el2_en && !in_host && hcr.tge &&
311  !sctlr.uci;
312  const bool tpu_trap = el2_en && !in_host && hcr.tpu;
313  const bool host_trap = el2_en && in_host && !sctlr2.uci;
314  trap_to_hyp = general_trap || tpu_trap || host_trap;
315  }
316  else if (el == EL1 && el2_en) {
317  trap_to_hyp = hcr.tpu;
318  }
319  }
320  break;
321  case MISCREG_DC_IVAC_Xt:
322  trap_to_hyp = EL2Enabled(tc) && el == EL1 && hcr.tpc;
323  break;
324  case MISCREG_DC_CVAC_Xt:
325 // case MISCREG_DC_CVAP_Xt:
326  case MISCREG_DC_CIVAC_Xt:
327  {
328  const bool el2_en = EL2Enabled(tc);
329  if (el == EL0 && el2_en) {
330 
331  const bool in_host = hcr.e2h && hcr.tge;
332  const bool general_trap = el2_en && !in_host && hcr.tge &&
333  !sctlr.uci;
334  const bool tpc_trap = el2_en && !in_host && hcr.tpc;
335  const bool host_trap = el2_en && in_host && !sctlr2.uci;
336  trap_to_hyp = general_trap || tpc_trap || host_trap;
337  } else if (el == EL1 && el2_en) {
338  trap_to_hyp = hcr.tpc;
339  }
340  }
341  break;
342  case MISCREG_DC_ISW_Xt:
343  case MISCREG_DC_CSW_Xt:
344  case MISCREG_DC_CISW_Xt:
345  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.tsw;
346  break;
347  case MISCREG_ACTLR_EL1:
348  trap_to_hyp = EL2Enabled (tc) && (el == EL1) && hcr.tacr;
349  break;
360  trap_to_hyp = EL2Enabled(tc) && el == EL1 && !hcr.apk;
361  break;
362  case MISCREG_ID_PFR0_EL1:
363  case MISCREG_ID_PFR1_EL1:
364  //case MISCREG_ID_PFR2_EL1:
365  case MISCREG_ID_DFR0_EL1:
366  case MISCREG_ID_AFR0_EL1:
379  case MISCREG_MVFR0_EL1:
380  case MISCREG_MVFR1_EL1:
381  case MISCREG_MVFR2_EL1:
393  trap_to_hyp = EL2Enabled(tc) && el == EL1 && hcr.tid3;
394  break;
395  case MISCREG_CTR_EL0:
396  {
397  const bool el2_en = EL2Enabled(tc);
398  if (el == EL0 && el2_en) {
399  const bool in_host = hcr.e2h && hcr.tge;
400  const bool general_trap = el2_en && !in_host && hcr.tge &&
401  !sctlr.uct;
402  const bool tid_trap = el2_en && !in_host && hcr.tid2;
403  const bool host_trap = el2_en && in_host && !sctlr2.uct;
404  trap_to_hyp = general_trap || tid_trap || host_trap;
405  } else if (el == EL1 && el2_en) {
406  trap_to_hyp = hcr.tid2;
407  }
408  }
409  break;
410  case MISCREG_CCSIDR_EL1:
411 // case MISCREG_CCSIDR2_EL1:
412  case MISCREG_CLIDR_EL1:
413  case MISCREG_CSSELR_EL1:
414  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.tid2;
415  break;
416  case MISCREG_AIDR_EL1:
417  case MISCREG_REVIDR_EL1:
418  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.tid1;
419  break;
420  // Generic Timer
422  trap_to_hyp = el <= EL1 &&
423  isGenericTimerSystemAccessTrapEL2(misc_reg, tc);
424  break;
425  case MISCREG_DAIF:
426  trap_to_hyp = EL2Enabled(tc) && el == EL0 &&
427  (hcr.tge && (hcr.e2h || !sctlr.uma));
428  break;
429  case MISCREG_SPSR_EL1:
430  case MISCREG_ELR_EL1:
431  case MISCREG_VBAR_EL1:
432  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv1 && !hcr.nv2;
433  break;
434  case MISCREG_HCR_EL2:
435  case MISCREG_HSTR_EL2:
436  case MISCREG_SP_EL1:
437  case MISCREG_TPIDR_EL2:
438  case MISCREG_VTCR_EL2:
439  case MISCREG_VTTBR_EL2:
440  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv && !hcr.nv2;
441  break;
442 // case MISCREG_AT_S1E1WP_Xt:
443 // case MISCREG_AT_S1E1RP_Xt:
444  case MISCREG_AT_S1E1R_Xt:
445  case MISCREG_AT_S1E1W_Xt:
446  case MISCREG_AT_S1E0W_Xt:
447  case MISCREG_AT_S1E0R_Xt:
448  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.at;
449  break;
450  case MISCREG_ACTLR_EL2:
451  case MISCREG_AFSR0_EL2:
452  case MISCREG_AFSR1_EL2:
453  case MISCREG_AMAIR_EL2:
455  case MISCREG_CPTR_EL2:
456  case MISCREG_DACR32_EL2:
457  case MISCREG_ESR_EL2:
458  case MISCREG_FAR_EL2:
459  case MISCREG_HACR_EL2:
460  case MISCREG_HPFAR_EL2:
461  case MISCREG_MAIR_EL2:
462 // case MISCREG_RMR_EL2:
463  case MISCREG_SCTLR_EL2:
464  case MISCREG_TCR_EL2:
465  case MISCREG_TTBR0_EL2:
466  case MISCREG_TTBR1_EL2:
467  case MISCREG_VBAR_EL2:
468  case MISCREG_VMPIDR_EL2:
469  case MISCREG_VPIDR_EL2:
470  case MISCREG_TLBI_ALLE1:
472 // case MISCREG_TLBI_ALLE1OS:
473  case MISCREG_TLBI_ALLE2:
475 // case MISCREG_TLBI_ALLE2OS:
478 // case MISCREG_TLBI_IPAS2E1OS:
481 // case MISCREG_TLBI_IPAS2LE1OS:
482 // case MISCREG_TLBI_RIPAS2E1:
483 // case MISCREG_TLBI_RIPAS2E1IS:
484 // case MISCREG_TLBI_RIPAS2E1OS:
485 // case MISCREG_TLBI_RIPAS2LE1:
486 // case MISCREG_TLBI_RIPAS2LE1IS:
487 // case MISCREG_TLBI_RIPAS2LE1OS:
488 // case MISCREG_TLBI_RVAE2:
489 // case MISCREG_TLBI_RVAE2IS:
490 // case MISCREG_TLBI_RVAE2OS:
491 // case MISCREG_TLBI_RVALE2:
492 // case MISCREG_TLBI_RVALE2IS:
493 // case MISCREG_TLBI_RVALE2OS:
496 // case MISCREG_TLBI_VAE2OS:
499 // case MISCREG_TLBI_VALE2OS:
502 // case MISCREG_TLBI_VMALLS12E1OS:
503  case MISCREG_AT_S1E2W_Xt:
504  case MISCREG_AT_S1E2R_Xt:
509  case MISCREG_SPSR_UND:
510  case MISCREG_SPSR_IRQ:
511  case MISCREG_SPSR_FIQ:
512  case MISCREG_SPSR_ABT:
513  case MISCREG_SPSR_EL2:
514  case MISCREG_ELR_EL2:
515  case MISCREG_IFSR32_EL2:
517  case MISCREG_MDCR_EL2:
518  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv;
519  break;
520 // case MISCREG_VSTTBR_EL2:
521 // case MISCREG_VSTCR_EL2:
522 // trap_to_hyp = (el == EL1) && !scr.ns && scr.eel2 && ELIs64(tc,EL2)
523 // && !hcr.nv2 && hcr.nv && (!hcr.e2h|| (hcr.e2h && !hcr.tge));
524 // break;
525 
526  //case MISCREG_LORC_EL1:
527  //case MISCREG_LOREA_EL1:
528  //case MISCREG_LORID_EL1:
529  //case MISCREG_LORN_EL1:
530  //case MISCREG_LORSA_EL1:
531  // trap_to_hyp = (el == EL1) && (scr.ns || scr.eel2) && ELIs64(tc,EL2)
532  // && hcr.tlor && (!hcr.e2h || (hcr.e2h && !hcr.tge));
533  // break;
534 
535  case MISCREG_DC_ZVA_Xt:
536  {
537  const bool el2_en = EL2Enabled(tc);
538  if (el == EL0 && el2_en) {
539  const bool in_host = hcr.e2h && hcr.tge;
540  const bool general_trap = el2_en && !in_host && hcr.tge &&
541  !sctlr.dze;
542  const bool tdz_trap = el2_en && !in_host && hcr.tdz;
543  const bool host_trap = el2_en && in_host && !sctlr2.dze;
544  trap_to_hyp = general_trap || tdz_trap || host_trap;
545  } else if (el == EL1 && el2_en) {
546  trap_to_hyp = hcr.tdz;
547  }
548  }
549  break;
550  case MISCREG_DBGBVR0_EL1:
551  case MISCREG_DBGBVR1_EL1:
552  case MISCREG_DBGBVR2_EL1:
553  case MISCREG_DBGBVR3_EL1:
554  case MISCREG_DBGBVR4_EL1:
555  case MISCREG_DBGBVR5_EL1:
556  case MISCREG_DBGBVR6_EL1:
557  case MISCREG_DBGBVR7_EL1:
558  case MISCREG_DBGBVR8_EL1:
559  case MISCREG_DBGBVR9_EL1:
566  case MISCREG_DBGBCR0_EL1:
567  case MISCREG_DBGBCR1_EL1:
568  case MISCREG_DBGBCR2_EL1:
569  case MISCREG_DBGBCR3_EL1:
570  case MISCREG_DBGBCR4_EL1:
571  case MISCREG_DBGBCR5_EL1:
572  case MISCREG_DBGBCR6_EL1:
573  case MISCREG_DBGBCR7_EL1:
574  case MISCREG_DBGBCR8_EL1:
575  case MISCREG_DBGBCR9_EL1:
582  case MISCREG_DBGWVR0_EL1:
583  case MISCREG_DBGWVR1_EL1:
584  case MISCREG_DBGWVR2_EL1:
585  case MISCREG_DBGWVR3_EL1:
586  case MISCREG_DBGWVR4_EL1:
587  case MISCREG_DBGWVR5_EL1:
588  case MISCREG_DBGWVR6_EL1:
589  case MISCREG_DBGWVR7_EL1:
590  case MISCREG_DBGWVR8_EL1:
591  case MISCREG_DBGWVR9_EL1:
598  case MISCREG_DBGWCR0_EL1:
599  case MISCREG_DBGWCR1_EL1:
600  case MISCREG_DBGWCR2_EL1:
601  case MISCREG_DBGWCR3_EL1:
602  case MISCREG_DBGWCR4_EL1:
603  case MISCREG_DBGWCR5_EL1:
604  case MISCREG_DBGWCR6_EL1:
605  case MISCREG_DBGWCR7_EL1:
606  case MISCREG_DBGWCR8_EL1:
607  case MISCREG_DBGWCR9_EL1:
614  case MISCREG_MDCCINT_EL1:
615  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && mdcr.tda;
616  break;
617  case MISCREG_ZCR_EL1:
618  {
619  bool from_el1 = (el == EL1) && EL2Enabled(tc) &&
620  ELIs64(tc, EL2) && ((!hcr.e2h && cptr.tz) ||
621  (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
622  bool from_el2 = (el == EL2) && ((!hcr.e2h && cptr.tz) ||
623  (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
624  trap_to_hyp = from_el1 || from_el2;
625  }
626  ec = EC_TRAPPED_SVE;
627  immediate = 0;
628  break;
629  case MISCREG_ZCR_EL2:
630  {
631  bool from_el1 = (el == EL1) && EL2Enabled(tc) && hcr.nv;
632  bool from_el2 = (el == EL2) && ((!hcr.e2h && cptr.tz) ||
633  (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
634  trap_to_hyp = from_el1 || from_el2;
636  }
637  immediate = 0;
638  break;
639  default:
640  break;
641  }
642  return trap_to_hyp;
643 }
644 
645 bool
646 MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
648  uint32_t &immediate) const
649 {
650  const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3);
651  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
652  const HDCR mdcr = tc->readMiscReg(MISCREG_MDCR_EL3);
653  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
654  bool trap_to_mon = false;
655 
656  switch (misc_reg) {
657  // FP/SIMD regs
658  case MISCREG_FPCR:
659  case MISCREG_FPSR:
660  case MISCREG_FPEXC32_EL2:
661  trap_to_mon = cptr.tfp && ELIs64(tc, EL3);
663  immediate = 0x1E00000;
664  break;
665  // CPACR, CPTR
666  case MISCREG_CPACR_EL12:
667  trap_to_mon = ((el == EL2 && cptr.tcpac && ELIs64(tc, EL3)) ||
668  (el == EL1 && cptr.tcpac && ELIs64(tc, EL3) &&
669  (!hcr.nv2 || hcr.nv1 || !hcr.nv))) ;
670  break;
671  case MISCREG_CPACR_EL1:
672  trap_to_mon = el <= EL2 && cptr.tcpac && ELIs64(tc, EL3);
673  break;
674  case MISCREG_CPTR_EL2:
675  if (el == EL2) {
676  trap_to_mon = cptr.tcpac;
677  }
678  break;
679 // case MISCREG_LORC_EL1:
680 // case MISCREG_LOREA_EL1:
681 // case MISCREG_LORID_EL1:
682 // case MISCREG_LORN_EL1:
683 // case MISCREG_LORSA_EL1:
684 // trap_to_mon = (el <= EL2) && scr.ns && ELIs64(tc,EL3)
685 // && hcr.tlor && (!hcr.e2h || (hcr.e2h && !hcr.tge));
686 // break;
687  case MISCREG_MDCCSR_EL0:
688  trap_to_mon = (el <= EL2) && ELIs64(tc, EL3) && mdcr.tda == 0x1;
689  break;
700  trap_to_mon = (el == EL1 || el == EL2) && scr.apk == 0 &&
701  ELIs64(tc, EL3);
702  break;
703  // Generic Timer
705  trap_to_mon = el == EL1 &&
706  isGenericTimerSystemAccessTrapEL3(misc_reg, tc);
707  break;
708  case MISCREG_DBGBVR0_EL1:
709  case MISCREG_DBGBVR1_EL1:
710  case MISCREG_DBGBVR2_EL1:
711  case MISCREG_DBGBVR3_EL1:
712  case MISCREG_DBGBVR4_EL1:
713  case MISCREG_DBGBVR5_EL1:
714  case MISCREG_DBGBVR6_EL1:
715  case MISCREG_DBGBVR7_EL1:
716  case MISCREG_DBGBVR8_EL1:
717  case MISCREG_DBGBVR9_EL1:
724  case MISCREG_DBGBCR0_EL1:
725  case MISCREG_DBGBCR1_EL1:
726  case MISCREG_DBGBCR2_EL1:
727  case MISCREG_DBGBCR3_EL1:
728  case MISCREG_DBGBCR4_EL1:
729  case MISCREG_DBGBCR5_EL1:
730  case MISCREG_DBGBCR6_EL1:
731  case MISCREG_DBGBCR7_EL1:
732  case MISCREG_DBGBCR8_EL1:
733  case MISCREG_DBGBCR9_EL1:
741  case MISCREG_DBGWVR0_EL1:
742  case MISCREG_DBGWVR1_EL1:
743  case MISCREG_DBGWVR2_EL1:
744  case MISCREG_DBGWVR3_EL1:
745  case MISCREG_DBGWVR4_EL1:
746  case MISCREG_DBGWVR5_EL1:
747  case MISCREG_DBGWVR6_EL1:
748  case MISCREG_DBGWVR7_EL1:
749  case MISCREG_DBGWVR8_EL1:
750  case MISCREG_DBGWVR9_EL1:
757  case MISCREG_DBGWCR0_EL1:
758  case MISCREG_DBGWCR1_EL1:
759  case MISCREG_DBGWCR2_EL1:
760  case MISCREG_DBGWCR3_EL1:
761  case MISCREG_DBGWCR4_EL1:
762  case MISCREG_DBGWCR5_EL1:
763  case MISCREG_DBGWCR6_EL1:
764  case MISCREG_DBGWCR7_EL1:
765  case MISCREG_DBGWCR8_EL1:
766  case MISCREG_DBGWCR9_EL1:
773  case MISCREG_MDCCINT_EL1:
774  case MISCREG_MDCR_EL2:
775  trap_to_mon = ELIs64(tc, EL3) && mdcr.tda && (el == EL2);
776  break;
777  case MISCREG_ZCR_EL1:
778  trap_to_mon = !cptr.ez && ((el == EL3) ||
779  ((el <= EL2) && ArmSystem::haveEL(tc,EL3) && ELIs64(tc, EL3)));
780  ec = EC_TRAPPED_SVE;
781  immediate = 0;
782  break;
783  case MISCREG_ZCR_EL2:
784  trap_to_mon = !cptr.ez && ((el == EL3) ||
785  ((el == EL2) && ArmSystem::haveEL(tc,EL3) && ELIs64(tc, EL3)));
786  ec = EC_TRAPPED_SVE;
787  immediate = 0;
788  break;
789  case MISCREG_ZCR_EL3:
790  trap_to_mon = !cptr.ez && (el == EL3);
791  ec = EC_TRAPPED_SVE;
792  immediate = 0;
793  break;
794  default:
795  break;
796  }
797  return trap_to_mon;
798 }
799 
800 RegVal
801 MiscRegImmOp64::miscRegImm() const
802 {
803  if (dest == MISCREG_SPSEL) {
804  return imm & 0x1;
805  } else if (dest == MISCREG_PAN) {
806  return (imm & 0x1) << 22;
807  } else {
808  panic("Not a valid PSTATE field register\n");
809  }
810 }
811 
812 std::string
813 MiscRegImmOp64::generateDisassembly(
814  Addr pc, const loader::SymbolTable *symtab) const
815 {
816  std::stringstream ss;
817  printMnemonic(ss);
818  printMiscReg(ss, dest);
819  ss << ", ";
820  ccprintf(ss, "#0x%x", imm);
821  return ss.str();
822 }
823 
824 std::string
825 MiscRegRegImmOp64::generateDisassembly(
826  Addr pc, const loader::SymbolTable *symtab) const
827 {
828  std::stringstream ss;
829  printMnemonic(ss);
830  printMiscReg(ss, dest);
831  ss << ", ";
832  printIntReg(ss, op1);
833  return ss.str();
834 }
835 
836 std::string
837 RegMiscRegImmOp64::generateDisassembly(
838  Addr pc, const loader::SymbolTable *symtab) const
839 {
840  std::stringstream ss;
841  printMnemonic(ss);
842  printIntReg(ss, dest);
843  ss << ", ";
844  printMiscReg(ss, op1);
845  return ss.str();
846 }
847 
848 Fault
849 MiscRegImplDefined64::execute(ExecContext *xc,
850  Trace::InstRecord *traceData) const
851 {
852  auto tc = xc->tcBase();
853  const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
854  const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
855 
856  Fault fault = trap(tc, miscReg, el, imm);
857 
858  if (fault != NoFault) {
859  return fault;
860 
861  } else if (warning) {
862  warn_once("\tinstruction '%s' unimplemented\n", fullMnemonic.c_str());
863  return NoFault;
864 
865  } else {
866  return std::make_shared<UndefinedInstruction>(machInst, false,
867  mnemonic);
868  }
869 }
870 
871 std::string
872 MiscRegImplDefined64::generateDisassembly(
873  Addr pc, const loader::SymbolTable *symtab) const
874 {
875  return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
876 }
877 
878 std::string
879 RegNone::generateDisassembly(
880  Addr pc, const loader::SymbolTable *symtab) const
881 {
882  std::stringstream ss;
883  printMnemonic(ss);
884  printIntReg(ss, dest);
885  return ss.str();
886 }
887 
888 } // namespace gem5
gem5::ArmISA::MISCREG_APDAKeyLo_EL1
@ MISCREG_APDAKeyLo_EL1
Definition: misc.hh:826
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: misc.hh:575
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:649
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:588
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: misc.hh:483
gem5::ArmISA::MISCREG_DBGWVR8_EL1
@ MISCREG_DBGWVR8_EL1
Definition: misc.hh:498
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:603
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: misc.hh:728
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:674
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::MISCREG_AMAIR_EL12
@ MISCREG_AMAIR_EL12
Definition: misc.hh:729
gem5::MiscRegOp64::checkEL1Trap
bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:117
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:282
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:596
gem5::ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition: misc.hh:491
gem5::ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition: misc.hh:664
gem5::MiscRegOp64::checkEL2Trap
bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:182
gem5::ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition: misc.hh:669
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:681
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: misc.hh:520
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: misc.hh:297
gem5::ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition: misc.hh:590
gem5::ArmISA::MISCREG_IFSR32_EL2
@ MISCREG_IFSR32_EL2
Definition: misc.hh:641
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:509
gem5::ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition: misc.hh:549
gem5::ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:701
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:675
gem5::ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition: misc.hh:577
gem5::ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition: misc.hh:573
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:477
gem5::ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition: misc.hh:552
gem5::ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition: misc.hh:667
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: misc.hh:489
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::MISCREG_FAR_EL12
@ MISCREG_FAR_EL12
Definition: misc.hh:650
gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:690
warn_once
#define warn_once(...)
Definition: logging.hh:249
gem5::ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition: misc.hh:589
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:475
gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:687
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::MISCREG_APDAKeyHi_EL1
@ MISCREG_APDAKeyHi_EL1
Definition: misc.hh:825
gem5::ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition: misc.hh:666
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:518
gem5::ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition: misc.hh:663
gem5::ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition: misc.hh:556
gem5::ArmISA::MISCREG_DBGWVR14_EL1
@ MISCREG_DBGWVR14_EL1
Definition: misc.hh:504
gem5::ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition: misc.hh:493
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:691
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: misc.hh:620
gem5::ArmISA::MISCREG_APDBKeyLo_EL1
@ MISCREG_APDBKeyLo_EL1
Definition: misc.hh:828
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:599
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:740
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:696
gem5::ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:702
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: misc.hh:643
gem5::ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition: misc.hh:546
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:644
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:662
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:515
gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: misc.hh:695
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:516
gem5::ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition: misc.hh:503
gem5::ArmISA::MISCREG_APIAKeyLo_EL1
@ MISCREG_APIAKeyLo_EL1
Definition: misc.hh:832
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:482
gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: misc.hh:682
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:745
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:566
gem5::ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition: misc.hh:459
gem5::ArmISA::MISCREG_ICC_SGI1R_EL1
@ MISCREG_ICC_SGI1R_EL1
Definition: misc.hh:860
gem5::ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition: misc.hh:553
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition: misc.hh:554
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:487
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition: misc.hh:555
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:486
gem5::ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition: misc.hh:501
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: misc.hh:726
gem5::ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: misc.hh:688
gem5::ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition: misc.hh:615
gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:679
gem5::ArmISA::encoding
Bitfield< 27, 25 > encoding
Definition: types.hh:90
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:564
gem5::ImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:47
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:511
gem5::ArmISA::MISCREG_DBGBVR15_EL1
@ MISCREG_DBGBVR15_EL1
Definition: misc.hh:473
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:703
gem5::ArmISA::isGenericTimerSystemAccessTrapEL3
bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1112
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:544
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:606
gem5::ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:700
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:512
gem5::ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition: misc.hh:543
gem5::ArmISA::MISCREG_DBGWVR9_EL1
@ MISCREG_DBGWVR9_EL1
Definition: misc.hh:499
gem5::ArmISA::ec
ec
Definition: misc_types.hh:669
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: misc.hh:730
gem5::ArmISA::MISCREG_APIBKeyHi_EL1
@ MISCREG_APIBKeyHi_EL1
Definition: misc.hh:833
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:458
gem5::ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition: misc.hh:600
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: misc.hh:521
gem5::ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition: misc.hh:542
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:614
misc64.hh
gem5::ArmISA::MISCREG_DBGBVR14_EL1
@ MISCREG_DBGBVR14_EL1
Definition: misc.hh:472
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition: misc.hh:463
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:562
gem5::ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition: misc.hh:580
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:508
gem5::ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition: misc.hh:583
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:822
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition: misc.hh:548
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:595
gem5::ArmISA::MISCREG_TCR_EL12
@ MISCREG_TCR_EL12
Definition: misc.hh:602
gem5::ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition: misc.hh:453
gem5::ArmISA::MISCREG_CONTEXTIDR_EL12
@ MISCREG_CONTEXTIDR_EL12
Definition: misc.hh:746
gem5::ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition: misc.hh:462
gem5::ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition: misc.hh:492
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition: misc.hh:541
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: misc.hh:731
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:660
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:565
isa.hh
gem5::ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition: misc.hh:468
gem5::ArmISA::EC_TRAPPED_MSR_MRS_64
@ EC_TRAPPED_MSR_MRS_64
Definition: types.hh:317
gem5::MiscRegOp64::trap
Fault trap(ThreadContext *tc, ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, uint32_t immediate) const
Definition: misc64.cc:91
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:510
gem5::ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition: misc.hh:490
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: misc.hh:292
gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1
@ MISCREG_ICC_ASGI1R_EL1
Definition: misc.hh:861
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:507
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:582
gem5::ArmISA::MISCREG_DBGVCR32_EL2
@ MISCREG_DBGVCR32_EL2
Definition: misc.hh:526
gem5::ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition: misc.hh:559
gem5::ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition: misc.hh:551
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:274
gem5::ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition: misc.hh:585
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: misc.hh:617
gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:680
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:625
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:665
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: misc.hh:627
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:661
gem5::ArmISA::MISCREG_ID_ISAR6_EL1
@ MISCREG_ID_ISAR6_EL1
Definition: misc.hh:557
gem5::ArmISA::MISCREG_APIBKeyLo_EL1
@ MISCREG_APIBKeyLo_EL1
Definition: misc.hh:834
gem5::ArmISA::MISCREG_APIAKeyHi_EL1
@ MISCREG_APIAKeyHi_EL1
Definition: misc.hh:831
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::RegRegRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:69
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:478
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition: misc.hh:460
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:563
gem5::ArmISA::MISCREG_APDBKeyHi_EL1
@ MISCREG_APDBKeyHi_EL1
Definition: misc.hh:827
gem5::ArmISA::isGenericTimerSystemAccessTrapEL1
bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:882
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:612
gem5::ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition: misc.hh:574
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_APGAKeyLo_EL1
@ MISCREG_APGAKeyLo_EL1
Definition: misc.hh:830
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:474
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
warning
const char * warning
Definition: remote_gdb.cc:200
gem5::ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition: misc.hh:560
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: misc.hh:642
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:672
gem5::ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition: misc.hh:638
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:568
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:671
gem5::ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition: misc.hh:750
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:293
gem5::ArmISA::MISCREG_DBGWVR12_EL1
@ MISCREG_DBGWVR12_EL1
Definition: misc.hh:502
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: misc.hh:698
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:481
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:479
gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: misc.hh:683
gem5::ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition: misc.hh:545
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: misc.hh:484
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:788
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:506
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:517
gem5::ArmISA::MISCREG_APGAKeyHi_EL1
@ MISCREG_APGAKeyHi_EL1
Definition: misc.hh:829
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition: misc.hh:467
gem5::ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: misc.hh:1093
gem5::ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition: misc.hh:497
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::MISCREG_ICC_SGI0R_EL1
@ MISCREG_ICC_SGI0R_EL1
Definition: misc.hh:862
gem5::ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: misc.hh:1058
gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: misc.hh:686
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: misc.hh:605
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:689
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:476
gem5::ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition: misc.hh:466
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:513
gem5::UnknownOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:84
gem5::ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:162
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition: misc.hh:547
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:626
gem5::ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition: misc.hh:494
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:578
gem5::ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition: misc.hh:727
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:480
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::MISCREG_DBGWVR15_EL1
@ MISCREG_DBGWVR15_EL1
Definition: misc.hh:505
gem5::ArmISA::EC_TRAPPED_SIMD_FP
@ EC_TRAPPED_SIMD_FP
Definition: types.hh:303
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:622
gem5::ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: misc.hh:1055
gem5::ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition: misc.hh:465
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: misc.hh:635
gem5::ArmISA::MISCREG_AFSR0_EL12
@ MISCREG_AFSR0_EL12
Definition: misc.hh:636
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:817
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:621
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition: misc.hh:657
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:753
gem5::ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition: misc.hh:668
gem5::ArmISA::MISCREG_DBGBVR6_EL1
@ MISCREG_DBGBVR6_EL1
Definition: misc.hh:464
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:673
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: misc.hh:637
gem5::ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:694
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:597
gem5::ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition: misc.hh:1077
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:485
gem5::ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: misc.hh:699
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: misc.hh:1056
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:651
gem5::ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:684
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:514
gem5::ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition: misc.hh:470
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: misc.hh:652
gem5::ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: misc.hh:685
gem5::ArmISA::MISCREG_FPEXC32_EL2
@ MISCREG_FPEXC32_EL2
Definition: misc.hh:645
gem5::ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition: misc.hh:598
gem5::ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition: misc.hh:581
gem5::ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition: misc.hh:571
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:639
gem5::ArmISA::MISCREG_DACR32_EL2
@ MISCREG_DACR32_EL2
Definition: misc.hh:611
gem5::ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: misc.hh:678
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:736
gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:697
gem5::ArmISA::EC_TRAPPED_SVE
@ EC_TRAPPED_SVE
Definition: types.hh:318
gem5::ArmISA::MISCREG_DBGWVR6_EL1
@ MISCREG_DBGWVR6_EL1
Definition: misc.hh:496
gem5::ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition: misc.hh:640
gem5::RegRegImmImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:56
gem5::ArmISA::MISCREG_ID_MMFR4_EL1
@ MISCREG_ID_MMFR4_EL1
Definition: misc.hh:550
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:455
gem5::ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition: misc.hh:500
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:488
gem5::ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition: misc.hh:737
gem5::ArmISA::isGenericTimerSystemAccessTrapEL2
bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:942
gem5::ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition: misc.hh:658
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:567
gem5::ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition: misc.hh:572
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:659
gem5::ArmISA::MISCREG_DBGBVR13_EL1
@ MISCREG_DBGBVR13_EL1
Definition: misc.hh:471
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:820
gem5::ArmISA::MISCREG_SPSR_EL12
@ MISCREG_SPSR_EL12
Definition: misc.hh:613
gem5::ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition: misc.hh:558
gem5::ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:171
gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:693
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:601
gem5::ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition: misc.hh:461
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:692
gem5::ArmISA::MISCREG_DBGBVR11_EL1
@ MISCREG_DBGBVR11_EL1
Definition: misc.hh:469
gem5::ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition: misc.hh:522
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:670
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:519
gem5::ArmISA::tvm
Bitfield< 26 > tvm
Definition: misc_types.hh:257
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition: misc.hh:495

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