55#include "debug/MSHR.hh"
64 downstreamPending(false),
65 pendingModified(false),
66 postInvalidate(false), postDowngrade(false),
67 wasWholeLineWrite(false), isForward(false),
68 targets(
name +
".targets"),
69 deferredTargets(
name +
".deferredTargets")
75 needsWritable(false), hasUpgrade(false),
76 allocOnFill(false), hasFromCache(false)
103 updateWriteFlags(pkt);
112 for (
auto&
t: *
this) {
113 updateFlags(
t.pkt,
t.source,
t.allocOnFill);
127 if (canMergeWrites) {
131 canMergeWrites =
false;
141 const auto &req_flags = pkt->
req->getFlags();
142 bool compat_write = !req_flags.isSet(no_merge_flags);
150 bool first_write = empty();
151 if (!masked_write && (first_write || compat_write)) {
153 auto begin = writesBitmap.begin() +
offset;
154 std::fill(begin, begin + pkt->
getSize(),
true);
159 canMergeWrites &= compat_write;
168 updateFlags(pkt, source, alloc_on_fill);
174 if (mshr !=
nullptr) {
183 emplace_back(pkt,
readyTime,
order, source, markPending, alloc_on_fill);
197 DPRINTF(
MSHR,
"Replacing UpgradeReq with ReadExReq\n");
200 DPRINTF(
MSHR,
"Replacing SCUpgradeReq with SCUpgradeFailReq\n");
203 DPRINTF(
MSHR,
"Replacing StoreCondReq with StoreCondFailReq\n");
227 for (
auto&
t : *
this) {
237 MSHR::TargetList::iterator end)
239 for (
auto t = begin;
t != end;
t++) {
240 if (
t->markedPending) {
247 MSHR *mshr =
t->pkt->findNextSenderState<
MSHR>();
248 if (mshr !=
nullptr) {
251 t->markedPending =
false;
266 for (
auto&
t : *
this) {
278 const std::string &prefix)
const
280 for (
auto&
t : *
this) {
290 s =
"FromPrefetcher";
297 t.pkt->print(
os, verbosity,
"");
305 Tick when_ready,
Counter _order,
bool alloc_on_fill)
326 targets.
add(target, when_ready, _order, source,
true, alloc_on_fill);
399 if (pkt->
req->isCacheMaintenance() ||
400 tgt_pkt->
req->isCacheMaintenance() ||
432 !pkt->
req->isCacheMaintenance(),
433 "%s got snoop %s where needsWritable, "
434 "does not match isInvalidate",
name(), pkt->
print());
499 new Packet(std::make_shared<Request>(*pkt->
req), pkt->
cmd,
561 ready_targets.push_back(*it);
571 ready_targets.push_back(*it);
580 ready_targets.push_back(*it);
593 return ready_targets;
610 return t.pkt->req->isCacheMaintenance();
672 return !
t.pkt->req->isCacheInvalidate() &&
673 !
t.pkt->needsWritable();
688 !def_tgt_pkt->
req->isCacheInvalidate()) {
701 return !
t.pkt->req->isCacheInvalidate();
731MSHR::print(std::ostream &
os,
int verbosity,
const std::string &prefix)
const
733 ccprintf(
os,
"%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s %s\n",
751 ccprintf(
os,
"%s Deferred Targets:\n", prefix);
759 std::ostringstream str;
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
virtual bool sendMSHRQueuePacket(MSHR *mshr)
Take an MSHR, turn it into a suitable downstream packet, and send it out.
void updateFlags(PacketPtr pkt, Target::Source source, bool alloc_on_fill)
Use the provided packet and the source to update the flags of this TargetList.
void replaceUpgrades()
Convert upgrades to the equivalent request if the cache line they refer to would have been invalid (U...
void populateFlags()
Goes through the list of targets and uses them to populate the flags of this TargetList.
bool trySatisfyFunctional(PacketPtr pkt)
bool isReset() const
Tests if the flags of this TargetList have their default values.
void add(PacketPtr pkt, Tick readyTime, Counter order, Target::Source source, bool markPending, bool alloc_on_fill)
Add the specified packet in the TargetList.
void print(std::ostream &os, int verbosity, const std::string &prefix) const
void updateWriteFlags(PacketPtr pkt)
Add the specified packet in the TargetList.
TargetList(const std::string &name=".unnamedTargetList")
void init(Addr blk_addr, Addr blk_size)
Reset state.
void clearDownstreamPending()
Miss Status and handling Register.
bool postInvalidate
Did we snoop an invalidate while waiting for data?
TargetList targets
List of all requests that match the address.
void clearDownstreamPending()
bool wasWholeLineWrite
Track if we sent this as a whole line write or not.
void updateLockedRMWReadTarget(PacketPtr pkt)
Replaces the matching packet in the Targets list with a dummy packet to ensure the MSHR remains alloc...
std::string print() const
A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overhea...
MSHR(const std::string &name)
A simple constructor.
void promoteIf(const std::function< bool(Target &)> &pred)
Promotes deferred targets that satisfy a predicate.
void markInService(bool pending_modified_resp)
bool downstreamPending
Flag set by downstream caches.
TargetList extractServiceableTargets(PacketPtr pkt)
Extracts the subset of the targets that can be serviced given a received response.
bool isPendingModified() const
bool postDowngrade
Did we snoop a read while waiting for data?
bool conflictAddr(const QueueEntry *entry) const override
Check if given entry's packets conflict with this' entries packets.
void promoteReadable()
Promotes deferred targets that do not require writable.
bool pendingModified
Here we use one flag to track both if:
void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter _order, bool alloc_on_fill)
Allocate a miss to this MSHR.
TargetList deferredTargets
bool sendPacket(BaseCache &cache) override
Send this queue entry as a downstream packet, with the exact behaviour depending on the specific entr...
bool trySatisfyFunctional(PacketPtr pkt)
bool hasPostDowngrade() const
bool matchBlockAddr(const Addr addr, const bool is_secure) const override
Check if entry corresponds to the one being looked for.
bool handleSnoop(PacketPtr target, Counter order)
bool needsWritable() const
The pending* and post* flags are only valid if inService is true.
bool isForward
True if the entry is just a simple forward from an upper level.
bool hasLockedRMWReadTarget()
Determine if there are any LockedRMWReads in the Targets list.
bool hasFromCache() const
Determine if there are non-deferred requests from other caches.
bool promoteDeferredTargets()
bool isWholeLineWrite() const
Check if this MSHR contains only compatible writes, and if they span the entire cache line.
void allocateTarget(PacketPtr target, Tick when, Counter order, bool alloc_on_fill)
Add a request to the list of targets.
void promoteWritable()
Promotes deferred targets that do not require writable.
bool hasPostInvalidate() const
void deallocate()
Mark this MSHR as free.
bool hasTargets() const
Returns true if there are targets left.
Interface for things with names.
virtual std::string name() const
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
bool needsWritable() const
void print(std::ostream &o, int verbosity=0, const std::string &prefix="") const
bool needsResponse() const
T * findNextSenderState() const
Go through the sender state stack and return the first instance that is of type T (as determined by a...
void setResponderHadWritable()
On responding to a snoop request (which only happens for Modified or Owned lines),...
Addr getOffset(unsigned int blk_size) const
bool trySatisfyFunctional(PacketPtr other)
Check a functional request against a memory value stored in another packet (i.e.
RequestPtr req
A pointer to the original request.
void setCacheResponding()
Snoop flags.
bool isExpressSnoop() const
void setHasSharers()
On fills, the hasSharers flag is used by the caches in combination with the cacheResponding flag,...
bool matchBlockAddr(const Addr addr, const bool is_secure, const int blk_size) const
Check if packet corresponds to a given block-aligned address and address space.
void setSatisfied()
Set when a request hits in a cache and the cache is not going to respond.
MemCmd cmd
The command field of the packet.
bool isMaskedWrite() const
bool isInvalidate() const
void allocate()
Allocate memory for the packet.
A queue entry base class, to be used by both the MSHRs and write-queue entries.
bool _isUncacheable
True if the entry is uncacheable.
unsigned blkSize
Block size of the cache.
virtual bool matchBlockAddr(const Addr addr, const bool is_secure) const =0
Check if entry corresponds to the one being looked for.
Addr blkAddr
Block aligned address.
Counter order
Order number assigned to disambiguate writes and misses.
bool inService
True if the entry has been sent downstream.
bool isSecure
True if the entry targets the secure memory space.
Tick readyTime
Tick when ready to issue.
@ SECURE
The request targets the secure memory space.
@ LOCKED_RMW
This request will lock or unlock the accessed memory.
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
@ UNCACHEABLE
The request is to an uncacheable address.
@ PRIVILEGED
This request is made in privileged mode.
@ MEM_SWAP
This request is for a memory swap.
@ LLSC
The request is a Load locked/store conditional.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Declares a basic cache interface BaseCache.
Miss Status and Handling Register (MSHR) declaration.
double Counter
All counters are of 64-bit values.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
std::shared_ptr< Request > RequestPtr
Tick curTick()
The universal simulation clock.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
uint64_t Tick
Tick count type.
static void replaceUpgrade(PacketPtr pkt)
void ccprintf(cp::Print &print)
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
const std::string & name()