gem5  v21.1.0.2
mem.cc
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29 
30 #include "arch/power/insts/mem.hh"
31 
32 #include "base/loader/symtab.hh"
33 
34 namespace gem5
35 {
36 
37 using namespace PowerISA;
38 
39 std::string
41 {
42  return csprintf("%-10s", mnemonic);
43 }
44 
45 
46 std::string
48  Addr pc, const loader::SymbolTable *symtab) const
49 {
50  std::stringstream ss;
51 
52  ccprintf(ss, "%-10s ", mnemonic);
53 
54  // Print the destination only for a load
55  if (!flags[IsStore]) {
56  if (_numDestRegs > 0) {
57 
58  // If the instruction updates the source register with the
59  // EA, then this source register is placed in position 0,
60  // therefore we print the last destination register.
62  }
63  }
64 
65  // Print the data register for a store
66  else {
67  if (_numSrcRegs > 0) {
68  printReg(ss, srcRegIdx(0));
69  }
70  }
71 
72  // Print the displacement
73  ss << ", " << d;
74  ss << "(";
75 
76  // Print the address register for a load
77  if (!flags[IsStore]) {
78  if (_numSrcRegs > 0) {
79  printReg(ss, srcRegIdx(0));
80  }
81 
82  // The address register is skipped if it is R0
83  else {
84  ss << "0";
85  }
86  }
87 
88  // Print the address register for a store
89  else {
90  if (_numSrcRegs > 1) {
91  printReg(ss, srcRegIdx(1));
92  }
93 
94  // The address register is skipped if it is R0
95  else {
96  ss << "0";
97  }
98  }
99 
100  ss << ")";
101 
102  return ss.str();
103 }
104 
105 
106 std::string
108  Addr pc, const Loader::SymbolTable *symtab) const
109 {
110  std::stringstream ss;
111 
112  ccprintf(ss, "%-10s ", mnemonic);
113 
114  // Print the destination only for a load
115  if (!flags[IsStore]) {
116  if (_numDestRegs > 0) {
117 
118  // If the instruction updates the source register with the
119  // EA, then this source register is placed in position 0,
120  // therefore we print the last destination register.
122  }
123  }
124 
125  // Print the data register for a store
126  else {
127  if (_numSrcRegs > 0) {
128  printReg(ss, srcRegIdx(0));
129  }
130  }
131 
132  // Print the displacement
133  ss << ", " << (ds << 2);
134  ss << "(";
135 
136  // Print the address register for a load
137  if (!flags[IsStore]) {
138  if (_numSrcRegs > 0) {
139  printReg(ss, srcRegIdx(0));
140  }
141 
142  // The address register is skipped if it is R0
143  else {
144  ss << "0";
145  }
146  }
147 
148  // Print the address register for a store
149  else {
150  if (_numSrcRegs > 1) {
151  printReg(ss, srcRegIdx(1));
152  }
153 
154  // The address register is skipped if it is R0
155  else {
156  ss << "0";
157  }
158  }
159 
160  ss << ")";
161 
162  return ss.str();
163 }
164 
165 std::string
167  Addr pc, const Loader::SymbolTable *symtab) const
168 {
169  std::stringstream ss;
170 
171  ccprintf(ss, "%-10s ", mnemonic);
172 
173  // Print the destination only for a load
174  if (!flags[IsStore]) {
175  if (_numDestRegs > 0) {
176 
177  // If the instruction updates the source register with the
178  // EA, then this source register is placed in position 0,
179  // therefore we print the last destination register.
181  }
182  }
183 
184  // Print the data register for a store
185  else {
186  if (_numSrcRegs > 0) {
187  printReg(ss, srcRegIdx(0));
188  }
189  }
190 
191  ss << ", ";
192 
193  // Print the address registers for a load
194  if (!flags[IsStore]) {
195  if (_numSrcRegs > 1) {
196  printReg(ss, srcRegIdx(0));
197  ss << ", ";
198  printReg(ss, srcRegIdx(1));
199  }
200 
201  // The first address register is skipped if it is R0
202  else if (_numSrcRegs > 0) {
203  ss << "0, ";
204  printReg(ss, srcRegIdx(0));
205  }
206  }
207 
208  // Print the address registers for a store
209  else {
210  if (_numSrcRegs > 2) {
211  printReg(ss, srcRegIdx(1));
212  ss << ", ";
213  printReg(ss, srcRegIdx(2));
214  }
215 
216  // The first address register is skipped if it is R0
217  else if (_numSrcRegs > 1) {
218  ss << "0, ";
219  printReg(ss, srcRegIdx(1));
220  }
221  }
222 
223  return ss.str();
224 }
225 
226 } // namespace gem5
gem5::PowerISA::MemDispOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:47
gem5::PowerISA::MemDispShiftOp::ds
int64_t ds
Definition: mem.hh:90
gem5::PowerISA::PowerStaticInst::printReg
void printReg(std::ostream &os, RegId reg) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:40
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::PowerISA::MemOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:40
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::PowerISA::MemDispShiftOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: mem.cc:107
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::PowerISA::MemIndexOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: mem.cc:166
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
ss
std::stringstream ss
Definition: trace.test.cc:45
mem.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::StaticInst::_numDestRegs
int8_t _numDestRegs
See numDestRegs().
Definition: static_inst.hh:112
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::PowerISA::MemDispOp::d
int64_t d
Definition: mem.hh:70
symtab.hh
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:109

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