gem5  v21.2.0.0
isa.cc
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37 
38 #include "arch/power/isa.hh"
39 
40 #include "arch/power/regs/float.hh"
41 #include "arch/power/regs/int.hh"
42 #include "arch/power/regs/misc.hh"
43 #include "cpu/thread_context.hh"
44 #include "params/PowerISA.hh"
45 
46 namespace gem5
47 {
48 
49 namespace PowerISA
50 {
51 
53 {
54  _regClasses.emplace_back(NumIntRegs, NumIntRegs - 1);
55  _regClasses.emplace_back(NumFloatRegs);
56  _regClasses.emplace_back(1);
57  _regClasses.emplace_back(2);
58  _regClasses.emplace_back(1);
59  _regClasses.emplace_back(0);
60  _regClasses.emplace_back(NUM_MISCREGS);
61  clear();
62 }
63 
64 void
66 {
67  // First loop through the integer registers.
68  for (int i = 0; i < NumIntRegs; ++i)
69  tc->setIntReg(i, src->readIntReg(i));
70 
71  // Then loop through the floating point registers.
72  for (int i = 0; i < NumFloatRegs; ++i)
73  tc->setFloatReg(i, src->readFloatReg(i));
74 
75  //TODO Copy misc. registers
76 
77  // Lastly copy PC/NPC
78  tc->pcState(src->pcState());
79 }
80 
81 } // namespace PowerISA
82 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::PowerISA::ISA::clear
void clear()
Definition: isa.hh:60
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:67
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::PowerISA::ISA::Params
PowerISAParams Params
Definition: isa.hh:148
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
isa.hh
int.hh
gem5::ThreadContext::setFloatReg
virtual void setFloatReg(RegIndex reg_idx, RegVal val)=0
misc.hh
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::PowerISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:43
float.hh
gem5::PowerISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:52
gem5::PowerISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:65
gem5::BaseISA
Definition: isa.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::PowerISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:46
thread_context.hh
gem5::PowerISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:39

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