gem5  v22.0.0.2
isa.cc
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37 
38 #include "arch/power/isa.hh"
39 
40 #include "arch/power/regs/float.hh"
41 #include "arch/power/regs/int.hh"
42 #include "arch/power/regs/misc.hh"
43 #include "cpu/thread_context.hh"
44 #include "debug/FloatRegs.hh"
45 #include "debug/IntRegs.hh"
46 #include "debug/MiscRegs.hh"
47 #include "params/PowerISA.hh"
48 
49 namespace gem5
50 {
51 
52 namespace PowerISA
53 {
54 
56 {
57  _regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
58  _regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
59  _regClasses.emplace_back(1, debug::IntRegs);
60  _regClasses.emplace_back(2, debug::IntRegs);
61  _regClasses.emplace_back(1, debug::IntRegs);
62  _regClasses.emplace_back(0, debug::IntRegs);
63  _regClasses.emplace_back(NUM_MISCREGS, debug::MiscRegs);
64  clear();
65 }
66 
67 void
69 {
70  // First loop through the integer registers.
71  for (int i = 0; i < int_reg::NumRegs; ++i) {
73  tc->setReg(reg, src->getReg(reg));
74  }
75 
76  // Then loop through the floating point registers.
77  for (int i = 0; i < float_reg::NumRegs; ++i) {
79  tc->setReg(reg, src->getReg(reg));
80  }
81 
82  //TODO Copy misc. registers
83 
84  // Lastly copy PC/NPC
85  tc->pcState(src->pcState());
86 }
87 
88 } // namespace PowerISA
89 } // namespace gem5
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::PowerISA::ISA::clear
void clear()
Definition: isa.hh:60
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::PowerISA::float_reg::NumRegs
const int NumRegs
Definition: float.hh:42
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::PowerISA::int_reg::NumRegs
@ NumRegs
Definition: int.hh:92
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:67
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::PowerISA::ISA::Params
PowerISAParams Params
Definition: isa.hh:148
isa.hh
int.hh
misc.hh
gem5::PowerISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:43
float.hh
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::PowerISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:55
gem5::PowerISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:68
gem5::BaseISA
Definition: isa.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
thread_context.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183

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