gem5  v21.1.0.2
isa.hh
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30 
31 #ifndef __ARCH_POWER_ISA_HH__
32 #define __ARCH_POWER_ISA_HH__
33 
34 #include "arch/generic/isa.hh"
35 #include "arch/power/regs/misc.hh"
36 #include "arch/power/types.hh"
37 #include "base/logging.hh"
38 #include "cpu/reg_class.hh"
39 #include "sim/sim_object.hh"
40 
41 namespace gem5
42 {
43 
44 struct PowerISAParams;
45 class ThreadContext;
46 class Checkpoint;
47 class EventManager;
48 
49 namespace PowerISA
50 {
51 
52 class ISA : public BaseISA
53 {
54  protected:
57 
58  public:
59  void clear() {}
60 
61  public:
62  RegVal
63  readMiscRegNoEffect(int misc_reg) const
64  {
65  fatal("Power does not currently have any misc regs defined\n");
66  return dummy;
67  }
68 
69  RegVal
70  readMiscReg(int misc_reg)
71  {
72  fatal("Power does not currently have any misc regs defined\n");
73  return dummy;
74  }
75 
76  void
77  setMiscRegNoEffect(int misc_reg, RegVal val)
78  {
79  fatal("Power does not currently have any misc regs defined\n");
80  }
81 
82  void
83  setMiscReg(int misc_reg, RegVal val)
84  {
85  fatal("Power does not currently have any misc regs defined\n");
86  }
87 
88  RegId flattenRegId(const RegId& regId) const { return regId; }
89 
90  int
91  flattenIntIndex(int reg) const
92  {
93  return reg;
94  }
95 
96  int
98  {
99  return reg;
100  }
101 
102  int
103  flattenVecIndex(int reg) const
104  {
105  return reg;
106  }
107 
108  int
110  {
111  return reg;
112  }
113 
114  int
116  {
117  return reg;
118  }
119 
120  // dummy
121  int
122  flattenCCIndex(int reg) const
123  {
124  return reg;
125  }
126 
127  int
129  {
130  return reg;
131  }
132 
133  bool
134  inUserMode() const override
135  {
136  return false;
137  }
138 
139  void copyRegsFrom(ThreadContext *src) override;
140 
141  using Params = PowerISAParams;
142 
143  ISA(const Params &p);
144 };
145 
146 } // namespace PowerISA
147 } // namespace gem5
148 
149 #endif // __ARCH_POWER_ISA_HH__
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::PowerISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:103
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::PowerISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:109
gem5::PowerISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:91
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::PowerISA::ISA::clear
void clear()
Definition: isa.hh:59
gem5::PowerISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.hh:70
gem5::PowerISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:115
gem5::PowerISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.hh:63
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::PowerISA::ISA::Params
PowerISAParams Params
Definition: isa.hh:141
sim_object.hh
gem5::PowerISA::ISA::miscRegs
RegVal miscRegs[NUM_MISCREGS]
Definition: isa.hh:56
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::PowerISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:128
misc.hh
gem5::PowerISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:43
gem5::PowerISA::ISA::dummy
RegVal dummy
Definition: isa.hh:55
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
isa.hh
gem5::PowerISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:134
gem5::PowerISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:88
reg_class.hh
logging.hh
gem5::PowerISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:52
gem5::PowerISA::ISA
Definition: isa.hh:52
gem5::PowerISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:65
gem5::PowerISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:122
gem5::BaseISA
Definition: isa.hh:54
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::PowerISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:97
types.hh
gem5::PowerISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.hh:83
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::PowerISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.hh:77

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