gem5  v22.0.0.2
isa.hh
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30 
31 #ifndef __ARCH_POWER_ISA_HH__
32 #define __ARCH_POWER_ISA_HH__
33 
34 #include "arch/generic/isa.hh"
35 #include "arch/power/pcstate.hh"
36 #include "arch/power/regs/misc.hh"
37 #include "arch/power/types.hh"
38 #include "base/logging.hh"
39 #include "cpu/reg_class.hh"
40 #include "sim/sim_object.hh"
41 
42 namespace gem5
43 {
44 
45 struct PowerISAParams;
46 class ThreadContext;
47 class Checkpoint;
48 class EventManager;
49 
50 namespace PowerISA
51 {
52 
53 class ISA : public BaseISA
54 {
55  protected:
58 
59  public:
60  void clear() {}
61 
62  PCStateBase *
63  newPCState(Addr new_inst_addr=0) const override
64  {
65  return new PCState(new_inst_addr);
66  }
67 
68  public:
69  RegVal
70  readMiscRegNoEffect(int misc_reg) const
71  {
72  fatal("Power does not currently have any misc regs defined\n");
73  return dummy;
74  }
75 
76  RegVal
77  readMiscReg(int misc_reg)
78  {
79  fatal("Power does not currently have any misc regs defined\n");
80  return dummy;
81  }
82 
83  void
84  setMiscRegNoEffect(int misc_reg, RegVal val)
85  {
86  fatal("Power does not currently have any misc regs defined\n");
87  }
88 
89  void
90  setMiscReg(int misc_reg, RegVal val)
91  {
92  fatal("Power does not currently have any misc regs defined\n");
93  }
94 
95  RegId flattenRegId(const RegId& regId) const { return regId; }
96 
97  int
98  flattenIntIndex(int reg) const
99  {
100  return reg;
101  }
102 
103  int
105  {
106  return reg;
107  }
108 
109  int
110  flattenVecIndex(int reg) const
111  {
112  return reg;
113  }
114 
115  int
117  {
118  return reg;
119  }
120 
121  int
123  {
124  return reg;
125  }
126 
127  // dummy
128  int
129  flattenCCIndex(int reg) const
130  {
131  return reg;
132  }
133 
134  int
136  {
137  return reg;
138  }
139 
140  bool
141  inUserMode() const override
142  {
143  return false;
144  }
145 
146  void copyRegsFrom(ThreadContext *src) override;
147 
148  using Params = PowerISAParams;
149 
150  ISA(const Params &p);
151 };
152 
153 } // namespace PowerISA
154 } // namespace gem5
155 
156 #endif // __ARCH_POWER_ISA_HH__
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::PowerISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:110
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::PowerISA::ISA::newPCState
PCStateBase * newPCState(Addr new_inst_addr=0) const override
Definition: isa.hh:63
gem5::PowerISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:116
gem5::PowerISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:98
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::PowerISA::ISA::clear
void clear()
Definition: isa.hh:60
gem5::PowerISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.hh:77
gem5::PowerISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:122
gem5::PowerISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.hh:70
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::PowerISA::ISA::Params
PowerISAParams Params
Definition: isa.hh:148
pcstate.hh
sim_object.hh
gem5::PowerISA::ISA::miscRegs
RegVal miscRegs[NUM_MISCREGS]
Definition: isa.hh:57
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::PowerISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:135
misc.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:43
gem5::PowerISA::ISA::dummy
RegVal dummy
Definition: isa.hh:56
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
isa.hh
gem5::PowerISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:141
gem5::PowerISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:95
reg_class.hh
logging.hh
gem5::PowerISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:55
gem5::PowerISA::ISA
Definition: isa.hh:53
gem5::PowerISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:68
gem5::PowerISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:129
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::BaseISA
Definition: isa.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::PowerISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:104
types.hh
gem5::PowerISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.hh:90
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::PowerISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.hh:84

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