decoder.hh

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/*
 * Copyright (c) 2012 Google
 * Copyright (c) 2017 The University of Virginia
 * All rights reserved.
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 * met: redistributions of source code must retain the above copyright
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 * this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#ifndef __ARCH_RISCV_DECODER_HH__
#define __ARCH_RISCV_DECODER_HH__
 
#include "arch/generic/decode_cache.hh"
#include "arch/generic/decoder.hh"
#include "arch/riscv/insts/vector.hh"
#include "arch/riscv/types.hh"
#include "base/logging.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "debug/Decode.hh"
#include "params/RiscvDecoder.hh"
 
namespace gem5
{
 
class BaseISA;
 
namespace RiscvISA
{
 
class Decoder : public InstDecoder
{
  private:
    decode_cache::InstMap<ExtMachInst> instMap;
    bool aligned;
    bool mid;
 
  protected:
    //The extended machine instruction being generated
    ExtMachInst emi;
    uint32_t machInst;
 
    uint32_t vlen;
    uint32_t elen;
 
    virtual StaticInstPtr decodeInst(ExtMachInst mach_inst);
 
    StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
 
  public:
    Decoder(const RiscvDecoderParams &p);
 
    void reset() override;
 
    inline bool compressed(ExtMachInst inst) { return inst.quadRant < 0x3; }
 
    //Use this to give data to the decoder. This should be used
    //when there is control flow.
    void moreBytes(const PCStateBase &pc, Addr fetchPC) override;
 
    StaticInstPtr decode(PCStateBase &nextPC) override;
};
 
} // namespace RiscvISA
} // namespace gem5
 
#endif // __ARCH_RISCV_DECODER_HH__