gem5  v22.0.0.2
decoder.hh
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29 
30 #ifndef __ARCH_RISCV_DECODER_HH__
31 #define __ARCH_RISCV_DECODER_HH__
32 
34 #include "arch/generic/decoder.hh"
35 #include "arch/riscv/types.hh"
36 #include "base/logging.hh"
37 #include "base/types.hh"
38 #include "cpu/static_inst.hh"
39 #include "debug/Decode.hh"
40 #include "params/RiscvDecoder.hh"
41 
42 namespace gem5
43 {
44 
45 namespace RiscvISA
46 {
47 
48 class ISA;
49 class Decoder : public InstDecoder
50 {
51  private:
53  bool aligned;
54  bool mid;
55 
56  protected:
57  //The extended machine instruction being generated
59  uint32_t machInst;
60 
62 
67 
68  public:
69  Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
70  {
71  reset();
72  }
73 
74  void reset() override;
75 
76  inline bool compressed(ExtMachInst inst) { return (inst & 0x3) < 0x3; }
77 
78  //Use this to give data to the decoder. This should be used
79  //when there is control flow.
80  void moreBytes(const PCStateBase &pc, Addr fetchPC) override;
81 
82  StaticInstPtr decode(PCStateBase &nextPC) override;
83 };
84 
85 } // namespace RiscvISA
86 } // namespace gem5
87 
88 #endif // __ARCH_RISCV_DECODER_HH__
gem5::RiscvISA::Decoder::mid
bool mid
Definition: decoder.hh:54
gem5::RiscvISA::Decoder::machInst
uint32_t machInst
Definition: decoder.hh:59
gem5::decode_cache::InstMap
std::unordered_map< EMI, StaticInstPtr > InstMap
Hash for decoded instructions.
Definition: decode_cache.hh:47
decode_cache.hh
gem5::RiscvISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.cc:83
gem5::RiscvISA::Decoder::aligned
bool aligned
Definition: decoder.hh:53
gem5::RefCountingPtr< StaticInst >
decoder.hh
gem5::RiscvISA::Decoder::Decoder
Decoder(const RiscvDecoderParams &p)
Definition: decoder.hh:69
gem5::InstDecoder
Definition: decoder.hh:42
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::RiscvISA::Decoder
Definition: decoder.hh:49
types.hh
gem5::RiscvISA::Decoder::moreBytes
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition: decoder.cc:49
static_inst.hh
gem5::RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RiscvISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:54
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::Decoder::reset
void reset() override
Definition: decoder.cc:41
gem5::RiscvISA::Decoder::instMap
decode_cache::InstMap< ExtMachInst > instMap
Definition: decoder.hh:52
types.hh
logging.hh
gem5::RiscvISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:58
gem5::PCStateBase
Definition: pcstate.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RiscvISA::Decoder::compressed
bool compressed(ExtMachInst inst)
Definition: decoder.hh:76
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::RiscvISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)

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