gem5  v21.1.0.2
decoder.cc
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29 
30 #include "arch/riscv/decoder.hh"
31 #include "arch/riscv/types.hh"
32 #include "base/bitfield.hh"
33 #include "debug/Decode.hh"
34 
35 namespace gem5
36 {
37 
38 namespace RiscvISA
39 {
40 
42 {
43  aligned = true;
44  mid = false;
45  more = true;
46  emi = 0;
47  instDone = false;
48 }
49 
50 void
52 {
53  // The MSB of the upper and lower halves of a machine instruction.
54  constexpr size_t max_bit = sizeof(machInst) * 8 - 1;
55  constexpr size_t mid_bit = sizeof(machInst) * 4 - 1;
56 
57  auto inst = letoh(machInst);
58  DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
59  fetchPC);
60 
61  bool aligned = pc.pc() % sizeof(machInst) == 0;
62  if (aligned) {
63  emi = inst;
64  if (compressed(emi))
65  emi = bits(emi, mid_bit, 0);
66  more = !compressed(emi);
67  instDone = true;
68  } else {
69  if (mid) {
70  assert(bits(emi, max_bit, mid_bit + 1) == 0);
71  replaceBits(emi, max_bit, mid_bit + 1, inst);
72  mid = false;
73  more = false;
74  instDone = true;
75  } else {
76  emi = bits(inst, max_bit, mid_bit + 1);
77  mid = !compressed(emi);
78  more = true;
80  }
81  }
82 }
83 
86 {
87  DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n",
88  mach_inst, addr);
89 
90  StaticInstPtr &si = instMap[mach_inst];
91  if (!si)
92  si = decodeInst(mach_inst);
93 
94  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
95  si->getName(), mach_inst);
96  return si;
97 }
98 
101 {
102  if (!instDone)
103  return nullptr;
104  instDone = false;
105 
106  if (compressed(emi)) {
107  nextPC.npc(nextPC.instAddr() + sizeof(machInst) / 2);
108  } else {
109  nextPC.npc(nextPC.instAddr() + sizeof(machInst));
110  }
111 
112  return decode(emi, nextPC.instAddr());
113 }
114 
115 } // namespace RiscvISA
116 } // namespace gem5
gem5::RiscvISA::Decoder::mid
bool mid
Definition: decoder.hh:53
gem5::RiscvISA::Decoder::moreBytes
void moreBytes(const PCState &pc, Addr fetchPC)
Definition: decoder.cc:51
gem5::RiscvISA::Decoder::machInst
uint32_t machInst
Definition: decoder.hh:59
gem5::RiscvISA::Decoder::more
bool more
Definition: decoder.hh:54
gem5::GenericISA::SimplePCState::npc
Addr npc() const
Definition: types.hh:154
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::RiscvISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.cc:85
gem5::RiscvISA::Decoder::aligned
bool aligned
Definition: decoder.hh:52
gem5::RefCountingPtr< StaticInst >
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
bitfield.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
types.hh
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::RiscvISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:54
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:772
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::Decoder::instDone
bool instDone
Definition: decoder.hh:60
gem5::RiscvISA::Decoder::instMap
decode_cache::InstMap< ExtMachInst > instMap
Definition: decoder.hh:51
decoder.hh
gem5::GenericISA::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address the bytes of this instruction came from.
Definition: types.hh:73
gem5::RiscvISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:58
gem5::RiscvISA::Decoder::reset
void reset()
Definition: decoder.cc:41
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::Decoder::compressed
bool compressed(ExtMachInst inst)
Definition: decoder.hh:75
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::RiscvISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)

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