gem5  v21.2.1.1
decoder.cc
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29 
30 #include "arch/riscv/decoder.hh"
31 #include "arch/riscv/types.hh"
32 #include "base/bitfield.hh"
33 #include "debug/Decode.hh"
34 
35 namespace gem5
36 {
37 
38 namespace RiscvISA
39 {
40 
42 {
43  aligned = true;
44  mid = false;
45  emi = 0;
46 }
47 
48 void
50 {
51  // The MSB of the upper and lower halves of a machine instruction.
52  constexpr size_t max_bit = sizeof(machInst) * 8 - 1;
53  constexpr size_t mid_bit = sizeof(machInst) * 4 - 1;
54 
55  auto inst = letoh(machInst);
56  DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
57  fetchPC);
58 
59  bool aligned = pc.instAddr() % sizeof(machInst) == 0;
60  if (aligned) {
61  emi = inst;
62  if (compressed(emi))
63  emi = bits(emi, mid_bit, 0);
65  instDone = true;
66  } else {
67  if (mid) {
68  assert(bits(emi, max_bit, mid_bit + 1) == 0);
69  replaceBits(emi, max_bit, mid_bit + 1, inst);
70  mid = false;
71  outOfBytes = false;
72  instDone = true;
73  } else {
74  emi = bits(inst, max_bit, mid_bit + 1);
75  mid = !compressed(emi);
76  outOfBytes = true;
78  }
79  }
80 }
81 
84 {
85  DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n",
86  mach_inst, addr);
87 
88  StaticInstPtr &si = instMap[mach_inst];
89  if (!si)
90  si = decodeInst(mach_inst);
91 
92  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
93  si->getName(), mach_inst);
94  return si;
95 }
96 
99 {
100  if (!instDone)
101  return nullptr;
102  instDone = false;
103 
104  auto &next_pc = _next_pc.as<PCState>();
105 
106  if (compressed(emi)) {
107  next_pc.npc(next_pc.instAddr() + sizeof(machInst) / 2);
108  next_pc.compressed(true);
109  } else {
110  next_pc.npc(next_pc.instAddr() + sizeof(machInst));
111  next_pc.compressed(false);
112  }
113 
114  return decode(emi, next_pc.instAddr());
115 }
116 
117 } // namespace RiscvISA
118 } // namespace gem5
gem5::RiscvISA::Decoder::mid
bool mid
Definition: decoder.hh:54
gem5::RiscvISA::Decoder::machInst
uint32_t machInst
Definition: decoder.hh:59
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::RiscvISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.cc:83
gem5::RiscvISA::Decoder::aligned
bool aligned
Definition: decoder.hh:53
gem5::RefCountingPtr< StaticInst >
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
bitfield.hh
gem5::GenericISA::PCStateWithNext::npc
Addr npc() const
Definition: pcstate.hh:266
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
types.hh
gem5::RiscvISA::Decoder::moreBytes
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition: decoder.cc:49
gem5::InstDecoder::outOfBytes
bool outOfBytes
Definition: decoder.hh:50
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::RiscvISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:54
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:773
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::Decoder::reset
void reset() override
Definition: decoder.cc:41
gem5::RiscvISA::Decoder::instMap
decode_cache::InstMap< ExtMachInst > instMap
Definition: decoder.hh:52
gem5::InstDecoder::instDone
bool instDone
Definition: decoder.hh:49
decoder.hh
gem5::RiscvISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:58
gem5::PCStateBase
Definition: pcstate.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::RiscvISA::Decoder::compressed
bool compressed(ExtMachInst inst)
Definition: decoder.hh:76
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::RiscvISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)

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