gem5 v24.0.0.0
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int.cc
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1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
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14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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27 */
28
30
31#include "arch/sparc/isa.hh"
32
33namespace gem5
34{
35
36namespace SparcISA
37{
38
39RegId
40IntRegClassOps::flatten(const BaseISA &isa, const RegId &id) const
41{
42 auto &sparc_isa = static_cast<const SparcISA::ISA &>(isa);
43 return {flatIntRegClass, sparc_isa.mapIntRegId(id.index())};
44}
45
46} // namespace SparcISA
47} // namespace gem5
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
RegId flatten(const BaseISA &isa, const RegId &id) const override
Flatten register id id using information in the ISA object isa.
Definition int.cc:40
Bitfield< 30, 0 > index
constexpr RegClass flatIntRegClass
Definition int.hh:83
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36

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