gem5 v24.0.0.0
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#include <isa.hh>
Public Types | |
using | Params = SparcISAParams |
Public Types inherited from gem5::BaseISA | |
typedef std::vector< const RegClass * > | RegClasses |
Public Types inherited from gem5::SimObject | |
typedef SimObjectParams | Params |
Public Member Functions | |
const RegIndex & | mapIntRegId (RegIndex idx) const |
void | clear () override |
PCStateBase * | newPCState (Addr new_inst_addr=0) const override |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
RegVal | readMiscRegNoEffect (RegIndex idx) const override |
RegVal | readMiscReg (RegIndex idx) override |
void | setMiscRegNoEffect (RegIndex idx, RegVal val) override |
void | setMiscReg (RegIndex idx, RegVal val) override |
uint64_t | getExecutingAsid () const override |
bool | inUserMode () const override |
void | copyRegsFrom (ThreadContext *src) override |
ISA (const Params &p) | |
Public Member Functions inherited from gem5::BaseISA | |
virtual void | takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc) |
virtual void | setThreadContext (ThreadContext *_tc) |
virtual void | resetThread () |
const RegClasses & | regClasses () const |
const std::string | getIsaName () const |
virtual void | handleLockedRead (const RequestPtr &req) |
virtual void | handleLockedRead (ExecContext *xc, const RequestPtr &req) |
virtual bool | handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) |
virtual bool | handleLockedWrite (ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask) |
virtual void | handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) |
virtual void | handleLockedSnoop (ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask) |
virtual void | handleLockedSnoopHit () |
virtual void | handleLockedSnoopHit (ExecContext *xc) |
virtual void | globalClearExclusive () |
virtual void | globalClearExclusive (ExecContext *xc) |
virtual int64_t | getVectorLengthInBytes () const |
This function returns the vector length of the Vector Length Agnostic extension of the ISA. | |
Public Member Functions inherited from gem5::SimObject | |
const Params & | params () const |
SimObject (const Params &p) | |
virtual | ~SimObject () |
virtual void | init () |
init() is called after all C++ SimObjects have been created and all ports are connected. | |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. | |
virtual void | regProbePoints () |
Register probe points for this object. | |
virtual void | regProbeListeners () |
Register probe listeners for this object. | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. | |
virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
Get a port with a given name and index. | |
virtual void | startup () |
startup() is the final initialization call before simulation. | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
Public Member Functions inherited from gem5::EventManager | |
EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. | |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
Event manger manages events in the event queue. | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
Public Member Functions inherited from gem5::Serializable | |
Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
Public Member Functions inherited from gem5::Drainable | |
DrainState | drainState () const |
Return the current drain state of an object. | |
virtual void | notifyFork () |
Notify a child process of a fork. | |
Public Member Functions inherited from gem5::statistics::Group | |
Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. | |
virtual void | resetStats () |
Callback to reset stats. | |
virtual void | preDumpStats () |
Callback before stats are dumped. | |
void | addStat (statistics::Info *info) |
Register a stat with this group. | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. | |
void | mergeStatGroup (Group *block) |
Merge the contents (stats & children) of a block to this block. | |
Group ()=delete | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
Public Member Functions inherited from gem5::Named | |
Named (const std::string &name_) | |
virtual | ~Named ()=default |
virtual std::string | name () const |
Protected Member Functions | |
bool | isHyperPriv () |
bool | isPriv () |
bool | isNonPriv () |
Protected Member Functions inherited from gem5::BaseISA | |
BaseISA (const SimObjectParams &p, const std::string &name) | |
Protected Member Functions inherited from gem5::Drainable | |
Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. | |
void | signalDrainDone () const |
Signal that an object is drained. | |
Private Types | |
enum | InstIntRegOffsets { CurrentGlobalsOffset = 0 , CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs , MicroIntOffset = CurrentWindowOffset + NumWindowedRegs , NextGlobalsOffset = MicroIntOffset + int_reg::NumMicroRegs , NextWindowOffset = NextGlobalsOffset + NumGlobalRegs , PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs , PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs , TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs } |
typedef MemberEventWrapper<&ISA::processTickCompare > | TickCompareEvent |
typedef MemberEventWrapper<&ISA::processSTickCompare > | STickCompareEvent |
typedef MemberEventWrapper<&ISA::processHSTickCompare > | HSTickCompareEvent |
Private Member Functions | |
void | setFSReg (int miscReg, RegVal val) |
RegVal | readFSReg (int miscReg) |
void | checkSoftInt () |
void | processTickCompare () |
Process a tick compare event and generate an interrupt on the cpu if appropriate. | |
void | processSTickCompare () |
void | processHSTickCompare () |
void | installWindow (int cwp, int offset) |
void | installGlobals (int gl, int offset) |
void | reloadRegMap () |
Private Attributes | |
uint8_t | asi |
uint64_t | tick |
uint8_t | fprs |
uint64_t | gsr |
uint64_t | softint |
uint64_t | tick_cmpr |
uint64_t | stick |
uint64_t | stick_cmpr |
uint64_t | tpc [MaxTL] |
uint64_t | tnpc [MaxTL] |
uint64_t | tstate [MaxTL] |
uint16_t | tt [MaxTL] |
uint64_t | tba |
PSTATE | pstate |
uint8_t | tl |
uint8_t | pil |
uint8_t | cwp |
uint8_t | gl |
HPSTATE | hpstate |
Hyperprivileged Registers. | |
uint64_t | htstate [MaxTL] |
uint64_t | hintp |
uint64_t | htba |
uint64_t | hstick_cmpr |
uint64_t | strandStatusReg |
uint64_t | fsr |
Floating point misc registers. | |
uint16_t | priContext |
MMU Internal Registers. | |
uint16_t | secContext |
uint16_t | partId |
uint64_t | lsuCtrlReg |
uint64_t | scratchPad [8] |
uint64_t | cpu_mondo_head |
uint64_t | cpu_mondo_tail |
uint64_t | dev_mondo_head |
uint64_t | dev_mondo_tail |
uint64_t | res_error_head |
uint64_t | res_error_tail |
uint64_t | nres_error_head |
uint64_t | nres_error_tail |
TickCompareEvent * | tickCompare = nullptr |
STickCompareEvent * | sTickCompare = nullptr |
HSTickCompareEvent * | hSTickCompare = nullptr |
RegIndex | intRegMap [TotalInstIntRegs] |
Static Private Attributes | |
static const int | NumGlobalRegs = 8 |
static const int | NumWindowedRegs = 24 |
static const int | WindowOverlap = 8 |
static const int | TotalGlobals = (MaxGL + 1) * NumGlobalRegs |
static const int | RegsPerWindow = NumWindowedRegs - WindowOverlap |
static const int | TotalWindowed = NWindows * RegsPerWindow |
Additional Inherited Members | |
Static Public Member Functions inherited from gem5::SimObject | |
static void | serializeAll (const std::string &cpt_dir) |
Create a checkpoint by serializing all SimObjects in the system. | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. | |
static void | setSimObjectResolver (SimObjectResolver *resolver) |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
static SimObjectResolver * | getSimObjectResolver () |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
Static Public Member Functions inherited from gem5::Serializable | |
static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. | |
Protected Attributes inherited from gem5::BaseISA | |
ThreadContext * | tc = nullptr |
RegClasses | _regClasses |
std::string | isaName |
Protected Attributes inherited from gem5::SimObject | |
const SimObjectParams & | _params |
Cached copy of the object parameters. | |
Protected Attributes inherited from gem5::EventManager | |
EventQueue * | eventq |
A pointer to this object's event queue. | |
using gem5::SparcISA::ISA::Params = SparcISAParams |
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gem5::SparcISA::ISA::ISA | ( | const Params & | p | ) |
Definition at line 82 of file isa.cc.
References gem5::BaseISA::_regClasses, gem5::ArmISA::ccRegClass, clear(), gem5::SparcISA::flatIntRegClass, gem5::X86ISA::floatRegClass, gem5::ArmISA::matRegClass, gem5::ArmISA::miscRegClass, gem5::ArmISA::vecElemClass, gem5::ArmISA::vecPredRegClass, and gem5::ArmISA::vecRegClass.
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Definition at line 47 of file ua2005.cc.
References gem5::BaseCPU::clearInterrupt(), gem5::ThreadContext::getCpuPtr(), gem5::SparcISA::IT_SOFT_INT, gem5::BaseCPU::postInterrupt(), and gem5::BaseISA::tc.
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Reimplemented from gem5::BaseISA.
Definition at line 316 of file isa.cc.
References asi, cpu_mondo_head, cpu_mondo_tail, cwp, dev_mondo_head, dev_mondo_tail, fprs, fsr, gl, gsr, hintp, hpstate, hstick_cmpr, hSTickCompare, htba, htstate, lsuCtrlReg, nres_error_head, nres_error_tail, panic, partId, pil, priContext, pstate, reloadRegMap(), res_error_head, res_error_tail, scratchPad, secContext, softint, stick, stick_cmpr, sTickCompare, strandStatusReg, tba, tick, tick_cmpr, tickCompare, tl, tnpc, tpc, tstate, and tt.
Referenced by ISA().
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Implements gem5::BaseISA.
Definition at line 232 of file isa.cc.
References gem5::SparcISA::copyMiscRegs(), gem5::X86ISA::floatRegClass, gem5::ThreadContext::getReg(), gem5::ArmISA::i, gem5::SparcISA::intRegClass, gem5::SparcISA::MaxGL, gem5::SparcISA::MISCREG_CWP, gem5::SparcISA::MISCREG_GL, gem5::SparcISA::float_reg::NumArchRegs, gem5::SparcISA::int_reg::NumArchRegs, gem5::SparcISA::int_reg::NumMicroRegs, gem5::SparcISA::NWindows, gem5::ThreadContext::pcState(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::X86ISA::reg, gem5::ThreadContext::setMiscReg(), gem5::ThreadContext::setReg(), gem5::BaseISA::tc, and gem5::RiscvISA::x.
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Reimplemented from gem5::BaseISA.
Definition at line 198 of file isa.hh.
References gem5::SparcISA::MISCREG_MMU_P_CONTEXT, and readMiscRegNoEffect().
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Definition at line 306 of file isa.cc.
References gl, gem5::ArmISA::i, intRegMap, NumGlobalRegs, gem5::SparcISA::int_reg::NumRegs, and gem5::ArmISA::offset.
Referenced by reloadRegMap(), and setMiscReg().
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Definition at line 296 of file isa.cc.
References cwp, gem5::ArmISA::i, intRegMap, gem5::SparcISA::int_reg::NumRegs, NumWindowedRegs, gem5::ArmISA::offset, RegsPerWindow, TotalGlobals, and TotalWindowed.
Referenced by reloadRegMap(), and setMiscReg().
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Implements gem5::BaseISA.
Definition at line 206 of file isa.hh.
References hpstate, gem5::SparcISA::MISCREG_HPSTATE, gem5::SparcISA::MISCREG_PSTATE, pstate, and readMiscRegNoEffect().
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Implements gem5::BaseISA.
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Definition at line 352 of file ua2005.cc.
References gem5::Clocked::clockEdge(), DPRINTF, gem5::ThreadContext::getCpuPtr(), gem5::ThreadContext::Halted, gem5::BaseCPU::instCount(), gem5::ArmISA::mask, gem5::SparcISA::MISCREG_HINTP, gem5::SparcISA::MISCREG_HSTICK_CMPR, gem5::ThreadContext::readMiscRegNoEffect(), gem5::EventManager::schedule(), gem5::ArmISA::ISA::setMiscReg(), gem5::ThreadContext::status(), gem5::ThreadContext::Suspended, and gem5::BaseISA::tc.
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Definition at line 328 of file ua2005.cc.
References gem5::Clocked::clockEdge(), DPRINTF, gem5::ThreadContext::getCpuPtr(), gem5::BaseCPU::instCount(), gem5::ArmISA::mask, gem5::SparcISA::MISCREG_SOFTINT, gem5::SparcISA::MISCREG_STICK_CMPR, gem5::ThreadContext::readMiscRegNoEffect(), gem5::EventManager::schedule(), gem5::ArmISA::ISA::setMiscReg(), gem5::ThreadContext::status(), gem5::ThreadContext::Suspended, and gem5::BaseISA::tc.
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Definition at line 248 of file ua2005.cc.
References gem5::ThreadContext::Active, gem5::ThreadContext::contextId(), gem5::ThreadContext::getSystemPtr(), gem5::ThreadContext::Halted, gem5::SparcISA::MaxTL, gem5::SparcISA::MISCREG_HINTP, gem5::SparcISA::MISCREG_HPSTATE, gem5::SparcISA::MISCREG_HSTICK_CMPR, gem5::SparcISA::MISCREG_HTBA, gem5::SparcISA::MISCREG_HTSTATE, gem5::SparcISA::MISCREG_HVER, gem5::SparcISA::MISCREG_PIL, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_TAIL, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_TAIL, gem5::SparcISA::MISCREG_SOFTINT, gem5::SparcISA::MISCREG_STICK_CMPR, gem5::SparcISA::MISCREG_STRAND_STS_REG, gem5::SparcISA::MISCREG_TICK_CMPR, gem5::SparcISA::NWindows, panic, gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::System::Threads::size(), gem5::ThreadContext::Suspended, gem5::BaseISA::tc, gem5::System::threads, and gem5::RiscvISA::x.
Referenced by readMiscReg().
Implements gem5::BaseISA.
Definition at line 540 of file isa.cc.
References DPRINTF, fprs, gem5::ThreadContext::getCpuPtr(), gem5::BaseCPU::instCount(), gem5::mbits(), gem5::SparcISA::MISCREG_FPRS, gem5::SparcISA::MISCREG_HINTP, gem5::SparcISA::MISCREG_HPSTATE, gem5::SparcISA::MISCREG_HSTICK_CMPR, gem5::SparcISA::MISCREG_HTBA, gem5::SparcISA::MISCREG_HTSTATE, gem5::SparcISA::MISCREG_HVER, gem5::SparcISA::MISCREG_PCR, gem5::SparcISA::MISCREG_PIC, gem5::SparcISA::MISCREG_PRIVTICK, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_TAIL, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_TAIL, gem5::SparcISA::MISCREG_SOFTINT, gem5::SparcISA::MISCREG_SOFTINT_CLR, gem5::SparcISA::MISCREG_SOFTINT_SET, gem5::SparcISA::MISCREG_STICK, gem5::SparcISA::MISCREG_STICK_CMPR, gem5::SparcISA::MISCREG_STRAND_STS_REG, gem5::SparcISA::MISCREG_TICK, gem5::SparcISA::MISCREG_TICK_CMPR, panic, readFSReg(), readMiscRegNoEffect(), stick, gem5::BaseISA::tc, and tick.
Privilged Registers
Hyper privileged registers
Floating Point Status Register
Implements gem5::BaseISA.
Definition at line 379 of file isa.cc.
References asi, gem5::bits(), cpu_mondo_head, cpu_mondo_tail, cwp, dev_mondo_head, dev_mondo_tail, DPRINTF, fprs, fsr, gl, gsr, hintp, hpstate, hstick_cmpr, htba, htstate, lsuCtrlReg, gem5::SparcISA::MISCREG_ASI, gem5::SparcISA::MISCREG_CWP, gem5::SparcISA::MISCREG_FPRS, gem5::SparcISA::MISCREG_FSR, gem5::SparcISA::MISCREG_GL, gem5::SparcISA::MISCREG_GSR, gem5::SparcISA::MISCREG_HINTP, gem5::SparcISA::MISCREG_HPSTATE, gem5::SparcISA::MISCREG_HSTICK_CMPR, gem5::SparcISA::MISCREG_HTBA, gem5::SparcISA::MISCREG_HTSTATE, gem5::SparcISA::MISCREG_MMU_LSU_CTRL, gem5::SparcISA::MISCREG_MMU_P_CONTEXT, gem5::SparcISA::MISCREG_MMU_PART_ID, gem5::SparcISA::MISCREG_MMU_S_CONTEXT, gem5::SparcISA::MISCREG_PCR, gem5::SparcISA::MISCREG_PIC, gem5::SparcISA::MISCREG_PIL, gem5::SparcISA::MISCREG_PRIVTICK, gem5::SparcISA::MISCREG_PSTATE, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_TAIL, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_TAIL, gem5::SparcISA::MISCREG_SCRATCHPAD_R0, gem5::SparcISA::MISCREG_SCRATCHPAD_R1, gem5::SparcISA::MISCREG_SCRATCHPAD_R2, gem5::SparcISA::MISCREG_SCRATCHPAD_R3, gem5::SparcISA::MISCREG_SCRATCHPAD_R4, gem5::SparcISA::MISCREG_SCRATCHPAD_R5, gem5::SparcISA::MISCREG_SCRATCHPAD_R6, gem5::SparcISA::MISCREG_SCRATCHPAD_R7, gem5::SparcISA::MISCREG_SOFTINT, gem5::SparcISA::MISCREG_STICK, gem5::SparcISA::MISCREG_STICK_CMPR, gem5::SparcISA::MISCREG_STRAND_STS_REG, gem5::SparcISA::MISCREG_TBA, gem5::SparcISA::MISCREG_TICK, gem5::SparcISA::MISCREG_TICK_CMPR, gem5::SparcISA::MISCREG_TL, gem5::SparcISA::MISCREG_TLB_DATA, gem5::SparcISA::MISCREG_TNPC, gem5::SparcISA::MISCREG_TPC, gem5::SparcISA::MISCREG_TSTATE, gem5::SparcISA::MISCREG_TT, nres_error_head, nres_error_tail, panic, partId, pil, priContext, pstate, res_error_head, res_error_tail, scratchPad, secContext, softint, stick, stick_cmpr, strandStatusReg, tba, tick, tick_cmpr, tl, tnpc, tpc, tstate, and tt.
Referenced by getExecutingAsid(), inUserMode(), and readMiscReg().
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Definition at line 282 of file isa.cc.
References CurrentGlobalsOffset, CurrentWindowOffset, cwp, gl, gem5::ArmISA::i, installGlobals(), installWindow(), intRegMap, MicroIntOffset, NextGlobalsOffset, NextWindowOffset, gem5::SparcISA::int_reg::NumMicroRegs, gem5::SparcISA::NWindows, PreviousGlobalsOffset, PreviousWindowOffset, and TotalGlobals.
Referenced by clear(), and unserialize().
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Serialize an object.
Output an object's state into the current checkpoint section.
cp | Checkpoint state |
Reimplemented from gem5::BaseISA.
Definition at line 845 of file isa.cc.
References asi, cpu_mondo_head, cpu_mondo_tail, cwp, dev_mondo_head, dev_mondo_tail, fprs, fsr, gl, gsr, hintp, hpstate, hstick_cmpr, hSTickCompare, htba, htstate, lsuCtrlReg, gem5::SparcISA::MaxTL, nres_error_head, nres_error_tail, partId, pil, priContext, pstate, res_error_head, res_error_tail, gem5::Event::scheduled(), scratchPad, secContext, gem5::BaseISA::serialize(), SERIALIZE_ARRAY, SERIALIZE_SCALAR, softint, stick, stick_cmpr, sTickCompare, strandStatusReg, tba, tick, tick_cmpr, tickCompare, tl, tnpc, tpc, tstate, tt, and gem5::Event::when().
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Definition at line 92 of file ua2005.cc.
References gem5::bits(), gem5::BaseCPU::clearInterrupt(), gem5::Clocked::clockEdge(), gem5::EventManager::deschedule(), DPRINTF, gem5::ThreadContext::getCpuPtr(), gem5::getMiscRegName(), gem5::ThreadContext::getSystemPtr(), gem5::BaseCPU::instCount(), gem5::SparcISA::IT_CPU_MONDO, gem5::SparcISA::IT_DEV_MONDO, gem5::SparcISA::IT_HINTP, gem5::SparcISA::IT_RES_ERROR, gem5::SparcISA::IT_TRAP_LEVEL_ZERO, gem5::ArmISA::mask, gem5::SparcISA::MISCREG_HINTP, gem5::SparcISA::MISCREG_HPSTATE, gem5::SparcISA::MISCREG_HSTICK_CMPR, gem5::SparcISA::MISCREG_HTBA, gem5::SparcISA::MISCREG_HTSTATE, gem5::SparcISA::MISCREG_HVER, gem5::SparcISA::MISCREG_PIL, gem5::SparcISA::MISCREG_PSTATE, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_TAIL, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_TAIL, gem5::SparcISA::MISCREG_SOFTINT, gem5::SparcISA::MISCREG_SOFTINT_CLR, gem5::SparcISA::MISCREG_SOFTINT_SET, gem5::SparcISA::MISCREG_STICK_CMPR, gem5::SparcISA::MISCREG_STRAND_STS_REG, gem5::SparcISA::MISCREG_TICK_CMPR, panic, gem5::BaseCPU::postInterrupt(), gem5::Workload::recordQuiesce(), gem5::EventManager::schedule(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::ThreadContext::suspend(), gem5::BaseISA::tc, gem5::MipsISA::tl, gem5::X86ISA::val, and gem5::System::workload.
Referenced by setMiscReg().
Implements gem5::BaseISA.
Definition at line 769 of file isa.cc.
References gem5::InstDecoder::as(), gem5::BaseCPU::clearInterrupt(), CurrentGlobalsOffset, CurrentWindowOffset, DPRINTF, gem5::ThreadContext::getCpuPtr(), gem5::ThreadContext::getDecoderPtr(), hpstate, installGlobals(), installWindow(), gem5::BaseCPU::instCount(), gem5::SparcISA::IT_TRAP_LEVEL_ZERO, gem5::mbits(), gem5::SparcISA::MISCREG_ASI, gem5::SparcISA::MISCREG_CWP, gem5::SparcISA::MISCREG_FPRS, gem5::SparcISA::MISCREG_GL, gem5::SparcISA::MISCREG_HINTP, gem5::SparcISA::MISCREG_HPSTATE, gem5::SparcISA::MISCREG_HSTICK_CMPR, gem5::SparcISA::MISCREG_HTBA, gem5::SparcISA::MISCREG_HTSTATE, gem5::SparcISA::MISCREG_HVER, gem5::SparcISA::MISCREG_PCR, gem5::SparcISA::MISCREG_PIL, gem5::SparcISA::MISCREG_PSTATE, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_TAIL, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_TAIL, gem5::SparcISA::MISCREG_SOFTINT, gem5::SparcISA::MISCREG_SOFTINT_CLR, gem5::SparcISA::MISCREG_SOFTINT_SET, gem5::SparcISA::MISCREG_STICK, gem5::SparcISA::MISCREG_STICK_CMPR, gem5::SparcISA::MISCREG_STRAND_STS_REG, gem5::SparcISA::MISCREG_TICK, gem5::SparcISA::MISCREG_TICK_CMPR, gem5::SparcISA::MISCREG_TL, NextGlobalsOffset, NextWindowOffset, gem5::SparcISA::NWindows, gem5::BaseCPU::postInterrupt(), PreviousGlobalsOffset, PreviousWindowOffset, pstate, gem5::SparcISA::PstateMask, setFSReg(), setMiscRegNoEffect(), stick, gem5::BaseISA::tc, tick, tl, and gem5::X86ISA::val.
Privilged Registers
Hyper privileged registers
Floating Point Status Register
Implements gem5::BaseISA.
Definition at line 588 of file isa.cc.
References asi, cpu_mondo_head, cpu_mondo_tail, cwp, dev_mondo_head, dev_mondo_tail, DPRINTF, fprs, fsr, gl, gsr, hintp, hpstate, hstick_cmpr, htba, htstate, lsuCtrlReg, gem5::SparcISA::MISCREG_ASI, gem5::SparcISA::MISCREG_CWP, gem5::SparcISA::MISCREG_FPRS, gem5::SparcISA::MISCREG_FSR, gem5::SparcISA::MISCREG_GL, gem5::SparcISA::MISCREG_GSR, gem5::SparcISA::MISCREG_HINTP, gem5::SparcISA::MISCREG_HPSTATE, gem5::SparcISA::MISCREG_HSTICK_CMPR, gem5::SparcISA::MISCREG_HTBA, gem5::SparcISA::MISCREG_HTSTATE, gem5::SparcISA::MISCREG_MMU_LSU_CTRL, gem5::SparcISA::MISCREG_MMU_P_CONTEXT, gem5::SparcISA::MISCREG_MMU_PART_ID, gem5::SparcISA::MISCREG_MMU_S_CONTEXT, gem5::SparcISA::MISCREG_PCR, gem5::SparcISA::MISCREG_PIC, gem5::SparcISA::MISCREG_PIL, gem5::SparcISA::MISCREG_PRIVTICK, gem5::SparcISA::MISCREG_PSTATE, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_HEAD, gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_TAIL, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_TAIL, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_HEAD, gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_TAIL, gem5::SparcISA::MISCREG_SCRATCHPAD_R0, gem5::SparcISA::MISCREG_SCRATCHPAD_R1, gem5::SparcISA::MISCREG_SCRATCHPAD_R2, gem5::SparcISA::MISCREG_SCRATCHPAD_R3, gem5::SparcISA::MISCREG_SCRATCHPAD_R4, gem5::SparcISA::MISCREG_SCRATCHPAD_R5, gem5::SparcISA::MISCREG_SCRATCHPAD_R6, gem5::SparcISA::MISCREG_SCRATCHPAD_R7, gem5::SparcISA::MISCREG_SOFTINT, gem5::SparcISA::MISCREG_STICK, gem5::SparcISA::MISCREG_STICK_CMPR, gem5::SparcISA::MISCREG_STRAND_STS_REG, gem5::SparcISA::MISCREG_TBA, gem5::SparcISA::MISCREG_TICK, gem5::SparcISA::MISCREG_TICK_CMPR, gem5::SparcISA::MISCREG_TL, gem5::SparcISA::MISCREG_TNPC, gem5::SparcISA::MISCREG_TPC, gem5::SparcISA::MISCREG_TSTATE, gem5::SparcISA::MISCREG_TT, nres_error_head, nres_error_tail, panic, partId, pil, priContext, pstate, gem5::SparcISA::PstateMask, res_error_head, res_error_tail, scratchPad, secContext, softint, stick, stick_cmpr, strandStatusReg, tba, tick, tick_cmpr, tl, tnpc, tpc, tstate, tt, and gem5::X86ISA::val.
Referenced by setMiscReg().
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Unserialize an object.
Read an object's state from the current checkpoint section.
cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 902 of file isa.cc.
References asi, cpu_mondo_head, cpu_mondo_tail, cwp, dev_mondo_head, dev_mondo_tail, fprs, fsr, gl, gsr, hintp, hpstate, hstick_cmpr, hSTickCompare, htba, htstate, lsuCtrlReg, gem5::SparcISA::MaxTL, nres_error_head, nres_error_tail, partId, pil, priContext, pstate, reloadRegMap(), res_error_head, res_error_tail, gem5::EventManager::schedule(), scratchPad, secContext, softint, stick, stick_cmpr, sTickCompare, strandStatusReg, tba, tick, tick_cmpr, tickCompare, tl, tnpc, tpc, tstate, tt, UNSERIALIZE_ARRAY, and UNSERIALIZE_SCALAR.
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Definition at line 62 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 113 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 114 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 85 of file isa.hh.
Referenced by clear(), installWindow(), readMiscRegNoEffect(), reloadRegMap(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 115 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 116 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 64 of file isa.hh.
Referenced by clear(), readMiscReg(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Floating point misc registers.
Definition at line 103 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 91 of file isa.hh.
Referenced by clear(), installGlobals(), readMiscRegNoEffect(), reloadRegMap(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 65 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 96 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Hyperprivileged Registers.
Definition at line 94 of file isa.hh.
Referenced by clear(), inUserMode(), isHyperPriv(), isPriv(), readMiscRegNoEffect(), serialize(), setMiscReg(), setMiscRegNoEffect(), and unserialize().
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Definition at line 98 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 143 of file isa.hh.
Referenced by clear(), serialize(), and unserialize().
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Definition at line 97 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 95 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 165 of file isa.hh.
Referenced by installGlobals(), installWindow(), mapIntRegId(), and reloadRegMap().
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Definition at line 109 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 119 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 120 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 145 of file isa.hh.
Referenced by installGlobals().
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Definition at line 146 of file isa.hh.
Referenced by installWindow().
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Definition at line 108 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 84 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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MMU Internal Registers.
Definition at line 106 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 82 of file isa.hh.
Referenced by clear(), inUserMode(), isPriv(), readMiscRegNoEffect(), serialize(), setMiscReg(), setMiscRegNoEffect(), and unserialize().
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Definition at line 150 of file isa.hh.
Referenced by installWindow().
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Definition at line 117 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 118 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 111 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 107 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 66 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 68 of file isa.hh.
Referenced by clear(), readMiscReg(), readMiscRegNoEffect(), serialize(), setMiscReg(), setMiscRegNoEffect(), and unserialize().
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Definition at line 69 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 140 of file isa.hh.
Referenced by clear(), serialize(), and unserialize().
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Definition at line 100 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 80 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 63 of file isa.hh.
Referenced by clear(), readMiscReg(), readMiscRegNoEffect(), serialize(), setMiscReg(), setMiscRegNoEffect(), and unserialize().
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Definition at line 67 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 137 of file isa.hh.
Referenced by clear(), serialize(), and unserialize().
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Definition at line 83 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscReg(), setMiscRegNoEffect(), and unserialize().
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Definition at line 75 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 149 of file isa.hh.
Referenced by installWindow(), and reloadRegMap().
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Definition at line 151 of file isa.hh.
Referenced by installWindow().
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Definition at line 73 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 77 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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Definition at line 78 of file isa.hh.
Referenced by clear(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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