gem5  v21.1.0.2
isa.hh
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28 
29 #ifndef __ARCH_SPARC_ISA_HH__
30 #define __ARCH_SPARC_ISA_HH__
31 
32 #include <ostream>
33 #include <string>
34 
35 #include "arch/generic/isa.hh"
36 #include "arch/sparc/regs/int.hh"
37 #include "arch/sparc/regs/misc.hh"
39 #include "arch/sparc/types.hh"
40 #include "cpu/reg_class.hh"
41 #include "sim/sim_object.hh"
42 
43 namespace gem5
44 {
45 
46 class Checkpoint;
47 class EventManager;
48 struct SparcISAParams;
49 class ThreadContext;
50 
51 namespace SparcISA
52 {
53 class ISA : public BaseISA
54 {
55  private:
56 
57  /* ASR Registers */
58  // uint64_t y; // Y (used in obsolete multiplication)
59  // uint8_t ccr; // Condition Code Register
60  uint8_t asi; // Address Space Identifier
61  uint64_t tick; // Hardware clock-tick counter
62  uint8_t fprs; // Floating-Point Register State
63  uint64_t gsr; // General Status Register
64  uint64_t softint;
65  uint64_t tick_cmpr; // Hardware tick compare registers
66  uint64_t stick; // Hardware clock-tick counter
67  uint64_t stick_cmpr; // Hardware tick compare registers
68 
69 
70  /* Privileged Registers */
71  uint64_t tpc[MaxTL]; // Trap Program Counter (value from
72  // previous trap level)
73  uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
74  // previous trap level)
75  uint64_t tstate[MaxTL]; // Trap State
76  uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
77  // on the previous level)
78  uint64_t tba; // Trap Base Address
79 
80  PSTATE pstate; // Process State Register
81  uint8_t tl; // Trap Level
82  uint8_t pil; // Process Interrupt Register
83  uint8_t cwp; // Current Window Pointer
84  // uint8_t cansave; // Savable windows
85  // uint8_t canrestore; // Restorable windows
86  // uint8_t cleanwin; // Clean windows
87  // uint8_t otherwin; // Other windows
88  // uint8_t wstate; // Window State
89  uint8_t gl; // Global level register
90 
92  HPSTATE hpstate; // Hyperprivileged State Register
93  uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
94  uint64_t hintp;
95  uint64_t htba; // Hyperprivileged Trap Base Address register
96  uint64_t hstick_cmpr; // Hardware tick compare registers
97 
98  uint64_t strandStatusReg;// Per strand status register
99 
101  uint64_t fsr; // Floating-Point State Register
102 
104  uint16_t priContext;
105  uint16_t secContext;
106  uint16_t partId;
107  uint64_t lsuCtrlReg;
108 
109  uint64_t scratchPad[8];
110 
111  uint64_t cpu_mondo_head;
112  uint64_t cpu_mondo_tail;
113  uint64_t dev_mondo_head;
114  uint64_t dev_mondo_tail;
115  uint64_t res_error_head;
116  uint64_t res_error_tail;
117  uint64_t nres_error_head;
118  uint64_t nres_error_tail;
119 
120  // These need to check the int_dis field and if 0 then
121  // set appropriate bit in softint and checkinterrutps on the cpu
122  void setFSReg(int miscReg, RegVal val);
123  RegVal readFSReg(int miscReg);
124 
125  // Update interrupt state on softint or pil change
126  void checkSoftInt();
127 
130  void processTickCompare();
131  void processSTickCompare();
132  void processHSTickCompare();
133 
136 
139 
142 
143  static const int NumGlobalRegs = 8;
144  static const int NumWindowedRegs = 24;
145  static const int WindowOverlap = 8;
146 
147  static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
149  static const int TotalWindowed = NWindows * RegsPerWindow;
150 
152  {
161  };
162 
164  void installWindow(int cwp, int offset);
165  void installGlobals(int gl, int offset);
166  void reloadRegMap();
167 
168  public:
169 
170  void clear();
171 
172  void serialize(CheckpointOut &cp) const override;
173  void unserialize(CheckpointIn &cp) override;
174 
175  protected:
176  bool isHyperPriv() { return hpstate.hpriv; }
177  bool isPriv() { return hpstate.hpriv || pstate.priv; }
178  bool isNonPriv() { return !isPriv(); }
179 
180  public:
181 
182  RegVal readMiscRegNoEffect(int miscReg) const;
183  RegVal readMiscReg(int miscReg);
184 
185  void setMiscRegNoEffect(int miscReg, RegVal val);
186  void setMiscReg(int miscReg, RegVal val);
187 
188  RegId
189  flattenRegId(const RegId& regId) const
190  {
191  switch (regId.classValue()) {
192  case IntRegClass:
193  return RegId(IntRegClass, flattenIntIndex(regId.index()));
194  case FloatRegClass:
195  return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
196  case CCRegClass:
197  return RegId(CCRegClass, flattenCCIndex(regId.index()));
198  case MiscRegClass:
199  return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
200  default:
201  break;
202  }
203  return regId;
204  }
205 
206  int
207  flattenIntIndex(int reg) const
208  {
209  assert(reg < TotalInstIntRegs);
210  RegIndex flatIndex = intRegMap[reg];
211  assert(flatIndex < NumIntRegs);
212  return flatIndex;
213  }
214 
215  int flattenFloatIndex(int reg) const { return reg; }
216  int flattenVecIndex(int reg) const { return reg; }
217  int flattenVecElemIndex(int reg) const { return reg; }
218  int flattenVecPredIndex(int reg) const { return reg; }
219 
220  // dummy
221  int flattenCCIndex(int reg) const { return reg; }
222  int flattenMiscIndex(int reg) const { return reg; }
223 
224  uint64_t
225  getExecutingAsid() const override
226  {
228  }
229 
230  using Params = SparcISAParams;
231 
232  bool
233  inUserMode() const override
234  {
237  return !(pstate.priv || hpstate.hpriv);
238  }
239 
240  void copyRegsFrom(ThreadContext *src) override;
241 
242  ISA(const Params &p);
243 };
244 
245 } // namespace SparcISA
246 } // namespace gem5
247 
248 #endif
gem5::SparcISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:217
gem5::SparcISA::ISA::TotalWindowed
static const int TotalWindowed
Definition: isa.hh:149
gem5::SparcISA::ISA::fsr
uint64_t fsr
Floating point misc registers.
Definition: isa.hh:101
gem5::SparcISA::ISA::CurrentWindowOffset
@ CurrentWindowOffset
Definition: isa.hh:154
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::SparcISA::ISA::processTickCompare
void processTickCompare()
Process a tick compare event and generate an interrupt on the cpu if appropriate.
Definition: ua2005.cc:322
gem5::SparcISA::ISA::WindowOverlap
static const int WindowOverlap
Definition: isa.hh:145
gem5::SparcISA::ISA::checkSoftInt
void checkSoftInt()
Definition: ua2005.cc:47
misc.hh
gem5::SparcISA::ISA::HSTickCompareEvent
EventWrapper< ISA, &ISA::processHSTickCompare > HSTickCompareEvent
Definition: isa.hh:140
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::SparcISA::ISA::nres_error_head
uint64_t nres_error_head
Definition: isa.hh:117
gem5::SparcISA::ISA::installWindow
void installWindow(int cwp, int offset)
Definition: isa.cc:273
gem5::EventWrapper
Definition: eventq.hh:1084
gem5::SparcISA::ISA::strandStatusReg
uint64_t strandStatusReg
Definition: isa.hh:98
gem5::SparcISA::ISA::asi
uint8_t asi
Definition: isa.hh:60
gem5::SparcISA::ISA::processHSTickCompare
void processHSTickCompare()
Definition: ua2005.cc:352
gem5::SparcISA::ISA::setFSReg
void setFSReg(int miscReg, RegVal val)
Definition: ua2005.cc:92
gem5::SparcISA::ISA::tnpc
uint64_t tnpc[MaxTL]
Definition: isa.hh:73
gem5::SparcISA::ISA::getExecutingAsid
uint64_t getExecutingAsid() const override
Definition: isa.hh:225
gem5::SparcISA::ISA::InstIntRegOffsets
InstIntRegOffsets
Definition: isa.hh:151
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::SparcISA::ISA::stick
uint64_t stick
Definition: isa.hh:66
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::SparcISA::ISA::hSTickCompare
HSTickCompareEvent * hSTickCompare
Definition: isa.hh:141
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::SparcISA::ISA::NextGlobalsOffset
@ NextGlobalsOffset
Definition: isa.hh:156
gem5::SparcISA::ISA::readFSReg
RegVal readFSReg(int miscReg)
Definition: ua2005.cc:248
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::SparcISA::ISA::tl
uint8_t tl
Definition: isa.hh:81
gem5::SparcISA::ISA::PreviousGlobalsOffset
@ PreviousGlobalsOffset
Definition: isa.hh:158
gem5::SparcISA::ISA::cwp
uint8_t cwp
Definition: isa.hh:83
gem5::SparcISA::ISA::tt
uint16_t tt[MaxTL]
Definition: isa.hh:76
gem5::SparcISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:822
gem5::SparcISA::ISA::CurrentGlobalsOffset
@ CurrentGlobalsOffset
Definition: isa.hh:153
gem5::SparcISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:217
gem5::SparcISA::MaxTL
const int MaxTL
Definition: sparc_traits.hh:39
gem5::SparcISA::ISA::tpc
uint64_t tpc[MaxTL]
Definition: isa.hh:71
gem5::SparcISA::ISA::hstick_cmpr
uint64_t hstick_cmpr
Definition: isa.hh:96
gem5::RegId::classValue
RegClass classValue() const
Class accessor.
Definition: reg_class.hh:180
gem5::SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: misc.hh:77
gem5::SparcISA::ISA::res_error_head
uint64_t res_error_head
Definition: isa.hh:115
gem5::SparcISA::ISA::installGlobals
void installGlobals(int gl, int offset)
Definition: isa.cc:283
gem5::SparcISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:79
gem5::SparcISA::ISA::clear
void clear()
Definition: isa.cc:293
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:154
gem5::SparcISA::ISA::lsuCtrlReg
uint64_t lsuCtrlReg
Definition: isa.hh:107
gem5::SparcISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:222
gem5::SparcISA::ISA::scratchPad
uint64_t scratchPad[8]
Definition: isa.hh:109
gem5::SparcISA::ISA::NumGlobalRegs
static const int NumGlobalRegs
Definition: isa.hh:143
gem5::SparcISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:233
gem5::SparcISA::ISA::res_error_tail
uint64_t res_error_tail
Definition: isa.hh:116
gem5::SparcISA::ISA::tstate
uint64_t tstate[MaxTL]
Definition: isa.hh:75
gem5::SparcISA::ISA::htba
uint64_t htba
Definition: isa.hh:95
gem5::SparcISA::ISA::nres_error_tail
uint64_t nres_error_tail
Definition: isa.hh:118
gem5::SparcISA::NumMicroIntRegs
@ NumMicroIntRegs
Definition: int.hh:67
gem5::SparcISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:877
gem5::SparcISA::ISA::fprs
uint8_t fprs
Definition: isa.hh:62
gem5::SparcISA::ISA::STickCompareEvent
EventWrapper< ISA, &ISA::processSTickCompare > STickCompareEvent
Definition: isa.hh:137
gem5::SparcISA::ISA::TickCompareEvent
EventWrapper< ISA, &ISA::processTickCompare > TickCompareEvent
Definition: isa.hh:134
gem5::SparcISA::ISA::PreviousWindowOffset
@ PreviousWindowOffset
Definition: isa.hh:159
gem5::SparcISA::ISA::gsr
uint64_t gsr
Definition: isa.hh:63
gem5::SparcISA::ISA::gl
uint8_t gl
Definition: isa.hh:89
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
sim_object.hh
gem5::SparcISA::ISA::RegsPerWindow
static const int RegsPerWindow
Definition: isa.hh:148
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::SparcISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int miscReg, RegVal val)
Definition: isa.cc:565
gem5::SparcISA::ISA::TotalInstIntRegs
@ TotalInstIntRegs
Definition: isa.hh:160
gem5::SparcISA::ISA
Definition: isa.hh:53
gem5::SparcISA::ISA::tickCompare
TickCompareEvent * tickCompare
Definition: isa.hh:135
gem5::SparcISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:218
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::SparcISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:215
int.hh
gem5::SparcISA::ISA::processSTickCompare
void processSTickCompare()
Definition: ua2005.cc:328
gem5::SparcISA::ISA::hpstate
HPSTATE hpstate
Hyperprivileged Registers.
Definition: isa.hh:92
types.hh
gem5::SparcISA::ISA::dev_mondo_head
uint64_t dev_mondo_head
Definition: isa.hh:113
gem5::SparcISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:69
gem5::SparcISA::ISA::tba
uint64_t tba
Definition: isa.hh:78
gem5::SparcISA::ISA::secContext
uint16_t secContext
Definition: isa.hh:105
gem5::SparcISA::ISA::softint
uint64_t softint
Definition: isa.hh:64
gem5::SparcISA::ISA::priContext
uint16_t priContext
MMU Internal Registers.
Definition: isa.hh:104
gem5::SparcISA::ISA::TotalGlobals
static const int TotalGlobals
Definition: isa.hh:147
gem5::SparcISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int miscReg) const
Definition: isa.cc:356
gem5::SparcISA::ISA::hintp
uint64_t hintp
Definition: isa.hh:94
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::SparcISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:216
gem5::SparcISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:221
isa.hh
gem5::SparcISA::ISA::NextWindowOffset
@ NextWindowOffset
Definition: isa.hh:157
gem5::SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:44
gem5::SparcISA::ISA::reloadRegMap
void reloadRegMap()
Definition: isa.cc:259
gem5::SparcISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:189
gem5::SparcISA::ISA::pil
uint8_t pil
Definition: isa.hh:82
gem5::SparcISA::ISA::isPriv
bool isPriv()
Definition: isa.hh:177
gem5::SparcISA::ISA::setMiscReg
void setMiscReg(int miscReg, RegVal val)
Definition: isa.cc:746
gem5::SparcISA::MaxGL
const int MaxGL
Definition: sparc_traits.hh:40
reg_class.hh
gem5::SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: misc.hh:65
gem5::SparcISA::ISA::tick_cmpr
uint64_t tick_cmpr
Definition: isa.hh:65
gem5::SparcISA::ISA::isNonPriv
bool isNonPriv()
Definition: isa.hh:178
gem5::SparcISA::ISA::dev_mondo_tail
uint64_t dev_mondo_tail
Definition: isa.hh:114
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::SparcISA::ISA::partId
uint16_t partId
Definition: isa.hh:106
gem5::SparcISA::ISA::NumWindowedRegs
static const int NumWindowedRegs
Definition: isa.hh:144
gem5::SparcISA::ISA::readMiscReg
RegVal readMiscReg(int miscReg)
Definition: isa.cc:517
gem5::SparcISA::ISA::stick_cmpr
uint64_t stick_cmpr
Definition: isa.hh:67
gem5::SparcISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:207
gem5::SparcISA::ISA::intRegMap
RegIndex intRegMap[TotalInstIntRegs]
Definition: isa.hh:163
gem5::BaseISA
Definition: isa.hh:54
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::SparcISA::ISA::tick
uint64_t tick
Definition: isa.hh:61
gem5::SparcISA::ISA::isHyperPriv
bool isHyperPriv()
Definition: isa.hh:176
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SparcISA::ISA::MicroIntOffset
@ MicroIntOffset
Definition: isa.hh:155
gem5::SparcISA::ISA::sTickCompare
STickCompareEvent * sTickCompare
Definition: isa.hh:138
gem5::SparcISA::ISA::cpu_mondo_head
uint64_t cpu_mondo_head
Definition: isa.hh:111
sparc_traits.hh
gem5::SparcISA::ISA::pstate
PSTATE pstate
Definition: isa.hh:80
gem5::SparcISA::MISCREG_MMU_P_CONTEXT
@ MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition: misc.hh:89
gem5::SparcISA::ISA::cpu_mondo_tail
uint64_t cpu_mondo_tail
Definition: isa.hh:112
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::SparcISA::ISA::htstate
uint64_t htstate[MaxTL]
Definition: isa.hh:93
gem5::SparcISA::ISA::Params
SparcISAParams Params
Definition: isa.hh:230

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