gem5  v22.0.0.1
isa.hh
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28 
29 #ifndef __ARCH_SPARC_ISA_HH__
30 #define __ARCH_SPARC_ISA_HH__
31 
32 #include <ostream>
33 #include <string>
34 
35 #include "arch/generic/isa.hh"
36 #include "arch/sparc/pcstate.hh"
37 #include "arch/sparc/regs/int.hh"
38 #include "arch/sparc/regs/misc.hh"
40 #include "arch/sparc/types.hh"
41 #include "cpu/reg_class.hh"
42 #include "sim/sim_object.hh"
43 
44 namespace gem5
45 {
46 
47 class Checkpoint;
48 class EventManager;
49 struct SparcISAParams;
50 class ThreadContext;
51 
52 namespace SparcISA
53 {
54 class ISA : public BaseISA
55 {
56  private:
57 
58  /* ASR Registers */
59  // uint64_t y; // Y (used in obsolete multiplication)
60  // uint8_t ccr; // Condition Code Register
61  uint8_t asi; // Address Space Identifier
62  uint64_t tick; // Hardware clock-tick counter
63  uint8_t fprs; // Floating-Point Register State
64  uint64_t gsr; // General Status Register
65  uint64_t softint;
66  uint64_t tick_cmpr; // Hardware tick compare registers
67  uint64_t stick; // Hardware clock-tick counter
68  uint64_t stick_cmpr; // Hardware tick compare registers
69 
70 
71  /* Privileged Registers */
72  uint64_t tpc[MaxTL]; // Trap Program Counter (value from
73  // previous trap level)
74  uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
75  // previous trap level)
76  uint64_t tstate[MaxTL]; // Trap State
77  uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
78  // on the previous level)
79  uint64_t tba; // Trap Base Address
80 
81  PSTATE pstate; // Process State Register
82  uint8_t tl; // Trap Level
83  uint8_t pil; // Process Interrupt Register
84  uint8_t cwp; // Current Window Pointer
85  // uint8_t cansave; // Savable windows
86  // uint8_t canrestore; // Restorable windows
87  // uint8_t cleanwin; // Clean windows
88  // uint8_t otherwin; // Other windows
89  // uint8_t wstate; // Window State
90  uint8_t gl; // Global level register
91 
93  HPSTATE hpstate; // Hyperprivileged State Register
94  uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
95  uint64_t hintp;
96  uint64_t htba; // Hyperprivileged Trap Base Address register
97  uint64_t hstick_cmpr; // Hardware tick compare registers
98 
99  uint64_t strandStatusReg;// Per strand status register
100 
102  uint64_t fsr; // Floating-Point State Register
103 
105  uint16_t priContext;
106  uint16_t secContext;
107  uint16_t partId;
108  uint64_t lsuCtrlReg;
109 
110  uint64_t scratchPad[8];
111 
112  uint64_t cpu_mondo_head;
113  uint64_t cpu_mondo_tail;
114  uint64_t dev_mondo_head;
115  uint64_t dev_mondo_tail;
116  uint64_t res_error_head;
117  uint64_t res_error_tail;
118  uint64_t nres_error_head;
119  uint64_t nres_error_tail;
120 
121  // These need to check the int_dis field and if 0 then
122  // set appropriate bit in softint and checkinterrutps on the cpu
123  void setFSReg(int miscReg, RegVal val);
124  RegVal readFSReg(int miscReg);
125 
126  // Update interrupt state on softint or pil change
127  void checkSoftInt();
128 
131  void processTickCompare();
132  void processSTickCompare();
133  void processHSTickCompare();
134 
137 
140 
143 
144  static const int NumGlobalRegs = 8;
145  static const int NumWindowedRegs = 24;
146  static const int WindowOverlap = 8;
147 
148  static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
150  static const int TotalWindowed = NWindows * RegsPerWindow;
151 
153  {
162  };
163 
165  void installWindow(int cwp, int offset);
166  void installGlobals(int gl, int offset);
167  void reloadRegMap();
168 
169  public:
170  void clear();
171 
172  PCStateBase *
173  newPCState(Addr new_inst_addr=0) const override
174  {
175  return new PCState(new_inst_addr);
176  }
177 
178  void serialize(CheckpointOut &cp) const override;
179  void unserialize(CheckpointIn &cp) override;
180 
181  protected:
182  bool isHyperPriv() { return hpstate.hpriv; }
183  bool isPriv() { return hpstate.hpriv || pstate.priv; }
184  bool isNonPriv() { return !isPriv(); }
185 
186  public:
187 
188  RegVal readMiscRegNoEffect(int miscReg) const;
189  RegVal readMiscReg(int miscReg);
190 
191  void setMiscRegNoEffect(int miscReg, RegVal val);
192  void setMiscReg(int miscReg, RegVal val);
193 
194  RegId
195  flattenRegId(const RegId& regId) const
196  {
197  switch (regId.classValue()) {
198  case IntRegClass:
199  return RegId(IntRegClass, flattenIntIndex(regId.index()));
200  case FloatRegClass:
201  return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
202  case CCRegClass:
203  return RegId(CCRegClass, flattenCCIndex(regId.index()));
204  case MiscRegClass:
205  return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
206  default:
207  break;
208  }
209  return regId;
210  }
211 
212  int
213  flattenIntIndex(int reg) const
214  {
215  assert(reg < TotalInstIntRegs);
216  RegIndex flatIndex = intRegMap[reg];
217  assert(flatIndex < NumIntRegs);
218  return flatIndex;
219  }
220 
221  int flattenFloatIndex(int reg) const { return reg; }
222  int flattenVecIndex(int reg) const { return reg; }
223  int flattenVecElemIndex(int reg) const { return reg; }
224  int flattenVecPredIndex(int reg) const { return reg; }
225 
226  // dummy
227  int flattenCCIndex(int reg) const { return reg; }
228  int flattenMiscIndex(int reg) const { return reg; }
229 
230  uint64_t
231  getExecutingAsid() const override
232  {
234  }
235 
236  using Params = SparcISAParams;
237 
238  bool
239  inUserMode() const override
240  {
243  return !(pstate.priv || hpstate.hpriv);
244  }
245 
246  void copyRegsFrom(ThreadContext *src) override;
247 
248  ISA(const Params &p);
249 };
250 
251 } // namespace SparcISA
252 } // namespace gem5
253 
254 #endif
gem5::SparcISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:223
gem5::SparcISA::ISA::TotalWindowed
static const int TotalWindowed
Definition: isa.hh:150
gem5::SparcISA::ISA::fsr
uint64_t fsr
Floating point misc registers.
Definition: isa.hh:102
gem5::SparcISA::ISA::CurrentWindowOffset
@ CurrentWindowOffset
Definition: isa.hh:155
gem5::SparcISA::ISA::processTickCompare
void processTickCompare()
Process a tick compare event and generate an interrupt on the cpu if appropriate.
Definition: ua2005.cc:322
gem5::SparcISA::ISA::WindowOverlap
static const int WindowOverlap
Definition: isa.hh:146
gem5::SparcISA::ISA::checkSoftInt
void checkSoftInt()
Definition: ua2005.cc:47
misc.hh
gem5::SparcISA::ISA::HSTickCompareEvent
EventWrapper< ISA, &ISA::processHSTickCompare > HSTickCompareEvent
Definition: isa.hh:141
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::SparcISA::ISA::nres_error_head
uint64_t nres_error_head
Definition: isa.hh:118
gem5::SparcISA::ISA::installWindow
void installWindow(int cwp, int offset)
Definition: isa.cc:275
gem5::EventWrapper
Definition: eventq.hh:1084
gem5::SparcISA::ISA::strandStatusReg
uint64_t strandStatusReg
Definition: isa.hh:99
pcstate.hh
gem5::SparcISA::ISA::asi
uint8_t asi
Definition: isa.hh:61
gem5::SparcISA::ISA::processHSTickCompare
void processHSTickCompare()
Definition: ua2005.cc:352
gem5::SparcISA::ISA::setFSReg
void setFSReg(int miscReg, RegVal val)
Definition: ua2005.cc:92
gem5::SparcISA::ISA::tnpc
uint64_t tnpc[MaxTL]
Definition: isa.hh:74
gem5::SparcISA::ISA::getExecutingAsid
uint64_t getExecutingAsid() const override
Definition: isa.hh:231
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::SparcISA::ISA::InstIntRegOffsets
InstIntRegOffsets
Definition: isa.hh:152
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::SparcISA::ISA::stick
uint64_t stick
Definition: isa.hh:67
gem5::SparcISA::ISA::hSTickCompare
HSTickCompareEvent * hSTickCompare
Definition: isa.hh:142
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::SparcISA::ISA::NextGlobalsOffset
@ NextGlobalsOffset
Definition: isa.hh:157
gem5::SparcISA::ISA::readFSReg
RegVal readFSReg(int miscReg)
Definition: ua2005.cc:248
gem5::SparcISA::ISA::tl
uint8_t tl
Definition: isa.hh:82
gem5::SparcISA::ISA::PreviousGlobalsOffset
@ PreviousGlobalsOffset
Definition: isa.hh:159
gem5::SparcISA::ISA::cwp
uint8_t cwp
Definition: isa.hh:84
gem5::SparcISA::ISA::tt
uint16_t tt[MaxTL]
Definition: isa.hh:77
gem5::SparcISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:824
gem5::SparcISA::ISA::CurrentGlobalsOffset
@ CurrentGlobalsOffset
Definition: isa.hh:154
gem5::SparcISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:219
gem5::SparcISA::MaxTL
const int MaxTL
Definition: sparc_traits.hh:39
gem5::SparcISA::ISA::tpc
uint64_t tpc[MaxTL]
Definition: isa.hh:72
gem5::SparcISA::ISA::hstick_cmpr
uint64_t hstick_cmpr
Definition: isa.hh:97
gem5::SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: misc.hh:77
gem5::SparcISA::ISA::res_error_head
uint64_t res_error_head
Definition: isa.hh:116
gem5::SparcISA::ISA::installGlobals
void installGlobals(int gl, int offset)
Definition: isa.cc:285
gem5::SparcISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:79
gem5::SparcISA::ISA::clear
void clear()
Definition: isa.cc:295
gem5::SparcISA::ISA::lsuCtrlReg
uint64_t lsuCtrlReg
Definition: isa.hh:108
gem5::SparcISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:228
gem5::SparcISA::ISA::scratchPad
uint64_t scratchPad[8]
Definition: isa.hh:110
gem5::SparcISA::ISA::NumGlobalRegs
static const int NumGlobalRegs
Definition: isa.hh:144
gem5::SparcISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:239
gem5::SparcISA::ISA::res_error_tail
uint64_t res_error_tail
Definition: isa.hh:117
gem5::SparcISA::ISA::tstate
uint64_t tstate[MaxTL]
Definition: isa.hh:76
gem5::SparcISA::ISA::htba
uint64_t htba
Definition: isa.hh:96
gem5::SparcISA::ISA::newPCState
PCStateBase * newPCState(Addr new_inst_addr=0) const override
Definition: isa.hh:173
gem5::SparcISA::ISA::nres_error_tail
uint64_t nres_error_tail
Definition: isa.hh:119
gem5::SparcISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:879
gem5::SparcISA::ISA::fprs
uint8_t fprs
Definition: isa.hh:63
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::SparcISA::ISA::STickCompareEvent
EventWrapper< ISA, &ISA::processSTickCompare > STickCompareEvent
Definition: isa.hh:138
gem5::SparcISA::ISA::TickCompareEvent
EventWrapper< ISA, &ISA::processTickCompare > TickCompareEvent
Definition: isa.hh:135
gem5::SparcISA::ISA::PreviousWindowOffset
@ PreviousWindowOffset
Definition: isa.hh:160
gem5::SparcISA::ISA::gsr
uint64_t gsr
Definition: isa.hh:64
gem5::SparcISA::ISA::gl
uint8_t gl
Definition: isa.hh:90
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
sim_object.hh
gem5::SparcISA::ISA::RegsPerWindow
static const int RegsPerWindow
Definition: isa.hh:149
gem5::SparcISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int miscReg, RegVal val)
Definition: isa.cc:567
gem5::SparcISA::ISA::TotalInstIntRegs
@ TotalInstIntRegs
Definition: isa.hh:161
gem5::SparcISA::ISA
Definition: isa.hh:54
gem5::SparcISA::ISA::tickCompare
TickCompareEvent * tickCompare
Definition: isa.hh:136
gem5::SparcISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:224
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::SparcISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:221
int.hh
gem5::SparcISA::ISA::processSTickCompare
void processSTickCompare()
Definition: ua2005.cc:328
gem5::SparcISA::ISA::hpstate
HPSTATE hpstate
Hyperprivileged Registers.
Definition: isa.hh:93
types.hh
gem5::SparcISA::ISA::dev_mondo_head
uint64_t dev_mondo_head
Definition: isa.hh:114
gem5::SparcISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:71
gem5::SparcISA::ISA::tba
uint64_t tba
Definition: isa.hh:79
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::ISA::secContext
uint16_t secContext
Definition: isa.hh:106
gem5::SparcISA::ISA::softint
uint64_t softint
Definition: isa.hh:65
gem5::SparcISA::ISA::priContext
uint16_t priContext
MMU Internal Registers.
Definition: isa.hh:105
gem5::SparcISA::ISA::TotalGlobals
static const int TotalGlobals
Definition: isa.hh:148
gem5::SparcISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int miscReg) const
Definition: isa.cc:358
gem5::SparcISA::ISA::hintp
uint64_t hintp
Definition: isa.hh:95
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::SparcISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:222
gem5::SparcISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:227
isa.hh
gem5::SparcISA::ISA::NextWindowOffset
@ NextWindowOffset
Definition: isa.hh:158
gem5::SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:44
gem5::SparcISA::ISA::reloadRegMap
void reloadRegMap()
Definition: isa.cc:261
gem5::SparcISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:195
gem5::SparcISA::ISA::pil
uint8_t pil
Definition: isa.hh:83
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::SparcISA::ISA::isPriv
bool isPriv()
Definition: isa.hh:183
gem5::SparcISA::ISA::setMiscReg
void setMiscReg(int miscReg, RegVal val)
Definition: isa.cc:748
gem5::SparcISA::MaxGL
const int MaxGL
Definition: sparc_traits.hh:40
reg_class.hh
gem5::SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: misc.hh:65
gem5::SparcISA::ISA::tick_cmpr
uint64_t tick_cmpr
Definition: isa.hh:66
gem5::SparcISA::ISA::isNonPriv
bool isNonPriv()
Definition: isa.hh:184
gem5::SparcISA::ISA::dev_mondo_tail
uint64_t dev_mondo_tail
Definition: isa.hh:115
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::SparcISA::ISA::partId
uint16_t partId
Definition: isa.hh:107
gem5::SparcISA::ISA::NumWindowedRegs
static const int NumWindowedRegs
Definition: isa.hh:145
gem5::SparcISA::PCState
GenericISA::DelaySlotUPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::SparcISA::ISA::readMiscReg
RegVal readMiscReg(int miscReg)
Definition: isa.cc:519
gem5::SparcISA::ISA::stick_cmpr
uint64_t stick_cmpr
Definition: isa.hh:68
gem5::SparcISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:213
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::RegId::index
constexpr RegIndex index() const
Index accessors.
Definition: reg_class.hh:188
gem5::SparcISA::ISA::intRegMap
RegIndex intRegMap[TotalInstIntRegs]
Definition: isa.hh:164
gem5::BaseISA
Definition: isa.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::SparcISA::ISA::tick
uint64_t tick
Definition: isa.hh:62
gem5::SparcISA::ISA::isHyperPriv
bool isHyperPriv()
Definition: isa.hh:182
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RegId::classValue
constexpr RegClassType classValue() const
Class accessor.
Definition: reg_class.hh:191
gem5::SparcISA::ISA::MicroIntOffset
@ MicroIntOffset
Definition: isa.hh:156
gem5::SparcISA::ISA::sTickCompare
STickCompareEvent * sTickCompare
Definition: isa.hh:139
gem5::SparcISA::ISA::cpu_mondo_head
uint64_t cpu_mondo_head
Definition: isa.hh:112
sparc_traits.hh
gem5::SparcISA::ISA::pstate
PSTATE pstate
Definition: isa.hh:81
gem5::SparcISA::NumMicroIntRegs
@ NumMicroIntRegs
Definition: int.hh:67
gem5::SparcISA::MISCREG_MMU_P_CONTEXT
@ MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition: misc.hh:89
gem5::SparcISA::ISA::cpu_mondo_tail
uint64_t cpu_mondo_tail
Definition: isa.hh:113
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::SparcISA::ISA::htstate
uint64_t htstate[MaxTL]
Definition: isa.hh:94
gem5::SparcISA::ISA::Params
SparcISAParams Params
Definition: isa.hh:236

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