43using namespace ArmISA;
109 std::stringstream
ss;
122 std::stringstream
ss;
137 std::stringstream
ss;
151 std::stringstream
ss;
167 std::stringstream
ss;
184 int roundingMode = fegetround();
207 bool underflow =
false;
222 if ((exceptions &
FeInexact) && !(underflow && flush) &&
mask.ixc) {
228template <
class fpType>
230fixDest(
bool flush,
bool defaultNan, fpType val, fpType op1)
232 int fpClass = std::fpclassify(
val);
234 if (fpClass == FP_NAN) {
235 const bool single = (
sizeof(
val) ==
sizeof(
float));
236 const uint64_t qnan = single ? 0x7fc00000 : 0x7ff8000000000000ULL;
238 if (!nan || defaultNan) {
239 val = bitsToFp(qnan, junk);
241 val = bitsToFp(fpToBits(op1) | qnan, junk);
243 }
else if (fpClass == FP_SUBNORMAL && flush == 1) {
245 uint64_t bitMask = 0x1ULL << (
sizeof(fpType) * 8 - 1);
246 val = bitsToFp(fpToBits(
val) & bitMask, junk);
254float fixDest<float>(
bool flush,
bool defaultNan,
float val,
float op1);
256double fixDest<double>(
bool flush,
bool defaultNan,
double val,
double op1);
258template <
class fpType>
260fixDest(
bool flush,
bool defaultNan, fpType val, fpType op1, fpType op2)
262 int fpClass = std::fpclassify(
val);
264 if (fpClass == FP_NAN) {
265 const bool single = (
sizeof(
val) ==
sizeof(
float));
266 const uint64_t qnan = single ? 0x7fc00000 : 0x7ff8000000000000ULL;
269 const bool signal1 = nan1 && ((fpToBits(op1) & qnan) != qnan);
270 const bool signal2 = nan2 && ((fpToBits(op2) & qnan) != qnan);
271 if ((!nan1 && !nan2) || defaultNan) {
272 val = bitsToFp(qnan, junk);
273 }
else if (signal1) {
274 val = bitsToFp(fpToBits(op1) | qnan, junk);
275 }
else if (signal2) {
276 val = bitsToFp(fpToBits(op2) | qnan, junk);
282 }
else if (fpClass == FP_SUBNORMAL && flush) {
284 uint64_t bitMask = 0x1ULL << (
sizeof(fpType) * 8 - 1);
285 val = bitsToFp(fpToBits(
val) & bitMask, junk);
293float fixDest<float>(
bool flush,
bool defaultNan,
294 float val,
float op1,
float op2);
296double fixDest<double>(
bool flush,
bool defaultNan,
297 double val,
double op1,
double op2);
299template <
class fpType>
301fixDivDest(
bool flush,
bool defaultNan, fpType val, fpType op1, fpType op2)
303 fpType mid =
fixDest(flush, defaultNan,
val, op1, op2);
304 const bool single = (
sizeof(fpType) ==
sizeof(
float));
305 const fpType junk = 0.0;
306 if ((single && (
val == bitsToFp(0x00800000, junk) ||
307 val == bitsToFp(0x80800000, junk))) ||
308 (!single && (
val == bitsToFp(0x0010000000000000ULL, junk) ||
309 val == bitsToFp(0x8010000000000000ULL, junk)))
311 __asm__ __volatile__(
"" :
"=m" (op1) :
"m" (op1));
314 __asm__ __volatile__(
"" :
"=m" (temp) :
"m" (temp));
323 __asm__ __volatile__(
"" ::
"m" (temp));
329float fixDivDest<float>(
bool flush,
bool defaultNan,
330 float val,
float op1,
float op2);
332double fixDivDest<double>(
bool flush,
bool defaultNan,
333 double val,
double op1,
double op2);
338 const float junk = 0.0;
341 uint64_t valBits = fpToBits(
val);
342 uint32_t op1Bits =
bits(valBits, 50, 29) |
344 (
bits(valBits, 63) << 31);
345 op1 = bitsToFp(op1Bits, junk);
347 float mid =
fixDest(fpscr.fz, fpscr.dn, (
float)
val, op1);
352 if (mid == bitsToFp(0x00800000, junk) ||
353 mid == bitsToFp(0x80800000, junk)) {
354 __asm__ __volatile__(
"" :
"=m" (
val) :
"m" (
val));
357 __asm__ __volatile__(
"" :
"=m" (temp) :
"m" (temp));
366 __asm__ __volatile__(
"" ::
"m" (temp));
374 const double junk = 0.0;
377 uint32_t valBits = fpToBits(
val);
378 uint64_t op1Bits = ((uint64_t)
bits(valBits, 21, 0) << 29) |
380 ((uint64_t)
bits(valBits, 31) << 63);
381 op1 = bitsToFp(op1Bits, junk);
383 double mid =
fixDest(fpscr.fz, fpscr.dn, (
double)
val, op1);
384 if (mid == bitsToFp(0x0010000000000000ULL, junk) ||
385 mid == bitsToFp(0x8010000000000000ULL, junk)) {
386 __asm__ __volatile__(
"" :
"=m" (
val) :
"m" (
val));
389 __asm__ __volatile__(
"" :
"=m" (temp) :
"m" (temp));
398 __asm__ __volatile__(
"" ::
"m" (temp));
403static inline uint16_t
405 uint32_t rMode,
bool ahp, uint64_t opBits,
bool isDouble)
419 sBitPos = eWidth + mWidth;
420 eHalfRange = (1 << (eWidth-1)) - 1;
423 bool neg =
bits(opBits, sBitPos);
424 uint32_t exponent =
bits(opBits, sBitPos-1, mWidth);
425 uint64_t oldMantissa =
bits(opBits, mWidth-1, 0);
426 uint32_t mantissa = oldMantissa >> (mWidth - 10);
428 uint64_t extra = oldMantissa &
mask(mWidth - 10);
429 if (exponent ==
mask(eWidth)) {
430 if (oldMantissa != 0) {
432 if (
bits(mantissa, 9) == 0) {
440 }
else if (defaultNan) {
446 mantissa |= (1 << 9);
458 }
else if (exponent == 0 && oldMantissa == 0) {
463 bool inexact = (extra != 0);
471 if (inexact || fpscr.ufe)
480 (extra == (1 << 9) &&
bits(mantissa, 0))))) {
485 if (mantissa == (1 << 10)) {
494 bool topOne =
bits(extra, mWidth - 10 - 1);
495 bool restZeros =
bits(extra, mWidth - 10 - 2, 0) == 0;
497 if (exponent <= (eHalfRange - 15)) {
499 mantissa |= (1 << 10);
500 while (mantissa && exponent <= (eHalfRange - 15)) {
501 restZeros = restZeros && !topOne;
502 topOne =
bits(mantissa, 0);
503 mantissa = mantissa >> 1;
506 if (topOne || !restZeros)
511 exponent -= (eHalfRange - 15);
514 if (exponent == 0 && (inexact || fpscr.ufe)) {
521 bool nonZero = topOne || !restZeros;
525 (!restZeros ||
bits(mantissa, 0)))) {
530 if (mantissa == (1 << 10)) {
537 if (exponent >= 0x20) {
545 if (exponent >= 0x1f) {
568 uint32_t result =
bits(mantissa, 9, 0);
577 uint32_t rMode,
bool ahp,
float op)
579 uint64_t opBits = fpToBits(
op);
585 uint32_t rMode,
bool ahp,
double op)
587 uint64_t opBits = fpToBits(
op);
591static inline uint64_t
592vcvtFpHFp(FPSCR &fpscr,
bool defaultNan,
bool ahp, uint16_t op,
bool isDouble)
606 sBitPos = eWidth + mWidth;
607 eHalfRange = (1 << (eWidth-1)) - 1;
611 uint32_t exponent =
bits(
op, 14, 10);
612 uint64_t mantissa =
bits(
op, 9, 0);
617 exponent = exponent + (eHalfRange - 15) + 1;
618 while (mantissa < (1 << 10)) {
619 mantissa = mantissa << 1;
623 mantissa = mantissa << (mWidth - 10);
624 }
else if (exponent == 0x1f && !
ahp) {
626 exponent =
mask(eWidth);
629 mantissa = mantissa << (mWidth - 10);
630 if (
bits(mantissa, mWidth-1) == 0) {
633 mantissa |= (((uint64_t) 1) << (mWidth-1));
636 mantissa &= ~mask(mWidth-1);
641 exponent = exponent + (eHalfRange - 15);
642 mantissa = mantissa << (mWidth - 10);
645 uint64_t result =
bits(mantissa, mWidth-1, 0);
648 result |= (((uint64_t) 1) << sBitPos);
654vcvtFpHFpD(FPSCR &fpscr,
bool defaultNan,
bool ahp, uint16_t op)
660 return bitsToFp(result, junk);
664vcvtFpHFpS(FPSCR &fpscr,
bool defaultNan,
bool ahp, uint16_t op)
670 return bitsToFp(result, junk);
675 uint64_t val, uint8_t width, uint8_t imm)
680 else if (
width == 32)
682 else if (
width != 64)
685 __asm__ __volatile__(
"" :
"=m" (
scale) :
"m" (
scale));
687 __asm__ __volatile__(
"" :
"=m" (
scale) :
"m" (
scale));
693 int64_t val, uint8_t width, uint8_t imm)
698 else if (
width == 32)
700 else if (
width != 64)
704 __asm__ __volatile__(
"" :
"=m" (
scale) :
"m" (
scale));
706 __asm__ __volatile__(
"" :
"=m" (
scale) :
"m" (
scale));
713 uint64_t val, uint8_t width, uint8_t imm)
718 else if (
width == 32)
720 else if (
width != 64)
724 __asm__ __volatile__(
"" :
"=m" (
scale) :
"m" (
scale));
726 __asm__ __volatile__(
"" :
"=m" (
scale) :
"m" (
scale));
732 int64_t val, uint8_t width, uint8_t imm)
737 else if (
width == 32)
739 else if (
width != 64)
743 __asm__ __volatile__(
"" :
"=m" (
scale) :
"m" (
scale));
745 __asm__ __volatile__(
"" :
"=m" (
scale) :
"m" (
scale));
757 q0 = (int64_t)(
a * 512.0);
758 r = 1.0 / sqrt(((
double)q0 + 0.5) / 512.0);
760 q1 = (int64_t)(
a * 256.0);
761 r = 1.0 / sqrt(((
double)q1 + 0.5) / 256.0);
763 s = (int64_t)(256.0 * r + 0.5);
764 return (
double)s / 256.0;
772 const uint32_t qnan = 0x7fc00000;
774 int fpClass = std::fpclassify(
op);
775 if (fpClass == FP_NAN) {
776 if ((fpToBits(
op) & qnan) != qnan)
778 return bitsToFp(qnan, junk);
779 }
else if (fpClass == FP_ZERO) {
782 return bitsToFp((std::signbit(
op) << 31) |
783 (0xFF << 23) | (0 << 0), junk);
784 }
else if (std::signbit(
op)) {
787 return bitsToFp(qnan, junk);
788 }
else if (fpClass == FP_INFINITE) {
791 uint64_t opBits = fpToBits(
op);
793 if (
bits(opBits, 23)) {
794 scaled = bitsToFp((0 << 0) | (
bits(opBits, 22, 0) << 29) |
795 (0x3fdULL << 52) | (
bits(opBits, 31) << 63),
798 scaled = bitsToFp((0 << 0) | (
bits(opBits, 22, 0) << 29) |
799 (0x3feULL << 52) | (
bits(opBits, 31) << 63),
802 uint64_t resultExp = (380 -
bits(opBits, 30, 23)) / 2;
806 return bitsToFp((
bits(estimate, 63) << 31) |
807 (
bits(resultExp, 7, 0) << 23) |
808 (
bits(estimate, 51, 29) << 0), junk);
815 if (
bits(
op, 31, 30) == 0) {
820 dpOp = bitsToFp((0ULL << 63) |
822 (
bits((uint64_t)
op, 30, 0) << 21) |
823 (0 << 0), (
double)0.0);
825 dpOp = bitsToFp((0ULL << 63) |
827 (
bits((uint64_t)
op, 29, 0) << 22) |
828 (0 << 0), (
double)0.0);
831 return (1 << 31) |
bits(estimate, 51, 21);
843 q = (int64_t)(
a * 512.0);
844 r = 1.0 / (((double)
q + 0.5) / 512.0);
845 s = (int64_t)(256.0 * r + 0.5);
846 return (
double)s / 256.0;
854 const uint32_t qnan = 0x7fc00000;
856 int fpClass = std::fpclassify(
op);
857 if (fpClass == FP_NAN) {
858 if ((fpToBits(
op) & qnan) != qnan)
860 return bitsToFp(qnan, junk);
861 }
else if (fpClass == FP_INFINITE) {
862 return bitsToFp(std::signbit(
op) << 31, junk);
863 }
else if (fpClass == FP_ZERO) {
866 return bitsToFp((std::signbit(
op) << 31) |
867 (0xFF << 23) | (0 << 0), junk);
868 }
else if (fabs(
op) >= pow(2.0, 126)) {
870 return bitsToFp(std::signbit(
op) << 31, junk);
872 uint64_t opBits = fpToBits(
op);
874 scaled = bitsToFp((0 << 0) | (
bits(opBits, 22, 0) << 29) |
875 (0x3feULL << 52) | (0ULL << 63),
877 uint64_t resultExp = 253 -
bits(opBits, 30, 23);
881 return bitsToFp((
bits(opBits, 31) << 31) |
882 (
bits(resultExp, 7, 0) << 23) |
883 (
bits(estimate, 51, 29) << 0), junk);
894 dpOp = bitsToFp((0ULL << 63) |
896 (
bits((uint64_t)
op, 30, 0) << 21) |
897 (0 << 0), (
double)0.0);
899 return (1 << 31) |
bits(estimate, 51, 21);
907 new_fpscr.ahp = fpscr.ahp;
910 new_fpscr.fz16 = fpscr.fz16;
914template <
class fpType>
916FpOp::processNans(FPSCR &fpscr,
bool &done,
bool defaultNan,
917 fpType op1, fpType op2)
const
922 const bool single = (
sizeof(fpType) ==
sizeof(
float));
923 const uint64_t qnan =
924 single ? 0x7fc00000 : 0x7ff8000000000000ULL;
927 const bool signal1 = nan1 && ((fpToBits(op1) & qnan) != qnan);
928 const bool signal2 = nan2 && ((fpToBits(op2) & qnan) != qnan);
931 dest = bitsToFp(qnan, junk);
932 }
else if (signal1) {
933 dest = bitsToFp(fpToBits(op1) | qnan, junk);
934 }
else if (signal2) {
935 dest = bitsToFp(fpToBits(op2) | qnan, junk);
941 if (signal1 || signal2) {
951float FpOp::processNans(FPSCR &fpscr,
bool &done,
bool defaultNan,
952 float op1,
float op2)
const;
954double FpOp::processNans(FPSCR &fpscr,
bool &done,
bool defaultNan,
955 double op1,
double op2)
const;
958template <
class fpType>
960FpOp::ternaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType op3,
961 fpType (*func)(fpType, fpType, fpType),
962 bool flush,
bool defaultNan, uint32_t rMode)
const
964 const bool single = (
sizeof(fpType) ==
sizeof(
float));
970 __asm__ __volatile__ (
"" :
"=m" (op1),
"=m" (op2),
"=m" (op3),
"=m" (
state)
971 :
"m" (op1),
"m" (op2),
"m" (op3),
"m" (
state));
972 fpType dest = func(op1, op2, op3);
973 __asm__ __volatile__ (
"" :
"=m" (dest) :
"m" (dest));
975 int fpClass = std::fpclassify(dest);
977 if (fpClass == FP_NAN) {
978 const uint64_t qnan =
979 single ? 0x7fc00000 : 0x7ff8000000000000ULL;
983 const bool signal1 = nan1 && ((fpToBits(op1) & qnan) != qnan);
984 const bool signal2 = nan2 && ((fpToBits(op2) & qnan) != qnan);
985 const bool signal3 = nan3 && ((fpToBits(op3) & qnan) != qnan);
986 if ((!nan1 && !nan2 && !nan3) || (defaultNan == 1)) {
987 dest = bitsToFp(qnan, junk);
988 }
else if (signal1) {
989 dest = bitsToFp(fpToBits(op1) | qnan, junk);
990 }
else if (signal2) {
991 dest = bitsToFp(fpToBits(op2) | qnan, junk);
992 }
else if (signal3) {
993 dest = bitsToFp(fpToBits(op3) | qnan, junk);
1004 (single && (dest == bitsToFp(0x00800000, junk) ||
1005 dest == bitsToFp(0x80800000, junk))) ||
1007 (dest == bitsToFp(0x0010000000000000ULL, junk) ||
1008 dest == bitsToFp(0x8010000000000000ULL, junk)))
1015 __asm__ __volatile__ (
"" :
"=m" (op1),
"=m" (op2),
"=m" (op3)
1016 :
"m" (op1),
"m" (op2),
"m" (op3));
1017 fpType temp = func(op1, op2, op2);
1018 __asm__ __volatile__ (
"" :
"=m" (temp) :
"m" (temp));
1028float FpOp::ternaryOp(FPSCR &fpscr,
float op1,
float op2,
float op3,
1029 float (*func)(
float,
float,
float),
1030 bool flush,
bool defaultNan, uint32_t rMode)
const;
1032double FpOp::ternaryOp(FPSCR &fpscr,
double op1,
double op2,
double op3,
1033 double (*func)(
double,
double,
double),
1034 bool flush,
bool defaultNan, uint32_t rMode)
const;
1036template <
class fpType>
1038FpOp::binaryOp(FPSCR &fpscr, fpType op1, fpType op2,
1039 fpType (*func)(fpType, fpType),
1040 bool flush,
bool defaultNan, uint32_t rMode)
const
1042 const bool single = (
sizeof(fpType) ==
sizeof(
float));
1048 __asm__ __volatile__ (
"" :
"=m" (op1),
"=m" (op2),
"=m" (
state)
1049 :
"m" (op1),
"m" (op2),
"m" (
state));
1050 fpType dest = func(op1, op2);
1051 __asm__ __volatile__ (
"" :
"=m" (dest) :
"m" (dest));
1055 const uint64_t qnan =
1056 single ? 0x7fc00000 : 0x7ff8000000000000ULL;
1059 const bool signal1 = nan1 && ((fpToBits(op1) & qnan) != qnan);
1060 const bool signal2 = nan2 && ((fpToBits(op2) & qnan) != qnan);
1061 if ((!nan1 && !nan2) || (defaultNan == 1)) {
1062 dest = bitsToFp(qnan, junk);
1063 }
else if (signal1) {
1064 dest = bitsToFp(fpToBits(op1) | qnan, junk);
1065 }
else if (signal2) {
1066 dest = bitsToFp(fpToBits(op2) | qnan, junk);
1075 (single && (dest == bitsToFp(0x00800000, junk) ||
1076 dest == bitsToFp(0x80800000, junk))) ||
1078 (dest == bitsToFp(0x0010000000000000ULL, junk) ||
1079 dest == bitsToFp(0x8010000000000000ULL, junk)))
1086 __asm__ __volatile__ (
"" :
"=m" (op1),
"=m" (op2)
1087 :
"m" (op1),
"m" (op2));
1088 fpType temp = func(op1, op2);
1089 __asm__ __volatile__ (
"" :
"=m" (temp) :
"m" (temp));
1099float FpOp::binaryOp(FPSCR &fpscr,
float op1,
float op2,
1100 float (*func)(
float,
float),
1101 bool flush,
bool defaultNan, uint32_t rMode)
const;
1103double FpOp::binaryOp(FPSCR &fpscr,
double op1,
double op2,
1104 double (*func)(
double,
double),
1105 bool flush,
bool defaultNan, uint32_t rMode)
const;
1107template <
class fpType>
1109FpOp::unaryOp(FPSCR &fpscr, fpType op1, fpType (*func)(fpType),
1110 bool flush, uint32_t rMode)
const
1112 const bool single = (
sizeof(fpType) ==
sizeof(
float));
1118 __asm__ __volatile__ (
"" :
"=m" (op1),
"=m" (
state)
1119 :
"m" (op1),
"m" (
state));
1120 fpType dest = func(op1);
1121 __asm__ __volatile__ (
"" :
"=m" (dest) :
"m" (dest));
1125 const uint64_t qnan =
1126 single ? 0x7fc00000 : 0x7ff8000000000000ULL;
1128 if (!nan || fpscr.dn == 1) {
1129 dest = bitsToFp(qnan, junk);
1131 dest = bitsToFp(fpToBits(op1) | qnan, junk);
1136 (single && (dest == bitsToFp(0x00800000, junk) ||
1137 dest == bitsToFp(0x80800000, junk))) ||
1139 (dest == bitsToFp(0x0010000000000000ULL, junk) ||
1140 dest == bitsToFp(0x8010000000000000ULL, junk)))
1147 __asm__ __volatile__ (
"" :
"=m" (op1) :
"m" (op1));
1148 fpType temp = func(op1);
1149 __asm__ __volatile__ (
"" :
"=m" (temp) :
"m" (temp));
1159float FpOp::unaryOp(FPSCR &fpscr,
float op1,
float (*func)(
float),
1160 bool flush, uint32_t rMode)
const;
1162double FpOp::unaryOp(FPSCR &fpscr,
double op1,
double (*func)(
double),
1163 bool flush, uint32_t rMode)
const;
1171 unsigned offset = idx % 8;
1181 unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
1182 assert(!inScalarBank(dest));
1183 dest = addStride(dest,
stride);
1184 op1 = addStride(op1,
stride);
1185 if (!inScalarBank(op2)) {
1186 op2 = addStride(op2,
stride);
1193 unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
1194 assert(!inScalarBank(dest));
1195 dest = addStride(dest,
stride);
1196 if (!inScalarBank(op1)) {
1197 op1 = addStride(op1,
stride);
1204 unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
1205 assert(!inScalarBank(dest));
1206 dest = addStride(dest,
stride);
void printCondition(std::ostream &os, unsigned code, bool noImplicit=false) const
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
void printFloatReg(std::ostream &os, RegIndex reg_idx) const
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
#define panic(...)
This implements a cprintf based panic() function.
uint32_t unsignedRecipEstimate(uint32_t op)
fpType fixDivDest(bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
static uint16_t vcvtFpFpH(FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, uint64_t opBits, bool isDouble)
double vfpSFixedToFpD(bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
double vcvtFpHFpD(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
static uint64_t vcvtFpHFp(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op, bool isDouble)
float vfpUFixedToFpS(bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
uint32_t unsignedRSqrtEstimate(uint32_t op)
VfpSavedState prepFpState(uint32_t rMode)
float fixFpDFpSDest(FPSCR fpscr, double val)
void finishVfp(FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask)
double fixFpSFpDDest(FPSCR fpscr, float val)
float vcvtFpHFpS(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
float vfpSFixedToFpS(bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
fpType fixDest(bool flush, bool defaultNan, fpType val, fpType op1)
double vfpUFixedToFpD(bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
Bitfield< 21, 20 > stride
static double recipEstimate(double a)
uint16_t vcvtFpDFpH(FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, double op)
FPSCR fpStandardFPSCRValue(const FPSCR &fpscr)
uint16_t vcvtFpSFpH(FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, float op)
float fprSqrtEstimate(FPSCR &fpscr, float op)
static double recipSqrtEstimate(double a)
float fpRecipEstimate(FPSCR &fpscr, float op)
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uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
void ccprintf(cp::Print &print)
constexpr bool isnan(gem5::AMDGPU::fp16_e5m10_info a)