gem5  v22.1.0.0
int.cc
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37 
38 #include "arch/x86/regs/int.hh"
39 
40 #include <sstream>
41 
42 namespace gem5
43 {
44 
45 namespace X86ISA
46 {
47 
48 std::string
50 {
51  constexpr const char *abcdFormats[9] =
52  {"", "%s", "%sx", "", "e%sx", "", "", "", "r%sx"};
53  constexpr const char *piFormats[9] =
54  {"", "%s", "%s", "", "e%s", "", "", "", "r%s"};
55  constexpr const char *longFormats[9] =
56  {"", "r%sb", "r%sw", "", "r%sd", "", "", "", "r%s"};
57  constexpr const char *microFormats[9] =
58  {"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
59 
60  // Fix size at 8 for now.
61  constexpr unsigned size = 8;
62 
63  RegIndex reg_idx = id.index();
64 
65  std::ostringstream ss;
66 
67  const char * suffix = "";
68  bool fold = reg_idx & IntFoldBit;
69  reg_idx &= ~IntFoldBit;
70 
71  if (fold)
72  suffix = "h";
73  else if (reg_idx < 8 && size == 1)
74  suffix = "l";
75 
76  switch (reg_idx) {
77  case int_reg::Rax:
78  ccprintf(ss, abcdFormats[size], "a");
79  break;
80  case int_reg::Rbx:
81  ccprintf(ss, abcdFormats[size], "b");
82  break;
83  case int_reg::Rcx:
84  ccprintf(ss, abcdFormats[size], "c");
85  break;
86  case int_reg::Rdx:
87  ccprintf(ss, abcdFormats[size], "d");
88  break;
89  case int_reg::Rsp:
90  ccprintf(ss, piFormats[size], "sp");
91  break;
92  case int_reg::Rbp:
93  ccprintf(ss, piFormats[size], "bp");
94  break;
95  case int_reg::Rsi:
96  ccprintf(ss, piFormats[size], "si");
97  break;
98  case int_reg::Rdi:
99  ccprintf(ss, piFormats[size], "di");
100  break;
101  case int_reg::R8:
102  ccprintf(ss, longFormats[size], "8");
103  break;
104  case int_reg::R9:
105  ccprintf(ss, longFormats[size], "9");
106  break;
107  case int_reg::R10:
108  ccprintf(ss, longFormats[size], "10");
109  break;
110  case int_reg::R11:
111  ccprintf(ss, longFormats[size], "11");
112  break;
113  case int_reg::R12:
114  ccprintf(ss, longFormats[size], "12");
115  break;
116  case int_reg::R13:
117  ccprintf(ss, longFormats[size], "13");
118  break;
119  case int_reg::R14:
120  ccprintf(ss, longFormats[size], "14");
121  break;
122  case int_reg::R15:
123  ccprintf(ss, longFormats[size], "15");
124  break;
125  default:
126  ccprintf(ss, microFormats[size],
127  reg_idx - int_reg::MicroBegin);
128  }
129  ccprintf(ss, suffix);
130 
131  return ss.str();
132 }
133 
134 RegId
135 IntRegClassOps::flatten(const BaseISA &isa, const RegId &id) const
136 {
137  return {flatIntRegClass, (RegIndex)(id.index() & ~IntFoldBit)};
138 }
139 
140 } // namespace X86ISA
141 } // namespace gem5
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:91
std::string regName(const RegId &id) const override
Print the name of the register specified in id.
Definition: int.cc:49
RegId flatten(const BaseISA &isa, const RegId &id) const override
Flatten register id id using information in the ISA object isa.
Definition: int.cc:135
constexpr RegId R12
Definition: int.hh:144
constexpr RegId R9
Definition: int.hh:141
constexpr RegId R8
Definition: int.hh:140
constexpr RegId R14
Definition: int.hh:146
constexpr RegId Rbx
Definition: int.hh:135
constexpr RegId Rsi
Definition: int.hh:138
constexpr RegId R15
Definition: int.hh:147
constexpr RegId Rax
Definition: int.hh:132
constexpr RegId Rdx
Definition: int.hh:134
constexpr RegId Rsp
Definition: int.hh:136
constexpr RegId Rdi
Definition: int.hh:139
constexpr RegId R13
Definition: int.hh:145
constexpr RegId Rbp
Definition: int.hh:137
constexpr RegId R11
Definition: int.hh:143
constexpr RegId R10
Definition: int.hh:142
constexpr RegId Rcx
Definition: int.hh:133
constexpr RegClass flatIntRegClass
Definition: int.hh:112
Bitfield< 5, 3 > index
Definition: types.hh:98
constexpr RegIndex IntFoldBit
Definition: int.hh:178
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint16_t RegIndex
Definition: types.hh:176
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
std::stringstream ss
Definition: trace.test.cc:45

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