fetch.hh

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 * Authors: Kevin Lim
 *          Korey Sewell
 */

#ifndef __CPU_O3_FETCH_HH__
#define __CPU_O3_FETCH_HH__

#include "arch/decoder.hh"
#include "arch/utility.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/pc_event.hh"
#include "cpu/pred/bpred_unit.hh"
#include "cpu/timebuf.hh"
#include "cpu/translation.hh"
#include "enums/FetchPolicy.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"

struct DerivO3CPUParams;
template <class Impl>
class FullO3CPU;

template <class Impl>
class DefaultFetch
{
  public:
    typedef typename Impl::CPUPol CPUPol;
    typedef typename Impl::DynInst DynInst;
    typedef typename Impl::DynInstPtr DynInstPtr;
    typedef typename Impl::O3CPU O3CPU;

    typedef typename CPUPol::FetchStruct FetchStruct;
    typedef typename CPUPol::TimeStruct TimeStruct;

    typedef TheISA::MachInst MachInst;

    class IcachePort : public MasterPort
    {
      protected:
        DefaultFetch<Impl> *fetch;

      public:
        IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
            : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
        { }

      protected:

        virtual bool recvTimingResp(PacketPtr pkt);

        virtual void recvReqRetry();
    };

    class FetchTranslation : public BaseTLB::Translation
    {
      protected:
        DefaultFetch<Impl> *fetch;

      public:
        FetchTranslation(DefaultFetch<Impl> *_fetch)
            : fetch(_fetch)
        {}

        void
        markDelayed()
        {}

        void
        finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
               BaseTLB::Mode mode)
        {
            assert(mode == BaseTLB::Execute);
            fetch->finishTranslation(fault, req);
            delete this;
        }
    };

  private:
    /* Event to delay delivery of a fetch translation result in case of
     * a fault and the nop to carry the fault cannot be generated
     * immediately */
    class FinishTranslationEvent : public Event
    {
      private:
        DefaultFetch<Impl> *fetch;
        Fault fault;
        RequestPtr req;

      public:
        FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
            : fetch(_fetch), req(nullptr)
        {}

        void setFault(Fault _fault)
        {
            fault = _fault;
        }

        void setReq(const RequestPtr &_req)
        {
            req = _req;
        }

        void process()
        {
            assert(fetch->numInst < fetch->fetchWidth);
            fetch->finishTranslation(fault, req);
        }

        const char *description() const
        {
            return "FullO3CPU FetchFinishTranslation";
        }
      };

  public:
    enum FetchStatus {
        Active,
        Inactive
    };

    enum ThreadStatus {
        Running,
        Idle,
        Squashing,
        Blocked,
        Fetching,
        TrapPending,
        QuiescePending,
        ItlbWait,
        IcacheWaitResponse,
        IcacheWaitRetry,
        IcacheAccessComplete,
        NoGoodAddr
    };

  private:
    FetchStatus _status;

    ThreadStatus fetchStatus[Impl::MaxThreads];

    FetchPolicy fetchPolicy;

    std::list<ThreadID> priorityList;

    ProbePointArg<DynInstPtr> *ppFetch;
    ProbePointArg<RequestPtr> *ppFetchRequestSent;

  public:
    DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);

    std::string name() const;

    void regStats();

    void regProbePoints();

    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);

    void setActiveThreads(std::list<ThreadID> *at_ptr);

    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);

    void startupStage();

    void clearStates(ThreadID tid);

    void recvReqRetry();

    void processCacheCompletion(PacketPtr pkt);

    void drainResume();

    void drainSanityCheck() const;

    bool isDrained() const;

    void takeOverFrom();

    void drainStall(ThreadID tid);

    void wakeFromQuiesce();

    void deactivateThread(ThreadID tid);
  private:
    void resetStage();

    inline void switchToActive();

    inline void switchToInactive();

    bool lookupAndUpdateNextPC(const DynInstPtr &inst, TheISA::PCState &pc);

    bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
    void finishTranslation(const Fault &fault, const RequestPtr &mem_req);


    bool
    checkInterrupt(Addr pc)
    {
        return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
    }

    inline void doSquash(const TheISA::PCState &newPC,
                         const DynInstPtr squashInst, ThreadID tid);

    void squashFromDecode(const TheISA::PCState &newPC,
                          const DynInstPtr squashInst,
                          const InstSeqNum seq_num, ThreadID tid);

    bool checkStall(ThreadID tid) const;

    FetchStatus updateFetchStatus();

  public:
    void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
                DynInstPtr squashInst, ThreadID tid);

    void tick();

    bool checkSignalsAndUpdate(ThreadID tid);

    void fetch(bool &status_change);

    Addr fetchBufferAlignPC(Addr addr)
    {
        return (addr & ~(fetchBufferMask));
    }

    TheISA::Decoder *decoder[Impl::MaxThreads];

    MasterPort &getInstPort() { return icachePort; }

  private:
    DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
                         StaticInstPtr curMacroop, TheISA::PCState thisPC,
                         TheISA::PCState nextPC, bool trace);

    ThreadID getFetchingThread();

    ThreadID roundRobin();

    ThreadID iqCount();

    ThreadID lsqCount();

    ThreadID branchCount();

    void pipelineIcacheAccesses(ThreadID tid);

    void profileStall(ThreadID tid);

  private:
    O3CPU *cpu;

    TimeBuffer<TimeStruct> *timeBuffer;

    typename TimeBuffer<TimeStruct>::wire fromDecode;

    typename TimeBuffer<TimeStruct>::wire fromRename;

    typename TimeBuffer<TimeStruct>::wire fromIEW;

    typename TimeBuffer<TimeStruct>::wire fromCommit;

    //Might be annoying how this name is different than the queue.
    typename TimeBuffer<FetchStruct>::wire toDecode;

    BPredUnit *branchPred;

    TheISA::PCState pc[Impl::MaxThreads];

    Addr fetchOffset[Impl::MaxThreads];

    StaticInstPtr macroop[Impl::MaxThreads];

    bool delayedCommit[Impl::MaxThreads];

    RequestPtr memReq[Impl::MaxThreads];

    bool wroteToTimeBuffer;

    int numInst;

    struct Stalls {
        bool decode;
        bool drain;
    };

    Stalls stalls[Impl::MaxThreads];

    Cycles decodeToFetchDelay;

    Cycles renameToFetchDelay;

    Cycles iewToFetchDelay;

    Cycles commitToFetchDelay;

    unsigned fetchWidth;

    unsigned decodeWidth;

    bool cacheBlocked;

    PacketPtr retryPkt;

    ThreadID retryTid;

    unsigned int cacheBlkSize;

    unsigned fetchBufferSize;

    Addr fetchBufferMask;

    uint8_t *fetchBuffer[Impl::MaxThreads];

    Addr fetchBufferPC[Impl::MaxThreads];

    unsigned fetchQueueSize;

    std::deque<DynInstPtr> fetchQueue[Impl::MaxThreads];

    bool fetchBufferValid[Impl::MaxThreads];

    int instSize;

    Counter lastIcacheStall[Impl::MaxThreads];

    std::list<ThreadID> *activeThreads;

    ThreadID numThreads;

    ThreadID numFetchingThreads;

    ThreadID threadFetched;

    bool interruptPending;

    IcachePort icachePort;

    bool issuePipelinedIfetch[Impl::MaxThreads];

    FinishTranslationEvent finishTranslationEvent;

    // @todo: Consider making these vectors and tracking on a per thread basis.
    Stats::Scalar icacheStallCycles;
    Stats::Scalar fetchedInsts;
    Stats::Scalar fetchedBranches;
    Stats::Scalar predictedBranches;
    Stats::Scalar fetchCycles;
    Stats::Scalar fetchSquashCycles;
    Stats::Scalar fetchTlbCycles;
    Stats::Scalar fetchIdleCycles;
    Stats::Scalar fetchBlockedCycles;
    Stats::Scalar fetchMiscStallCycles;
    Stats::Scalar fetchPendingDrainCycles;
    Stats::Scalar fetchNoActiveThreadStallCycles;
    Stats::Scalar fetchPendingTrapStallCycles;
    Stats::Scalar fetchPendingQuiesceStallCycles;
    Stats::Scalar fetchIcacheWaitRetryStallCycles;
    Stats::Scalar fetchedCacheLines;
    Stats::Scalar fetchIcacheSquashes;
    Stats::Scalar fetchTlbSquashes;
    Stats::Distribution fetchNisnDist;
    Stats::Formula idleRate;
    Stats::Formula branchRate;
    Stats::Formula fetchRate;
};

#endif //__CPU_O3_FETCH_HH__