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tsunami.cc
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1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
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8  * notice, this list of conditions and the following disclaimer;
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10  * notice, this list of conditions and the following disclaimer in the
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12  * neither the name of the copyright holders nor the names of its
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14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * Authors: Ali Saidi
29  */
30 
35 #include "dev/alpha/tsunami.hh"
36 
37 #include <deque>
38 #include <string>
39 #include <vector>
40 
41 #include "arch/alpha/system.hh"
42 #include "cpu/intr_control.hh"
44 #include "dev/alpha/tsunami_io.hh"
46 
47 using namespace std;
48 
50  : Platform(p), system(p->system)
51 {
52  for (int i = 0; i < Tsunami::Max_CPUs; i++)
53  intr_sum_type[i] = 0;
54 }
55 
56 void
58 {
59  AlphaSystem *alphaSystem = dynamic_cast<AlphaSystem *>(system);
60  assert(alphaSystem);
61  alphaSystem->setIntrFreq(io->frequency());
62 }
63 
64 void
66 {
67  io->postPIC(0x10);
68 }
69 
70 void
72 {
73  io->clearPIC(0x10);
74 }
75 
76 void
78 {
79  cchip->postDRIR(line);
80 }
81 
82 void
84 {
85  cchip->clearDRIR(line);
86 }
87 
88 void
90 {
92 }
93 
94 void
96 {
98 }
99 
100 Tsunami *
101 TsunamiParams::create()
102 {
103  return new Tsunami(this);
104 }
void postPciInt(int line) override
Cause the chipset to post a cpi interrupt to the CPU.
Definition: tsunami.cc:77
Emulation of the Tsunami CChip CSRs.
Tsunami(const Params *p)
Definition: tsunami.cc:49
TsunamiParams Params
Definition: tsunami.hh:86
Bitfield< 7 > i
Tsunami PCI interface CSRs.
void postDRIR(uint32_t interrupt)
post an interrupt to the CPU.
Top level class for Tsunami Chipset emulation.
Definition: tsunami.hh:56
System * system
Pointer to the system.
Definition: tsunami.hh:63
static const int Max_CPUs
Max number of CPUs in a Tsunami.
Definition: tsunami.hh:60
void clearPIC(uint8_t bitvector)
Clear a posted interrupt.
Definition: tsunami_io.cc:242
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: tsunami.cc:89
void setIntrFreq(Tick freq)
Definition: system.hh:127
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:586
Definition: cprintf.cc:42
TsunamiCChip * cchip
Pointer to the Tsunami CChip.
Definition: tsunami.hh:72
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: tsunami.cc:57
void clearConsoleInt() override
Clear a posted CPU interrupt.
Definition: tsunami.cc:71
void postConsoleInt() override
Cause the cpu to post a serial interrupt to the CPU.
Definition: tsunami.cc:65
Declaration of top level class for the Tsunami chipset.
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:658
int intr_sum_type[Tsunami::Max_CPUs]
Definition: tsunami.hh:80
Tsunami I/O Space mapping including RTC/timer interrupts.
Bitfield< 15 > system
Definition: misc.hh:999
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:661
Tick frequency() const
Return the freqency of the RTC.
Definition: tsunami_io.cc:81
std::ostream CheckpointOut
Definition: serialize.hh:68
void clearDRIR(uint32_t interrupt)
clear an interrupt previously posted to the CPU.
TsunamiIO * io
Pointer to the TsunamiIO device which has the RTC.
Definition: tsunami.hh:66
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: tsunami.cc:95
void postPIC(uint8_t bitvector)
Post an PIC interrupt to the CPU via the CChip.
Definition: tsunami_io.cc:231
Bitfield< 0 > p
void clearPciInt(int line) override
Clear a posted PCI->CPU interrupt.
Definition: tsunami.cc:83

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