gem5  v21.1.0.2
cortex_r52.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXR52_CORETEX_R52_HH__
29 #define __ARCH_ARM_FASTMODEL_CORTEXR52_CORETEX_R52_HH__
30 
34 #include "params/FastModelCortexR52.hh"
35 #include "params/FastModelCortexR52Cluster.hh"
36 #include "scx/scx.h"
37 #include "sim/port.hh"
39 
40 namespace gem5
41 {
42 
43 class BaseCPU;
44 
45 GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
46 namespace fastmodel
47 {
48 
49 // The fast model exports a class called scx_evs_CortexR52x1 which represents
50 // the subsystem described in LISA+. This class specializes it to export gem5
51 // ports and interface with its peer gem5 CPU. The gem5 CPU inherits from the
52 // gem5 BaseCPU class and implements its API, while this class actually does
53 // the work.
54 class CortexR52Cluster;
55 
56 class CortexR52 : public Iris::CPU<CortexR52TC>
57 {
58  protected:
60 
62  int num = 0;
63 
64  public:
65  PARAMS(FastModelCortexR52);
66  CortexR52(const Params &p) :
67  Base(p, scx::scx_get_iris_connection_interface())
68  {}
69 
70  template <class T>
71  void set_evs_param(const std::string &n, T val);
72 
73  void setCluster(CortexR52Cluster *_cluster, int _num);
74 
75  Port &getPort(const std::string &if_name,
76  PortID idx=InvalidPortID) override;
77 };
78 
80 {
81  private:
84 
85  public:
86  template <class T>
87  void
88  set_evs_param(const std::string &n, T val)
89  {
90  scx::scx_set_parameter(evs->name() + std::string(".") + n, val);
91  }
92 
93  CortexR52 *getCore(int num) const { return cores.at(num); }
94  sc_core::sc_module *getEvs() const { return evs; }
95 
96  PARAMS(FastModelCortexR52Cluster);
97  CortexR52Cluster(const Params &p);
98 
99  Port &getPort(const std::string &if_name,
100  PortID idx=InvalidPortID) override;
101 };
102 
103 template <class T>
104 inline void
105 CortexR52::set_evs_param(const std::string &n, T val)
106 {
107  for (auto &path: params().thread_paths)
108  cluster->set_evs_param(path + "." + n, val);
109 }
110 
111 } // namespace fastmodel
112 } // namespace gem5
113 
114 #endif // __ARCH_ARM_FASTMODEL_CORTEXR52_CORETEX_R52_HH__
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::fastmodel::CortexR52Cluster::evs
sc_core::sc_module * evs
Definition: cortex_r52.hh:83
gem5::fastmodel::CortexR52Cluster::getEvs
sc_core::sc_module * getEvs() const
Definition: cortex_r52.hh:94
sc_core::sc_module
Definition: sc_module.hh:98
gem5::Serializable::path
static std::stack< std::string > path
Definition: serialize.hh:315
gem5::fastmodel::CortexR52::setCluster
void setCluster(CortexR52Cluster *_cluster, int _num)
Definition: cortex_r52.cc:43
gem5::fastmodel::CortexR52::cluster
CortexR52Cluster * cluster
Definition: cortex_r52.hh:61
gem5::fastmodel::CortexR52::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_r52.cc:83
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::fastmodel::CortexR52::CortexR52
CortexR52(const Params &p)
Definition: cortex_r52.hh:66
std::vector
STL vector class.
Definition: stl.hh:37
gem5::fastmodel::CortexR52
Definition: cortex_r52.hh:56
gem5::fastmodel::CortexR52Cluster::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_r52.hh:88
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::fastmodel::CortexR52Cluster::getCore
CortexR52 * getCore(int num) const
Definition: cortex_r52.hh:93
gem5::fastmodel::CortexR52::PARAMS
PARAMS(FastModelCortexR52)
cpu.hh
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::fastmodel::CortexR52::num
int num
Definition: cortex_r52.hh:62
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::fastmodel::CortexR52Cluster::PARAMS
PARAMS(FastModelCortexR52Cluster)
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
thread_context.hh
gem5::fastmodel::CortexR52Cluster::cores
std::vector< CortexR52 * > cores
Definition: cortex_r52.hh:82
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
port.hh
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::fastmodel::CortexR52Cluster
Definition: cortex_r52.hh:79
sc_module.hh
amba_ports.hh
gem5::fastmodel::CortexR52::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_r52.hh:105
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmISA::n
Bitfield< 31 > n
Definition: misc_types.hh:455
gem5::fastmodel::CortexR52::Base
Iris::CPU< CortexR52TC > Base
Definition: cortex_r52.hh:59
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
gem5::Iris::CPU
Definition: cpu.hh:113
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::fastmodel::CortexR52Cluster::CortexR52Cluster
CortexR52Cluster(const Params &p)
Definition: cortex_r52.cc:99
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::fastmodel::CortexR52Cluster::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_r52.cc:149

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