gem5  v22.0.0.2
nativetrace.cc
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28 
30 
31 #include "arch/sparc/pcstate.hh"
32 #include "arch/sparc/regs/int.hh"
33 #include "cpu/thread_context.hh"
34 #include "params/SparcNativeTrace.hh"
35 #include "sim/byteswap.hh"
36 
37 namespace gem5
38 {
39 
40 namespace Trace {
41 
42 static const char *intRegNames[SparcISA::NumIntArchRegs] = {
43  // Global registers
44  "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
45  // Output registers
46  "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
47  // Local registers
48  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
49  // Input registers
50  "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
51 };
52 
53 void
55 {
56  ThreadContext *tc = record->getThread();
57 
58  uint64_t regVal, realRegVal;
59 
60  // Integer registers
61 
62  // I doubt a real SPARC will describe more integer registers than this.
63  assert(SparcISA::NumIntArchRegs == 32);
64  const char **regName = intRegNames;
65  for (int i = 0; i < SparcISA::NumIntArchRegs; i++) {
66  regVal = tc->readIntReg(i);
67  read(&realRegVal, sizeof(realRegVal));
68  realRegVal = betoh(realRegVal);
69  checkReg(*(regName++), regVal, realRegVal);
70  }
71 
72  auto &pc = tc->pcState().as<SparcISA::PCState>();
73  // PC
74  read(&realRegVal, sizeof(realRegVal));
75  realRegVal = betoh(realRegVal);
76  regVal = pc.npc();
77  checkReg("pc", regVal, realRegVal);
78 
79  // NPC
80  read(&realRegVal, sizeof(realRegVal));
81  realRegVal = betoh(realRegVal);
82  regVal = pc.nnpc();
83  checkReg("npc", regVal, realRegVal);
84 
85  // CCR
86  read(&realRegVal, sizeof(realRegVal));
87  realRegVal = betoh(realRegVal);
88  regVal = tc->readIntReg(SparcISA::INTREG_CCR);
89  checkReg("ccr", regVal, realRegVal);
90 }
91 
92 } // namespace Trace
93 } // namespace gem5
pcstate.hh
nativetrace.hh
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::Trace::intRegNames
static const char * intRegNames[SparcISA::NumIntArchRegs]
Definition: nativetrace.cc:42
gem5::betoh
T betoh(T value)
Definition: byteswap.hh:175
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::SparcISA::INTREG_CCR
@ INTREG_CCR
Definition: int.hh:59
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const
Definition: thread_context.hh:204
gem5::SparcISA::NumIntArchRegs
@ NumIntArchRegs
Definition: int.hh:55
gem5::Trace::SparcNativeTrace::check
void check(NativeTraceRecord *record)
Definition: nativetrace.cc:54
gem5::Trace::InstRecord::getThread
ThreadContext * getThread() const
Definition: insttracer.hh:272
int.hh
gem5::GenericISA::DelaySlotUPCState
Definition: pcstate.hh:530
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
thread_context.hh
gem5::Trace::NativeTraceRecord
Definition: nativetrace.hh:51
byteswap.hh

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