gem5  v22.0.0.1
faults.cc
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40 
41 #include "arch/x86/faults.hh"
42 
43 #include "arch/x86/generated/decoder.hh"
45 #include "arch/x86/mmu.hh"
46 #include "arch/x86/regs/misc.hh"
47 #include "base/loader/symtab.hh"
48 #include "base/trace.hh"
49 #include "cpu/thread_context.hh"
50 #include "debug/Faults.hh"
51 #include "sim/full_system.hh"
52 #include "sim/process.hh"
53 
54 namespace gem5
55 {
56 
57 namespace X86ISA
58 {
59 
60 void
62 {
63  if (!FullSystem) {
64  FaultBase::invoke(tc, inst);
65  return;
66  }
67 
68  PCState pc = tc->pcState().as<PCState>();
69  DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc.pc(), vector, describe());
70  using namespace X86ISAInst::rom_labels;
71  HandyM5Reg m5reg = tc->readMiscRegNoEffect(misc_reg::M5Reg);
72  MicroPC entry;
73  if (m5reg.mode == LongMode) {
74  entry = extern_label_longModeInterrupt;
75  } else {
76  if (m5reg.submode == RealMode)
77  entry = extern_label_realModeInterrupt;
78  else
79  entry = extern_label_legacyModeInterrupt;
80  }
81  tc->setReg(intRegMicro(1), vector);
83  tc->setReg(intRegMicro(7), pc.pc() - cs_base);
84  if (errorCode != (uint64_t)(-1)) {
85  if (m5reg.mode == LongMode) {
86  entry = extern_label_longModeInterruptWithError;
87  } else {
88  panic("Legacy mode interrupts with error codes "
89  "aren't implemented.");
90  }
91  tc->setReg(intRegMicro(15), errorCode);
92  }
93  pc.upc(romMicroPC(entry));
94  pc.nupc(romMicroPC(entry) + 1);
95  tc->pcState(pc);
96 }
97 
98 std::string
100 {
101  std::stringstream ss;
102  ccprintf(ss, "%s", mnemonic());
103  if (errorCode != (uint64_t)(-1))
104  ccprintf(ss, "(%#x)", errorCode);
105 
106  return ss.str();
107 }
108 
109 void
111 {
112  // This is the same as a fault, but it happens -after- the
113  // instruction.
115 }
116 
117 void
119 {
120  panic("Abort exception!");
121 }
122 
123 void
125 {
126  if (FullSystem) {
127  X86Fault::invoke(tc, inst);
128  } else {
129  auto *xsi = static_cast<X86StaticInst *>(inst.get());
130  panic("Unrecognized/invalid instruction executed:\n %s",
131  xsi->machInst);
132  }
133 }
134 
135 void
137 {
138  if (FullSystem) {
139  // Invalidate any matching TLB entries before handling the page fault.
140  tc->getMMUPtr()->demapPage(addr, 0);
141  HandyM5Reg m5reg = tc->readMiscRegNoEffect(misc_reg::M5Reg);
143  // If something bad happens while trying to enter the page fault
144  // handler, I'm pretty sure that's a double fault and then all
145  // bets are off. That means it should be safe to update this
146  // state now.
147  if (m5reg.mode == LongMode)
149  else
150  tc->setMiscReg(misc_reg::Cr2, (uint32_t)addr);
151  } else if (!tc->getProcessPtr()->fixupFault(addr)) {
152  PageFaultErrorCode code = errorCode;
153  const char *modeStr = "";
154  if (code.fetch)
155  modeStr = "execute";
156  else if (code.write)
157  modeStr = "write";
158  else
159  modeStr = "read";
160 
161  // print information about what we are panic'ing on
162  if (!inst) {
163  panic("Tried to %s unmapped address %#x.", modeStr, addr);
164  } else {
165  panic("Tried to %s unmapped address %#x.\nPC: %#x, Instr: %s",
166  modeStr, addr, tc->pcState(),
167  inst->disassemble(tc->pcState().instAddr(),
169  }
170  }
171 }
172 
173 std::string
175 {
176  std::stringstream ss;
177  ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
178  return ss.str();
179 }
180 
181 void
183 {
184  DPRINTF(Faults, "Init interrupt.\n");
185  // The otherwise unmodified integer registers should be set to 0.
186  for (int index = 0; index < int_reg::NumArchRegs; index++) {
187  tc->setReg(RegId(IntRegClass, index), (RegVal)0);
188  }
189 
190  CR0 cr0 = tc->readMiscReg(misc_reg::Cr0);
191  CR0 newCR0 = 1 << 4;
192  newCR0.cd = cr0.cd;
193  newCR0.nw = cr0.nw;
194  tc->setMiscReg(misc_reg::Cr0, newCR0);
195  tc->setMiscReg(misc_reg::Cr2, 0);
196  tc->setMiscReg(misc_reg::Cr3, 0);
197  tc->setMiscReg(misc_reg::Cr4, 0);
198 
199  tc->setMiscReg(misc_reg::Rflags, 0x0000000000000002ULL);
200 
201  tc->setMiscReg(misc_reg::Efer, 0);
202 
203  SegAttr dataAttr = 0;
204  dataAttr.dpl = 0;
205  dataAttr.unusable = 0;
206  dataAttr.defaultSize = 0;
207  dataAttr.longMode = 0;
208  dataAttr.avl = 0;
209  dataAttr.granularity = 0;
210  dataAttr.present = 1;
211  dataAttr.type = 3;
212  dataAttr.writable = 1;
213  dataAttr.readable = 1;
214  dataAttr.expandDown = 0;
215  dataAttr.system = 1;
216 
217  for (int seg = 0; seg != segment_idx::NumIdxs; seg++) {
221  tc->setMiscReg(misc_reg::segLimit(seg), 0xffff);
222  tc->setMiscReg(misc_reg::segAttr(seg), dataAttr);
223  }
224 
225  SegAttr codeAttr = 0;
226  codeAttr.dpl = 0;
227  codeAttr.unusable = 0;
228  codeAttr.defaultSize = 0;
229  codeAttr.longMode = 0;
230  codeAttr.avl = 0;
231  codeAttr.granularity = 0;
232  codeAttr.present = 1;
233  codeAttr.type = 10;
234  codeAttr.writable = 0;
235  codeAttr.readable = 1;
236  codeAttr.expandDown = 0;
237  codeAttr.system = 1;
238 
239  tc->setMiscReg(misc_reg::Cs, 0xf000);
240  tc->setMiscReg(misc_reg::CsBase, 0x00000000ffff0000ULL);
241  tc->setMiscReg(misc_reg::CsEffBase, 0x00000000ffff0000ULL);
242  // This has the base value pre-added.
243  tc->setMiscReg(misc_reg::CsLimit, 0xffffffff);
244  tc->setMiscReg(misc_reg::CsAttr, codeAttr);
245 
246  PCState pc(0x000000000000fff0ULL + tc->readMiscReg(misc_reg::CsBase));
247  tc->pcState(pc);
248 
250  tc->setMiscReg(misc_reg::TsgLimit, 0xffff);
251 
253  tc->setMiscReg(misc_reg::IdtrLimit, 0xffff);
254 
255  SegAttr tslAttr = 0;
256  tslAttr.unusable = 1;
257  tslAttr.present = 1;
258  tslAttr.type = 2; // LDT
259  tc->setMiscReg(misc_reg::Tsl, 0);
261  tc->setMiscReg(misc_reg::TslLimit, 0xffff);
262  tc->setMiscReg(misc_reg::TslAttr, tslAttr);
263 
264  SegAttr trAttr = 0;
265  trAttr.unusable = 0;
266  trAttr.present = 1;
267  trAttr.type = 3; // Busy 16-bit TSS
268  tc->setMiscReg(misc_reg::Tr, 0);
270  tc->setMiscReg(misc_reg::TrLimit, 0xffff);
271  tc->setMiscReg(misc_reg::TrAttr, trAttr);
272 
273  // This value should be the family/model/stepping of the processor.
274  // (page 418). It should be consistent with the value from CPUID, but
275  // the actual value probably doesn't matter much.
276  tc->setReg(int_reg::Rdx, (RegVal)0);
277 
278  tc->setMiscReg(misc_reg::Dr0, 0);
279  tc->setMiscReg(misc_reg::Dr1, 0);
280  tc->setMiscReg(misc_reg::Dr2, 0);
281  tc->setMiscReg(misc_reg::Dr3, 0);
282 
283  tc->setMiscReg(misc_reg::Dr6, 0x00000000ffff0ff0ULL);
284  tc->setMiscReg(misc_reg::Dr7, 0x0000000000000400ULL);
285 
286  tc->setMiscReg(misc_reg::Mxcsr, 0x1f80);
287 
288  // Flag all elements on the x87 stack as empty.
289  tc->setMiscReg(misc_reg::Ftw, 0xFFFF);
290 
291  // Update the handy M5 Reg.
292  tc->setMiscReg(misc_reg::M5Reg, 0);
293  MicroPC entry = X86ISAInst::rom_labels::extern_label_initIntHalt;
294  pc.upc(romMicroPC(entry));
295  pc.nupc(romMicroPC(entry) + 1);
296  tc->pcState(pc);
297 }
298 
299 void
301 {
302  DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
303  HandyM5Reg m5Reg = tc->readMiscReg(misc_reg::M5Reg);
304  if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
305  panic("Startup IPI recived outside of real mode. "
306  "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
307  }
308 
309  tc->setMiscReg(misc_reg::Cs, vector << 8);
310  tc->setMiscReg(misc_reg::CsBase, vector << 12);
312  // This has the base value pre-added.
313  tc->setMiscReg(misc_reg::CsLimit, 0xffff);
314 
316 }
317 
318 } // namespace X86ISA
319 } // namespace gem5
gem5::X86ISA::misc_reg::Dr7
@ Dr7
Definition: misc.hh:140
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:805
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::X86ISA::misc_reg::TslAttr
@ TslAttr
Definition: misc.hh:378
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::X86ISA::misc_reg::Ftw
@ Ftw
Definition: misc.hh:391
mmu.hh
static_inst.hh
gem5::X86ISA::misc_reg::M5Reg
@ M5Reg
Definition: misc.hh:146
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::X86ISA::X86FaultBase::vector
uint8_t vector
Definition: faults.hh:61
gem5::X86ISA::X86FaultBase::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:61
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::X86ISA::misc_reg::Dr6
@ Dr6
Definition: misc.hh:139
gem5::X86ISA::misc_reg::CsBase
@ CsBase
Definition: misc.hh:322
gem5::X86ISA::misc_reg::CsLimit
@ CsLimit
Definition: misc.hh:356
gem5::X86ISA::misc_reg::Tr
@ Tr
Definition: misc.hh:316
gem5::X86ISA::misc_reg::segEffBase
static RegIndex segEffBase(int index)
Definition: misc.hh:517
gem5::X86ISA::misc_reg::segAttr
static RegIndex segAttr(int index)
Definition: misc.hh:531
gem5::X86ISA::InvalidOpcode::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:124
gem5::RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
gem5::X86ISA::InitInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:182
gem5::X86ISA::misc_reg::CsEffBase
@ CsEffBase
Definition: misc.hh:340
faults.hh
gem5::X86ISA::X86FaultBase::errorCode
uint64_t errorCode
Definition: faults.hh:62
gem5::X86ISA::misc_reg::Dr1
@ Dr1
Definition: misc.hh:134
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::X86ISA::misc_reg::Dr0
@ Dr0
Definition: misc.hh:133
gem5::RefCountingPtr< StaticInst >
gem5::X86ISA::misc_reg::Dr2
@ Dr2
Definition: misc.hh:135
gem5::X86ISA::misc_reg::TsgBase
@ TsgBase
Definition: misc.hh:329
gem5::Process::fixupFault
bool fixupFault(Addr vaddr)
Attempt to fix up a fault at vaddr by allocating a page on the stack.
Definition: process.cc:365
gem5::X86ISA::misc_reg::segSel
static RegIndex segSel(int index)
Definition: misc.hh:503
gem5::X86ISA::misc_reg::TrAttr
@ TrAttr
Definition: misc.hh:382
gem5::X86ISA::misc_reg::segBase
static RegIndex segBase(int index)
Definition: misc.hh:510
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::X86ISA::misc_reg::Cr0
@ Cr0
Definition: misc.hh:114
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::misc_reg::Mxcsr
@ Mxcsr
Definition: misc.hh:388
process.hh
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:97
gem5::X86ISA::misc_reg::TslBase
@ TslBase
Definition: misc.hh:328
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::X86ISA::misc_reg::Cr2
@ Cr2
Definition: misc.hh:116
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::X86ISA::misc_reg::Tsl
@ Tsl
Definition: misc.hh:312
gem5::X86ISA::misc_reg::Cr3
@ Cr3
Definition: misc.hh:117
gem5::X86ISA::PageFault::describe
virtual std::string describe() const
Definition: faults.cc:174
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::misc_reg::Cr4
@ Cr4
Definition: misc.hh:118
gem5::X86ISA::misc_reg::Cs
@ Cs
Definition: misc.hh:306
gem5::X86ISA::StartupInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:300
gem5::FaultBase::invoke
virtual void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:58
full_system.hh
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::X86ISA::misc_reg::Dr3
@ Dr3
Definition: misc.hh:136
gem5::X86ISA::misc_reg::IdtrBase
@ IdtrBase
Definition: misc.hh:333
gem5::X86ISA::X86StaticInst
Base class for all X86 static instructions.
Definition: static_inst.hh:100
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:60
gem5::X86ISA::misc_reg::TsgLimit
@ TsgLimit
Definition: misc.hh:363
gem5::PowerISA::float_reg::NumArchRegs
const int NumArchRegs
Definition: float.hh:41
gem5::X86ISA::intRegMicro
static constexpr RegId intRegMicro(int index)
Definition: int.hh:152
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::X86ISA::seg
Bitfield< 2, 0 > seg
Definition: types.hh:87
gem5::X86ISA::PCState
Definition: pcstate.hh:50
gem5::X86ISA::RealMode
@ RealMode
Definition: types.hh:208
gem5::X86ISA::misc_reg::Rflags
@ Rflags
Definition: misc.hh:143
gem5::romMicroPC
static MicroPC romMicroPC(MicroPC upc)
Definition: types.hh:154
trace.hh
gem5::X86ISA::misc_reg::TslLimit
@ TslLimit
Definition: misc.hh:362
symtab.hh
gem5::X86ISA::X86Abort::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:118
gem5::loader::debugSymbolTable
SymbolTable debugSymbolTable
Global unified debugging symbol table (for target).
Definition: symtab.cc:44
gem5::X86ISA::misc_reg::IdtrLimit
@ IdtrLimit
Definition: misc.hh:367
gem5::X86ISA::segment_idx::NumIdxs
@ NumIdxs
Definition: segment.hh:67
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::misc_reg::TrLimit
@ TrLimit
Definition: misc.hh:366
gem5::X86ISA::misc_reg::Efer
@ Efer
Definition: misc.hh:254
gem5::X86ISA::misc_reg::CsAttr
@ CsAttr
Definition: misc.hh:372
misc.hh
gem5::X86ISA::X86Trap::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:110
gem5::X86ISA::misc_reg::segLimit
static RegIndex segLimit(int index)
Definition: misc.hh:524
gem5::X86ISA::X86FaultBase::mnemonic
virtual const char * mnemonic() const
Definition: faults.hh:72
thread_context.hh
gem5::X86ISA::misc_reg::TrBase
@ TrBase
Definition: misc.hh:332
gem5::X86ISA::X86FaultBase::describe
virtual std::string describe() const
Definition: faults.cc:99
gem5::X86ISA::PageFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:136
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183

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