gem5  v21.1.0.2
faults.cc
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40 
41 #include "arch/x86/faults.hh"
42 
43 #include "arch/x86/generated/decoder.hh"
45 #include "arch/x86/mmu.hh"
46 #include "base/loader/symtab.hh"
47 #include "base/trace.hh"
48 #include "cpu/thread_context.hh"
49 #include "debug/Faults.hh"
50 #include "sim/full_system.hh"
51 #include "sim/process.hh"
52 
53 namespace gem5
54 {
55 
56 namespace X86ISA
57 {
58 
59 void
61 {
62  if (!FullSystem) {
63  FaultBase::invoke(tc, inst);
64  return;
65  }
66 
67  PCState pcState = tc->pcState();
68  Addr pc = pcState.pc();
69  DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
70  using namespace X86ISAInst::rom_labels;
71  HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
72  MicroPC entry;
73  if (m5reg.mode == LongMode) {
74  entry = isSoft() ? extern_label_longModeSoftInterrupt :
75  extern_label_longModeInterrupt;
76  } else {
77  entry = extern_label_legacyModeInterrupt;
78  }
79  tc->setIntReg(INTREG_MICRO(1), vector);
80  tc->setIntReg(INTREG_MICRO(7), pc);
81  if (errorCode != (uint64_t)(-1)) {
82  if (m5reg.mode == LongMode) {
83  entry = extern_label_longModeInterruptWithError;
84  } else {
85  panic("Legacy mode interrupts with error codes "
86  "aren't implemented.");
87  }
88  // Software interrupts shouldn't have error codes. If one
89  // does, there would need to be microcode to set it up.
90  assert(!isSoft());
92  }
93  pcState.upc(romMicroPC(entry));
94  pcState.nupc(romMicroPC(entry) + 1);
95  tc->pcState(pcState);
96 }
97 
98 std::string
100 {
101  std::stringstream ss;
102  ccprintf(ss, "%s", mnemonic());
103  if (errorCode != (uint64_t)(-1))
104  ccprintf(ss, "(%#x)", errorCode);
105 
106  return ss.str();
107 }
108 
109 void
111 {
113  if (!FullSystem)
114  return;
115 
116  // This is the same as a fault, but it happens -after- the
117  // instruction.
118  PCState pc = tc->pcState();
119  pc.uEnd();
120 }
121 
122 void
124 {
125  panic("Abort exception!");
126 }
127 
128 void
130 {
131  if (FullSystem) {
132  X86Fault::invoke(tc, inst);
133  } else {
134  auto *xsi = static_cast<X86StaticInst *>(inst.get());
135  panic("Unrecognized/invalid instruction executed:\n %s",
136  xsi->machInst);
137  }
138 }
139 
140 void
142 {
143  if (FullSystem) {
144  // Invalidate any matching TLB entries before handling the page fault.
145  tc->getMMUPtr()->demapPage(addr, 0);
146  HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
148  // If something bad happens while trying to enter the page fault
149  // handler, I'm pretty sure that's a double fault and then all
150  // bets are off. That means it should be safe to update this
151  // state now.
152  if (m5reg.mode == LongMode)
154  else
155  tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
156  } else if (!tc->getProcessPtr()->fixupFault(addr)) {
157  PageFaultErrorCode code = errorCode;
158  const char *modeStr = "";
159  if (code.fetch)
160  modeStr = "execute";
161  else if (code.write)
162  modeStr = "write";
163  else
164  modeStr = "read";
165 
166  // print information about what we are panic'ing on
167  if (!inst) {
168  panic("Tried to %s unmapped address %#x.", modeStr, addr);
169  } else {
170  panic("Tried to %s unmapped address %#x.\nPC: %#x, Instr: %s",
171  modeStr, addr, tc->pcState().pc(),
172  inst->disassemble(tc->pcState().pc(),
174  }
175  }
176 }
177 
178 std::string
180 {
181  std::stringstream ss;
182  ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
183  return ss.str();
184 }
185 
186 void
188 {
189  DPRINTF(Faults, "Init interrupt.\n");
190  // The otherwise unmodified integer registers should be set to 0.
191  for (int index = 0; index < NUM_ARCH_INTREGS; index++) {
192  tc->setIntReg(index, 0);
193  }
194 
195  CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
196  CR0 newCR0 = 1 << 4;
197  newCR0.cd = cr0.cd;
198  newCR0.nw = cr0.nw;
199  tc->setMiscReg(MISCREG_CR0, newCR0);
200  tc->setMiscReg(MISCREG_CR2, 0);
201  tc->setMiscReg(MISCREG_CR3, 0);
202  tc->setMiscReg(MISCREG_CR4, 0);
203 
204  tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
205 
206  tc->setMiscReg(MISCREG_EFER, 0);
207 
208  SegAttr dataAttr = 0;
209  dataAttr.dpl = 0;
210  dataAttr.unusable = 0;
211  dataAttr.defaultSize = 0;
212  dataAttr.longMode = 0;
213  dataAttr.avl = 0;
214  dataAttr.granularity = 0;
215  dataAttr.present = 1;
216  dataAttr.type = 3;
217  dataAttr.writable = 1;
218  dataAttr.readable = 1;
219  dataAttr.expandDown = 0;
220  dataAttr.system = 1;
221 
222  for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
223  tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
226  tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
227  tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
228  }
229 
230  SegAttr codeAttr = 0;
231  codeAttr.dpl = 0;
232  codeAttr.unusable = 0;
233  codeAttr.defaultSize = 0;
234  codeAttr.longMode = 0;
235  codeAttr.avl = 0;
236  codeAttr.granularity = 0;
237  codeAttr.present = 1;
238  codeAttr.type = 10;
239  codeAttr.writable = 0;
240  codeAttr.readable = 1;
241  codeAttr.expandDown = 0;
242  codeAttr.system = 1;
243 
244  tc->setMiscReg(MISCREG_CS, 0xf000);
246  0x00000000ffff0000ULL);
248  0x00000000ffff0000ULL);
249  // This has the base value pre-added.
250  tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
251  tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
252 
253  PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
254  tc->pcState(pc);
255 
257  tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
258 
260  tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
261 
262  SegAttr tslAttr = 0;
263  tslAttr.present = 1;
264  tslAttr.type = 2; // LDT
265  tc->setMiscReg(MISCREG_TSL, 0);
267  tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
268  tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
269 
270  SegAttr trAttr = 0;
271  trAttr.present = 1;
272  trAttr.type = 3; // Busy 16-bit TSS
273  tc->setMiscReg(MISCREG_TR, 0);
274  tc->setMiscReg(MISCREG_TR_BASE, 0);
275  tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
276  tc->setMiscReg(MISCREG_TR_ATTR, trAttr);
277 
278  // This value should be the family/model/stepping of the processor.
279  // (page 418). It should be consistent with the value from CPUID, but
280  // the actual value probably doesn't matter much.
281  tc->setIntReg(INTREG_RDX, 0);
282 
283  tc->setMiscReg(MISCREG_DR0, 0);
284  tc->setMiscReg(MISCREG_DR1, 0);
285  tc->setMiscReg(MISCREG_DR2, 0);
286  tc->setMiscReg(MISCREG_DR3, 0);
287 
288  tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
289  tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
290 
291  tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
292 
293  // Flag all elements on the x87 stack as empty.
294  tc->setMiscReg(MISCREG_FTW, 0xFFFF);
295 
296  // Update the handy M5 Reg.
297  tc->setMiscReg(MISCREG_M5_REG, 0);
298  MicroPC entry = X86ISAInst::rom_labels::extern_label_initIntHalt;
299  pc.upc(romMicroPC(entry));
300  pc.nupc(romMicroPC(entry) + 1);
301  tc->pcState(pc);
302 }
303 
304 void
306 {
307  DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
308  HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
309  if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
310  panic("Startup IPI recived outside of real mode. "
311  "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
312  }
313 
314  tc->setMiscReg(MISCREG_CS, vector << 8);
315  tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
317  // This has the base value pre-added.
318  tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
319 
321 }
322 
323 } // namespace X86ISA
324 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:811
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::X86ISA::MISCREG_M5_REG
@ MISCREG_M5_REG
Definition: misc.hh:143
gem5::X86ISA::MISCREG_SEG_SEL
static MiscRegIndex MISCREG_SEG_SEL(int index)
Definition: misc.hh:511
gem5::X86ISA::MISCREG_TR
@ MISCREG_TR
Definition: misc.hh:313
gem5::X86ISA::MISCREG_DR1
@ MISCREG_DR1
Definition: misc.hh:131
mmu.hh
gem5::X86ISA::MISCREG_TSL
@ MISCREG_TSL
Definition: misc.hh:309
static_inst.hh
gem5::X86ISA::MISCREG_DR3
@ MISCREG_DR3
Definition: misc.hh:133
gem5::X86ISA::MISCREG_TSG_LIMIT
@ MISCREG_TSG_LIMIT
Definition: misc.hh:360
gem5::X86ISA::MISCREG_SEG_LIMIT
static MiscRegIndex MISCREG_SEG_LIMIT(int index)
Definition: misc.hh:532
gem5::X86ISA::X86FaultBase::vector
uint8_t vector
Definition: faults.hh:61
gem5::X86ISA::X86FaultBase::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:60
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::X86ISA::MISCREG_SEG_ATTR
static MiscRegIndex MISCREG_SEG_ATTR(int index)
Definition: misc.hh:539
gem5::X86ISA::InvalidOpcode::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:129
gem5::X86ISA::MISCREG_TR_BASE
@ MISCREG_TR_BASE
Definition: misc.hh:329
gem5::RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:227
gem5::X86ISA::InitInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:187
gem5::X86ISA::MISCREG_DR2
@ MISCREG_DR2
Definition: misc.hh:132
faults.hh
gem5::X86ISA::MISCREG_IDTR_BASE
@ MISCREG_IDTR_BASE
Definition: misc.hh:330
gem5::X86ISA::X86FaultBase::errorCode
uint64_t errorCode
Definition: faults.hh:62
gem5::X86ISA::MISCREG_CR3
@ MISCREG_CR3
Definition: misc.hh:114
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::RefCountingPtr< StaticInst >
gem5::Process::fixupFault
bool fixupFault(Addr vaddr)
Attempt to fix up a fault at vaddr by allocating a page on the stack.
Definition: process.cc:359
gem5::X86ISA::MISCREG_CR2
@ MISCREG_CR2
Definition: misc.hh:113
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::X86ISA::MISCREG_CS_BASE
@ MISCREG_CS_BASE
Definition: misc.hh:319
gem5::X86ISA::MISCREG_IDTR_LIMIT
@ MISCREG_IDTR_LIMIT
Definition: misc.hh:364
gem5::X86ISA::MISCREG_DR7
@ MISCREG_DR7
Definition: misc.hh:137
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::X86ISA::NUM_SEGMENTREGS
@ NUM_SEGMENTREGS
Definition: segment.hh:65
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
process.hh
gem5::X86ISA::MISCREG_DR0
@ MISCREG_DR0
Definition: misc.hh:130
gem5::X86ISA::MISCREG_CR4
@ MISCREG_CR4
Definition: misc.hh:115
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:58
gem5::X86ISA::MISCREG_CS_ATTR
@ MISCREG_CS_ATTR
Definition: misc.hh:369
gem5::X86ISA::MISCREG_EFER
@ MISCREG_EFER
Definition: misc.hh:251
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::X86ISA::MISCREG_SEG_BASE
static MiscRegIndex MISCREG_SEG_BASE(int index)
Definition: misc.hh:518
gem5::X86ISA::MISCREG_CS_LIMIT
@ MISCREG_CS_LIMIT
Definition: misc.hh:353
gem5::X86ISA::MISCREG_RFLAGS
@ MISCREG_RFLAGS
Definition: misc.hh:140
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::X86ISA::MISCREG_TSL_ATTR
@ MISCREG_TSL_ATTR
Definition: misc.hh:375
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::X86ISA::MISCREG_TSL_BASE
@ MISCREG_TSL_BASE
Definition: misc.hh:325
gem5::X86ISA::PageFault::describe
virtual std::string describe() const
Definition: faults.cc:179
gem5::X86ISA::MISCREG_DR6
@ MISCREG_DR6
Definition: misc.hh:136
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::MISCREG_MXCSR
@ MISCREG_MXCSR
Definition: misc.hh:386
gem5::X86ISA::StartupInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:305
gem5::FaultBase::invoke
virtual void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:59
full_system.hh
gem5::X86ISA::INTREG_MICRO
static IntRegIndex INTREG_MICRO(int index)
Definition: int.hh:175
gem5::X86ISA::MISCREG_CS
@ MISCREG_CS
Definition: misc.hh:303
gem5::X86ISA::MISCREG_CS_EFF_BASE
@ MISCREG_CS_EFF_BASE
Definition: misc.hh:337
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::X86ISA::MISCREG_TSG_BASE
@ MISCREG_TSG_BASE
Definition: misc.hh:326
gem5::X86ISA::MISCREG_TR_LIMIT
@ MISCREG_TR_LIMIT
Definition: misc.hh:363
gem5::X86ISA::X86StaticInst
Base class for all X86 static instructions.
Definition: static_inst.hh:97
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:75
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::MISCREG_SEG_EFF_BASE
static MiscRegIndex MISCREG_SEG_EFF_BASE(int index)
Definition: misc.hh:525
gem5::GenericISA::UPCState::nupc
MicroPC nupc() const
Definition: types.hh:211
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::X86ISA::seg
Bitfield< 2, 0 > seg
Definition: types.hh:87
gem5::X86ISA::MISCREG_CR0
@ MISCREG_CR0
Definition: misc.hh:111
gem5::X86ISA::PCState
Definition: pcstate.hh:50
gem5::X86ISA::RealMode
@ RealMode
Definition: types.hh:202
gem5::X86ISA::X86FaultBase::isSoft
virtual bool isSoft()
Definition: faults.hh:73
gem5::X86ISA::MISCREG_TR_ATTR
@ MISCREG_TR_ATTR
Definition: misc.hh:379
gem5::romMicroPC
static MicroPC romMicroPC(MicroPC upc)
Definition: types.hh:154
trace.hh
gem5::X86ISA::MISCREG_FTW
@ MISCREG_FTW
Definition: misc.hh:389
gem5::GenericISA::UPCState::upc
MicroPC upc() const
Definition: types.hh:208
symtab.hh
gem5::X86ISA::X86Abort::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:123
gem5::loader::debugSymbolTable
SymbolTable debugSymbolTable
Global unified debugging symbol table (for target).
Definition: symtab.cc:44
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::MISCREG_TSL_LIMIT
@ MISCREG_TSL_LIMIT
Definition: misc.hh:359
gem5::X86ISA::X86Trap::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:110
gem5::GenericISA::SimplePCState::pc
Addr pc() const
Definition: types.hh:151
gem5::X86ISA::X86FaultBase::mnemonic
virtual const char * mnemonic() const
Definition: faults.hh:72
thread_context.hh
gem5::X86ISA::X86FaultBase::describe
virtual std::string describe() const
Definition: faults.cc:99
gem5::X86ISA::PageFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:141
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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