gem5  v21.1.0.2
isa.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
29 #define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
30 
31 #include "arch/arm/utility.hh"
32 #include "arch/generic/isa.hh"
33 
34 namespace gem5
35 {
36 
37 namespace Iris
38 {
39 
40 class ISA : public BaseISA
41 {
42  public:
43  ISA(const Params &p) : BaseISA(p) {}
44 
45  void serialize(CheckpointOut &cp) const override;
46 
47  void copyRegsFrom(ThreadContext *src) override;
48 
49  bool
50  inUserMode() const override
51  {
52  ArmISA::CPSR cpsr = tc->readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
53  return ArmISA::inUserMode(cpsr);
54  }
55 };
56 
57 } // namespace Iris
58 } // namespace gem5
59 
60 #endif // __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:62
gem5::Iris::ISA
Definition: isa.hh:40
gem5::Iris::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:50
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::Iris::ThreadContext
Definition: thread_context.hh:51
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Iris::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:48
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
utility.hh
isa.hh
gem5::ArmISA::inUserMode
static bool inUserMode(CPSR cpsr)
Definition: utility.hh:96
gem5::Iris::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:39
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::BaseISA
Definition: isa.hh:54
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Iris::ISA::ISA
ISA(const Params &p)
Definition: isa.hh:43

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