gem5 v24.0.0.0
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fs_workload.cc
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1/*
2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by the University of Cambridge Computer
6 * Laboratory as part of the CTSRD Project, with support from the UK Higher
7 * Education Innovation Fund (HEIF).
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are
11 * met: redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer;
13 * redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution;
16 * neither the name of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
34
35#include "arch/arm/utility.hh"
39#include "base/loader/symtab.hh"
40#include "cpu/base.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Loader.hh"
45#include "mem/physical.hh"
46#include "sim/stat_control.hh"
47
48namespace gem5
49{
50
51using namespace free_bsd;
52
53namespace ArmISA
54{
55
57 enableContextSwitchStatsDump(p.enable_context_switch_stats_dump)
58{
59 if (p.panic_on_panic) {
61 "panic", "Kernel panic in simulated kernel");
62 } else {
63#ifndef NDEBUG
65#endif
66 }
67
68 if (p.panic_on_oops) {
70 "oops_exit", "Kernel oops in guest");
71 }
72
73 skipUDelay = addSkipFunc<SkipUDelay>("DELAY", "DELAY", 1000, 0);
74}
75
76void
78{
80
81 // Load symbols at physical address, we might not want
82 // to do this permanently, for but early bootup work
83 // it is helpful.
84 if (params().early_kernel_symbols) {
85 auto phys_globals = kernelObj->symtab().globals()->mask(_loadAddrMask);
86 kernelSymtab.insert(*phys_globals);
87 loader::debugSymbolTable.insert(*phys_globals);
88 }
89
90 // Check if the kernel image has a symbol that tells us it supports
91 // device trees.
92 fatal_if(kernelSymtab.find("fdt_get_range") == kernelSymtab.end(),
93 "Kernel must have fdt support.");
94 fatal_if(params().dtb_filename == "", "dtb file is not specified.");
95
96 // Kernel supports flattened device tree and dtb file specified.
97 // Using Device Tree Blob to describe system configuration.
98 inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
99 params().dtb_addr);
100
101 auto *dtb_file = new loader::DtbFile(params().dtb_filename);
102
103 warn_if(!dtb_file->addBootCmdLine(commandLine.c_str(), commandLine.size()),
104 "Couldn't append bootargs to DTB file: %s",
105 params().dtb_filename);
106
107 Addr ra = dtb_file->findReleaseAddr();
108 if (ra)
109 bootReleaseAddr = ra & ~0x7FULL;
110
111 dtb_file->buildImage().
112 offset(params().dtb_addr).
113 write(system->physProxy);
114 delete dtb_file;
115
116 // Kernel boot requirements to set up r0, r1 and r2 in ARMv7
117 for (auto *tc: system->threads) {
118 tc->setReg(int_reg::R0, (RegVal)0);
119 tc->setReg(int_reg::R1, params().machine_type);
120 tc->setReg(int_reg::R2, params().dtb_addr);
121 }
122}
123
125{
126 delete skipUDelay;
127}
128
129} // namespace ArmISA
130} // namespace gem5
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
FsFreebsd(const Params &p)
PCEvent * kernelOops
Event to halt the simulator if the kernel calls oopses
PCEvent * skipUDelay
PC based event to skip udelay(<time>) calls and quiesce the processor for the appropriate amount of t...
PCEvent * kernelPanic
Event to halt the simulator if the kernel calls panic()
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
PCEvent * addSkipFunc(Args... args)
loader::SymbolTable kernelSymtab
const std::string commandLine
loader::ObjectFile * kernelObj
T * addKernelFuncEventOrPanic(const char *lbl, Args... args)
Addr _loadAddrMask
Mask that should be anded for binary/symbol loading.
SimObjectParams Params
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition system.hh:323
Threads threads
Definition system.hh:310
System * system
Definition workload.hh:81
const SymbolTable & symtab() const
SymbolTablePtr globals() const
Generates a new symbol table containing only global symbols.
Definition symtab.hh:369
const_iterator end() const
Definition symtab.hh:278
bool insert(const Symbol &symbol)
Insert a new symbol in the table if it does not already exist.
Definition symtab.cc:66
const_iterator find(Addr address) const
Search for a symbol by its address.
Definition symtab.hh:435
This implements an image file format to support loading and modifying flattened device tree blobs for...
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition logging.hh:236
const Params & params() const
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition logging.hh:283
#define inform(...)
Definition logging.hh:257
constexpr RegId R2
Definition int.hh:188
constexpr RegId R1
Definition int.hh:187
constexpr RegId R0
Definition int.hh:186
Bitfield< 23, 0 > offset
Definition types.hh:144
Bitfield< 0 > p
Bitfield< 20, 16 > ra
Definition types.hh:50
SymbolTable debugSymbolTable
Global unified debugging symbol table (for target).
Definition symtab.cc:55
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t RegVal
Definition types.hh:173
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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