gem5 v24.0.0.0
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fs_workload.cc
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1/*
2 * Copyright (c) 2010, 2012-2013, 2015,2017-2020 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
42
43#include "arch/arm/faults.hh"
45#include "base/loader/symtab.hh"
46#include "cpu/thread_context.hh"
47#include "dev/arm/gic_v2.hh"
48#include "kern/system_events.hh"
49#include "params/ArmFsWorkload.hh"
50
51namespace gem5
52{
53
54namespace ArmISA
55{
56
57void
59{
60 PCState new_pc = tc->pcState().as<PCState>();
61 if (inAArch64(tc)) {
62 new_pc.set(tc->getReg(int_reg::X30));
63 } else {
64 new_pc.set(tc->getReg(ReturnAddressReg) & ~1ULL);
65 }
66
67 CheckerCPU *checker = tc->getCheckerCpuPtr();
68 if (checker) {
69 tc->pcStateNoRecord(new_pc);
70 } else {
71 tc->pcState(new_pc);
72 }
73}
74
76{
77 if (kernelObj) {
80 }
81
82 bootLoaders.reserve(p.boot_loader.size());
83 for (const auto &bl : p.boot_loader) {
84 std::unique_ptr<loader::ObjectFile> bl_obj;
85 bl_obj.reset(loader::createObjectFile(bl));
86
87 fatal_if(!bl_obj, "Could not read bootloader: %s", bl);
88 bootLoaders.emplace_back(std::move(bl_obj));
89 }
90
92
93 fatal_if(!bootLoaders.empty() && !bootldr,
94 "Can't find a matching boot loader / kernel combination!");
95
96 if (bootldr)
98}
99
100void
102{
104
105 // Reset CP15?? What does that mean -- ali
106
107 // FPEXC.EN = 0
108
109 for (auto *tc: system->threads) {
110 Reset().invoke(tc);
111 tc->activate();
112 }
113
114 auto *arm_sys = dynamic_cast<ArmSystem *>(system);
115
116 if (bootldr) {
117 bool is_gic_v2 =
120
121 inform("Using bootloader at address %#x", bootldr->entryPoint());
122
123 // The address of the boot loader so we know
124 // where to branch to after the reset fault
125 // All other values needed by the boot loader to know what to do
126 fatal_if(!params().cpu_release_addr,
127 "cpu_release_addr must be set with bootloader");
128
129 fatal_if(!arm_sys->params().gic_cpu_addr && is_gic_v2,
130 "gic_cpu_addr must be set with bootloader");
131
132 for (auto *tc: arm_sys->threads) {
133 tc->setReg(int_reg::R3, kernelEntry);
134 if (is_gic_v2)
135 tc->setReg(int_reg::R4, arm_sys->params().gic_cpu_addr);
136 if (getArch() == loader::Arm)
137 tc->setReg(int_reg::R5, params().cpu_release_addr);
138 }
139 inform("Using kernel entry physical address at %#x\n", kernelEntry);
140 } else {
141 // Set the initial PC to be at start of the kernel code
142 if (!arm_sys->highestELIs64())
143 arm_sys->threads[0]->pcState(kernelObj->entryPoint());
144 }
145}
146
149{
150 if (obj) {
151 for (auto &bl : bootLoaders) {
152 if (bl->getArch() == obj->getArch())
153 return bl.get();
154 }
155 } else if (!bootLoaders.empty()) {
156 return bootLoaders[0].get();
157 }
158
159 return nullptr;
160}
161
162} // namespace ArmISA
163} // namespace gem5
loader::ObjectFile * getBootLoader(loader::ObjectFile *const obj)
Get a boot loader that matches the kernel.
loader::ObjectFile * bootldr
Pointer to the bootloader object.
loader::Arch getArch() const override
std::vector< std::unique_ptr< loader::ObjectFile > > bootLoaders
Bootloaders.
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Addr kernelEntry
This differs from entry since it takes into account where the kernel is loaded in memory (with loadAd...
FsWorkload(const Params &p)
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition faults.cc:741
void returnFromFuncIn(ThreadContext *tc) override
BaseGic * getGIC() const
Get a pointer to the system's GIC.
Definition system.hh:180
virtual bool supportsVersion(GicVersion version)=0
Check if version supported.
CheckerCPU class.
Definition cpu.hh:85
void set(Addr val) override
Force this PC to reflect a particular value, resetting all its other fields around it.
Definition pcstate.hh:378
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
loader::ObjectFile * kernelObj
Addr loadAddrOffset() const
Target & as()
Definition pcstate.hh:73
SimObjectParams Params
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition system.hh:323
Threads threads
Definition system.hh:310
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual void pcStateNoRecord(const PCStateBase &val)=0
virtual RegVal getReg(const RegId &reg) const
virtual CheckerCPU * getCheckerCpuPtr()=0
virtual const PCStateBase & pcState() const =0
System * system
Definition workload.hh:81
virtual MemoryImage buildImage() const =0
bool write(const PortProxy &proxy) const
const SymbolTable & symtab() const
SymbolTablePtr globals() const
Generates a new symbol table containing only global symbols.
Definition symtab.hh:369
bool insert(const Symbol &symbol)
Insert a new symbol in the table if it does not already exist.
Definition symtab.cc:66
Implementation of a GICv2.
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition logging.hh:236
const Params & params() const
#define inform(...)
Definition logging.hh:257
constexpr RegId X30
Definition int.hh:270
constexpr RegId R4
Definition int.hh:190
constexpr RegId R3
Definition int.hh:189
constexpr RegId R5
Definition int.hh:191
constexpr auto & ReturnAddressReg
Definition int.hh:655
bool inAArch64(ThreadContext *tc)
Definition utility.cc:126
Bitfield< 0 > p
SymbolTable debugSymbolTable
Global unified debugging symbol table (for target).
Definition symtab.cc:55
ObjectFile * createObjectFile(const std::string &fname, bool raw)
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36

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