#include <interrupts.hh>

Inheritance diagram for gem5::X86ISA::Interrupts:

Public Types
using	Params = X86LocalApicParams

Public Types inherited from gem5::BaseInterrupts
using	Params = BaseInterruptsParams

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
int	getInitialApicId ()

void	setThreadContext (ThreadContext *_tc) override

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

Tick	read (PacketPtr pkt)

Tick	write (PacketPtr pkt)

Tick	recvMessage (PacketPtr pkt)

void	completeIPI (PacketPtr pkt)

bool	triggerTimerInterrupt ()

AddrRangeList	getAddrRanges () const

AddrRangeList	getIntAddrRange () const

void	raiseInterruptPin (int number)

void	lowerInterruptPin (int number)

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index. More...

uint32_t	readReg (ApicRegIndex miscReg)

void	setReg (ApicRegIndex reg, uint32_t val)

void	setRegNoEffect (ApicRegIndex reg, uint32_t val)

	Interrupts (const Params &p)

bool	checkInterrupts () const override

bool	checkInterruptsRaw () const
	Check if there are pending interrupts without ignoring the interrupts disabled flag. More...

bool	hasPendingUnmaskable () const
	Check if there are pending unmaskable interrupts. More...

Fault	getInterrupt () override

void	updateIntrInfo () override

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

void	post (int int_num, int index) override

void	clear (int int_num, int index) override

void	clearAll () override

Public Member Functions inherited from gem5::BaseInterrupts
	BaseInterrupts (const Params &p)

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters. More...

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (statistics::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Protected Member Functions
	BitUnion32 (LVTEntry) Bitfield< 7

	EndBitUnion (LVTEntry) EventFunctionWrapper apicTimerEvent

void	processApicTimerEvent ()

int	findRegArrayMSB (ApicRegIndex base)

void	updateIRRV ()

void	updateISRV ()

void	setRegArrayBit (ApicRegIndex base, uint8_t vector)

void	clearRegArrayBit (ApicRegIndex base, uint8_t vector)

bool	getRegArrayBit (ApicRegIndex base, uint8_t vector)

Tick	clockPeriod () const

void	requestInterrupt (uint8_t vector, uint8_t deliveryMode, bool level)

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes
System *	sys = nullptr

ClockDomain &	clockDomain

uint32_t	regs [NUM_APIC_REGS] = {}

	vector

Bitfield< 10, 8 >	deliveryMode

Bitfield< 12 >	status

Bitfield< 13 >	polarity

Bitfield< 14 >	remoteIRR

Bitfield< 15 >	trigger

Bitfield< 16 >	masked

Bitfield< 17 >	periodic

bool	pendingSmi = false

uint8_t	smiVector = 0

bool	pendingNmi = false

uint8_t	nmiVector = 0

bool	pendingExtInt = false

uint8_t	extIntVector = 0

bool	pendingInit = false

uint8_t	initVector = 0

bool	pendingStartup = false

uint8_t	startupVector = 0

bool	startedUp = false

bool	pendingUnmaskableInt = false

int	pendingIPIs = 0

uint8_t	IRRV = 0

uint8_t	ISRV = 0

int	initialApicId = 0

IntResponsePort< Interrupts >	intResponsePort

IntRequestPort< Interrupts >	intRequestPort

IntSinkPin< Interrupts >	lint0Pin

IntSinkPin< Interrupts >	lint1Pin

PioPort< Interrupts >	pioPort

Tick	pioDelay = 0

Addr	pioAddr = MaxAddr

Protected Attributes inherited from gem5::BaseInterrupts
ThreadContext *	tc = nullptr

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Additional Inherited Members
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Detailed Description

Definition at line 78 of file interrupts.hh.

Member Typedef Documentation

◆ Params

using gem5::X86ISA::Interrupts::Params = X86LocalApicParams

Definition at line 201 of file interrupts.hh.

Constructor & Destructor Documentation

◆ Interrupts()

gem5::X86ISA::Interrupts::Interrupts ( const Params & p )

Definition at line 635 of file interrupts.cc.

References processApicTimerEvent().

Member Function Documentation

◆ BitUnion32()

gem5::X86ISA::Interrupts::BitUnion32 ( LVTEntry )

protected

◆ checkInterrupts()

bool gem5::X86ISA::Interrupts::checkInterrupts ( ) const

overridevirtual

Implements gem5::BaseInterrupts.

Definition at line 666 of file interrupts.cc.

References gem5::X86ISA::APIC_TASK_PRIORITY, gem5::bits(), DPRINTF, and gem5::X86ISA::misc_reg::Rflags.

◆ checkInterruptsRaw()

bool gem5::X86ISA::Interrupts::checkInterruptsRaw ( ) const

Check if there are pending interrupts without ignoring the interrupts disabled flag.

Returns: true if there are interrupts pending.

Definition at line 688 of file interrupts.cc.

References gem5::X86ISA::APIC_TASK_PRIORITY, and gem5::bits().

◆ clear()

void gem5::X86ISA::Interrupts::clear	(	int	int_num,
		int	index
	)

inlineoverridevirtual

Reimplemented from gem5::BaseInterrupts.

Definition at line 308 of file interrupts.hh.

References panic.

◆ clearAll()

void gem5::X86ISA::Interrupts::clearAll ( )

inlineoverridevirtual

Reimplemented from gem5::BaseInterrupts.

Definition at line 314 of file interrupts.hh.

References panic.

◆ clearRegArrayBit()

void gem5::X86ISA::Interrupts::clearRegArrayBit	(	ApicRegIndex	base,
		uint8_t	vector
	)

inlineprotected

Definition at line 163 of file interrupts.hh.

References gem5::X86ISA::base, regs, and vector.

◆ clockPeriod()

Tick gem5::X86ISA::Interrupts::clockPeriod ( ) const

inlineprotected

Definition at line 174 of file interrupts.hh.

References clockDomain, and gem5::ClockDomain::clockPeriod().

◆ completeIPI()

void gem5::X86ISA::Interrupts::completeIPI ( PacketPtr pkt )

Definition at line 369 of file interrupts.cc.

References gem5::X86ISA::APIC_INTERRUPT_COMMAND_LOW, and DPRINTF.

◆ EndBitUnion()

gem5::X86ISA::Interrupts::EndBitUnion ( LVTEntry )

protected

◆ findRegArrayMSB()

int gem5::X86ISA::Interrupts::findRegArrayMSB ( ApicRegIndex base )

inlineprotected

Definition at line 133 of file interrupts.hh.

References gem5::X86ISA::base, gem5::findMsbSet(), gem5::X86ISA::offset, and regs.

Referenced by updateIRRV(), and updateISRV().

◆ getAddrRanges()

AddrRangeList gem5::X86ISA::Interrupts::getAddrRanges ( ) const

Definition at line 383 of file interrupts.cc.

References gem5::X86ISA::PageBytes, and gem5::RangeSize().

◆ getInitialApicId()

int gem5::X86ISA::Interrupts::getInitialApicId ( )

inline

Definition at line 196 of file interrupts.hh.

References initialApicId.

◆ getIntAddrRange()

AddrRangeList gem5::X86ISA::Interrupts::getIntAddrRange ( ) const

Definition at line 393 of file interrupts.cc.

References gem5::X86ISA::PhysAddrAPICRangeSize, gem5::RangeEx(), and gem5::X86ISA::x86InterruptAddress().

◆ getInterrupt()

Fault gem5::X86ISA::Interrupts::getInterrupt ( )

overridevirtual

Implements gem5::BaseInterrupts.

Definition at line 696 of file interrupts.cc.

References DPRINTF, gem5::NoFault, and panic.

◆ getPort()

Port& gem5::X86ISA::Interrupts::getPort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

inlineoverridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from gem5::SimObject.

Definition at line 234 of file interrupts.hh.

References gem5::SimObject::getPort(), intRequestPort, intResponsePort, lint0Pin, lint1Pin, and pioPort.

◆ getRegArrayBit()

bool gem5::X86ISA::Interrupts::getRegArrayBit	(	ApicRegIndex	base,
		uint8_t	vector
	)

inlineprotected

Definition at line 169 of file interrupts.hh.

References gem5::X86ISA::base, gem5::bits(), regs, and vector.

◆ hasPendingUnmaskable()

bool gem5::X86ISA::Interrupts::hasPendingUnmaskable ( ) const

inline

Check if there are pending unmaskable interrupts.

Returns: true there are unmaskable interrupts pending.

Definition at line 287 of file interrupts.hh.

References pendingUnmaskableInt.

◆ init()

void gem5::X86ISA::Interrupts::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::SimObject.

Definition at line 328 of file interrupts.cc.

References name(), and panic_if.

◆ lowerInterruptPin()

void gem5::X86ISA::Interrupts::lowerInterruptPin ( int number )

Definition at line 303 of file interrupts.cc.

References DPRINTF, and panic_if.

◆ post()

void gem5::X86ISA::Interrupts::post	(	int	int_num,
		int	index
	)

inlineoverridevirtual

Reimplemented from gem5::BaseInterrupts.

Definition at line 302 of file interrupts.hh.

References panic.

◆ processApicTimerEvent()

void gem5::X86ISA::Interrupts::processApicTimerEvent ( )

protected

Definition at line 822 of file interrupts.cc.

References gem5::X86ISA::APIC_INITIAL_COUNT, and gem5::guest_abi::setReg().

Referenced by Interrupts().

◆ raiseInterruptPin()

void gem5::X86ISA::Interrupts::raiseInterruptPin ( int number )

Definition at line 278 of file interrupts.cc.

References gem5::X86ISA::APIC_LVT_LINT0, gem5::X86ISA::APIC_LVT_LINT1, gem5::X86ISA::buildIntAcknowledgePacket(), gem5::MipsISA::dm, DPRINTF, gem5::Packet::getLE(), panic_if, and gem5::X86ISA::trigger.

◆ read()

Tick gem5::X86ISA::Interrupts::read ( PacketPtr pkt )

Definition at line 194 of file interrupts.cc.

References gem5::X86ISA::decodeAddr(), DPRINTF, gem5::Packet::getAddr(), gem5::Packet::getSize(), gem5::htole(), gem5::Packet::makeAtomicResponse(), gem5::X86ISA::mask, gem5::X86ISA::offset, panic, pioAddr, pioDelay, readReg(), gem5::X86ISA::reg, gem5::Packet::setData(), and gem5::X86ISA::val.

◆ readReg()

uint32_t gem5::X86ISA::Interrupts::readReg ( ApicRegIndex miscReg )

Definition at line 404 of file interrupts.cc.

References gem5::X86ISA::APIC_ARBITRATION_PRIORITY, gem5::X86ISA::APIC_CURRENT_COUNT, gem5::X86ISA::APIC_DIVIDE_CONFIGURATION, gem5::X86ISA::APIC_ERROR_STATUS, gem5::X86ISA::APIC_INTERNAL_STATE, gem5::X86ISA::APIC_PROCESSOR_PRIORITY, gem5::X86ISA::APIC_TRIGGER_MODE(), gem5::curTick(), gem5::divideFromConf(), panic, gem5::X86ISA::reg, and gem5::X86ISA::val.

Referenced by read().

◆ recvMessage()

Tick gem5::X86ISA::Interrupts::recvMessage ( PacketPtr pkt )

Definition at line 341 of file interrupts.cc.

References gem5::Packet::cmd, DPRINTF, gem5::Packet::getAddr(), gem5::Packet::getRaw(), gem5::Packet::makeAtomicResponse(), gem5::X86ISA::offset, panic, gem5::MemCmd::WriteReq, and gem5::X86ISA::x86InterruptAddress().

◆ requestInterrupt()

void gem5::X86ISA::Interrupts::requestInterrupt	(	uint8_t	vector,
		uint8_t	deliveryMode,
		bool	level
	)

protected

Definition at line 228 of file interrupts.cc.

Referenced by triggerTimerInterrupt().

◆ serialize()

void gem5::X86ISA::Interrupts::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 765 of file interrupts.cc.

References gem5::X86ISA::NUM_APIC_REGS, SERIALIZE_ARRAY, and SERIALIZE_SCALAR.

◆ setReg()

void gem5::X86ISA::Interrupts::setReg	(	ApicRegIndex	reg,
		uint32_t	val
	)

Definition at line 442 of file interrupts.cc.

References gem5::X86ISA::APIC_ARBITRATION_PRIORITY, gem5::X86ISA::APIC_CURRENT_COUNT, gem5::X86ISA::APIC_DESTINATION_FORMAT, gem5::X86ISA::APIC_DIVIDE_CONFIGURATION, gem5::X86ISA::APIC_EOI, gem5::X86ISA::APIC_ERROR_STATUS, gem5::X86ISA::APIC_ID, gem5::X86ISA::APIC_IN_SERVICE(), gem5::X86ISA::APIC_IN_SERVICE_BASE, gem5::X86ISA::APIC_INITIAL_COUNT, gem5::X86ISA::APIC_INTERNAL_STATE, gem5::X86ISA::APIC_INTERRUPT_COMMAND_HIGH, gem5::X86ISA::APIC_INTERRUPT_COMMAND_LOW, gem5::X86ISA::APIC_INTERRUPT_REQUEST(), gem5::X86ISA::APIC_LOGICAL_DESTINATION, gem5::X86ISA::APIC_LVT_ERROR, gem5::X86ISA::APIC_LVT_LINT0, gem5::X86ISA::APIC_LVT_LINT1, gem5::X86ISA::APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, gem5::X86ISA::APIC_LVT_THERMAL_SENSOR, gem5::X86ISA::APIC_LVT_TIMER, gem5::X86ISA::APIC_PROCESSOR_PRIORITY, gem5::X86ISA::APIC_SPURIOUS_INTERRUPT_VECTOR, gem5::X86ISA::APIC_TASK_PRIORITY, gem5::X86ISA::APIC_TRIGGER_MODE(), gem5::X86ISA::APIC_VERSION, gem5::bits(), gem5::X86ISA::buildIntTriggerPacket(), gem5::curTick(), gem5::divideFromConf(), hack_once, gem5::high, gem5::ArmISA::i, gem5::X86ISA::delivery_mode::LowestPriority, gem5::X86ISA::offset, panic, gem5::X86ISA::reg, gem5::X86ISA::val, and warn.

◆ setRegArrayBit()

void gem5::X86ISA::Interrupts::setRegArrayBit	(	ApicRegIndex	base,
		uint8_t	vector
	)

inlineprotected

Definition at line 157 of file interrupts.hh.

References gem5::X86ISA::base, regs, and vector.

◆ setRegNoEffect()

void gem5::X86ISA::Interrupts::setRegNoEffect	(	ApicRegIndex	reg,
		uint32_t	val
	)

inline

Definition at line 259 of file interrupts.hh.

References gem5::X86ISA::reg, regs, and gem5::X86ISA::val.

◆ setThreadContext()

void gem5::X86ISA::Interrupts::setThreadContext ( ThreadContext * _tc )

overridevirtual

Reimplemented from gem5::BaseInterrupts.

Definition at line 312 of file interrupts.cc.

References gem5::X86ISA::APIC_ID, gem5::ThreadContext::cpuId(), panic_if, gem5::BaseInterrupts::setThreadContext(), and gem5::X86ISA::x86LocalAPICAddress().

◆ triggerTimerInterrupt()

bool gem5::X86ISA::Interrupts::triggerTimerInterrupt ( )

inline

Definition at line 219 of file interrupts.hh.

References gem5::X86ISA::APIC_LVT_TIMER, regs, and requestInterrupt().

◆ unserialize()

void gem5::X86ISA::Interrupts::unserialize ( CheckpointIn & cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 790 of file interrupts.cc.

References gem5::X86ISA::NUM_APIC_REGS, UNSERIALIZE_ARRAY, and UNSERIALIZE_SCALAR.

◆ updateIntrInfo()

void gem5::X86ISA::Interrupts::updateIntrInfo ( )

overridevirtual

Implements gem5::BaseInterrupts.

Definition at line 730 of file interrupts.cc.

References gem5::X86ISA::APIC_IN_SERVICE_BASE, gem5::X86ISA::APIC_INTERRUPT_REQUEST_BASE, and DPRINTF.

◆ updateIRRV()

void gem5::X86ISA::Interrupts::updateIRRV ( )

inlineprotected

Definition at line 145 of file interrupts.hh.

References gem5::X86ISA::APIC_INTERRUPT_REQUEST_BASE, findRegArrayMSB(), and IRRV.

◆ updateISRV()

void gem5::X86ISA::Interrupts::updateISRV ( )

inlineprotected

Definition at line 151 of file interrupts.hh.

References gem5::X86ISA::APIC_IN_SERVICE_BASE, findRegArrayMSB(), and ISRV.

◆ write()

Tick gem5::X86ISA::Interrupts::write ( PacketPtr pkt )

Definition at line 211 of file interrupts.cc.

References gem5::X86ISA::decodeAddr(), DPRINTF, gem5::Packet::getAddr(), gem5::Packet::getSize(), gem5::letoh(), gem5::Packet::makeAtomicResponse(), gem5::X86ISA::mask, gem5::X86ISA::offset, panic, gem5::X86ISA::reg, gem5::guest_abi::setReg(), gem5::X86ISA::val, and gem5::Packet::writeData().

Member Data Documentation

◆ clockDomain

ClockDomain& gem5::X86ISA::Interrupts::clockDomain

protected

Definition at line 82 of file interrupts.hh.

Referenced by clockPeriod().

◆ deliveryMode

Bitfield<10, 8> gem5::X86ISA::Interrupts::deliveryMode

protected

Definition at line 89 of file interrupts.hh.

◆ extIntVector

uint8_t gem5::X86ISA::Interrupts::extIntVector = 0

protected

Definition at line 113 of file interrupts.hh.

◆ initialApicId

int gem5::X86ISA::Interrupts::initialApicId = 0

protected

Definition at line 178 of file interrupts.hh.

Referenced by getInitialApicId().

◆ initVector

uint8_t gem5::X86ISA::Interrupts::initVector = 0

protected

Definition at line 115 of file interrupts.hh.

◆ intRequestPort

IntRequestPort<Interrupts> gem5::X86ISA::Interrupts::intRequestPort

protected

Definition at line 182 of file interrupts.hh.

Referenced by getPort().

◆ intResponsePort

IntResponsePort<Interrupts> gem5::X86ISA::Interrupts::intResponsePort

protected

Definition at line 181 of file interrupts.hh.

Referenced by getPort().

◆ IRRV

uint8_t gem5::X86ISA::Interrupts::IRRV = 0

protected

Definition at line 129 of file interrupts.hh.

Referenced by updateIRRV().

◆ ISRV

uint8_t gem5::X86ISA::Interrupts::ISRV = 0

protected

Definition at line 130 of file interrupts.hh.

Referenced by updateISRV().

◆ lint0Pin

IntSinkPin<Interrupts> gem5::X86ISA::Interrupts::lint0Pin

protected

Definition at line 185 of file interrupts.hh.

Referenced by getPort().

◆ lint1Pin

IntSinkPin<Interrupts> gem5::X86ISA::Interrupts::lint1Pin

protected

Definition at line 186 of file interrupts.hh.

Referenced by getPort().

◆ masked

Bitfield<16> gem5::X86ISA::Interrupts::masked

protected

Definition at line 94 of file interrupts.hh.

◆ nmiVector

uint8_t gem5::X86ISA::Interrupts::nmiVector = 0

protected

Definition at line 111 of file interrupts.hh.

◆ pendingExtInt

bool gem5::X86ISA::Interrupts::pendingExtInt = false

protected

Definition at line 112 of file interrupts.hh.

◆ pendingInit

bool gem5::X86ISA::Interrupts::pendingInit = false

protected

Definition at line 114 of file interrupts.hh.

◆ pendingIPIs

int gem5::X86ISA::Interrupts::pendingIPIs = 0

protected

Definition at line 124 of file interrupts.hh.

◆ pendingNmi

bool gem5::X86ISA::Interrupts::pendingNmi = false

protected

Definition at line 110 of file interrupts.hh.

◆ pendingSmi

bool gem5::X86ISA::Interrupts::pendingSmi = false

protected

Definition at line 108 of file interrupts.hh.

◆ pendingStartup

bool gem5::X86ISA::Interrupts::pendingStartup = false

protected

Definition at line 116 of file interrupts.hh.

◆ pendingUnmaskableInt

bool gem5::X86ISA::Interrupts::pendingUnmaskableInt = false

protected

Definition at line 121 of file interrupts.hh.

Referenced by hasPendingUnmaskable().

◆ periodic

Bitfield<17> gem5::X86ISA::Interrupts::periodic

protected

Definition at line 95 of file interrupts.hh.

◆ pioAddr

Addr gem5::X86ISA::Interrupts::pioAddr = MaxAddr

protected

Definition at line 192 of file interrupts.hh.

Referenced by read().

◆ pioDelay

Tick gem5::X86ISA::Interrupts::pioDelay = 0

protected

Definition at line 191 of file interrupts.hh.

Referenced by read().

◆ pioPort

PioPort<Interrupts> gem5::X86ISA::Interrupts::pioPort

protected

Definition at line 189 of file interrupts.hh.

Referenced by getPort().

◆ polarity

Bitfield<13> gem5::X86ISA::Interrupts::polarity

protected

Definition at line 91 of file interrupts.hh.

◆ regs

uint32_t gem5::X86ISA::Interrupts::regs[NUM_APIC_REGS] = {}

protected

Definition at line 85 of file interrupts.hh.

Referenced by clearRegArrayBit(), findRegArrayMSB(), getRegArrayBit(), setRegArrayBit(), setRegNoEffect(), and triggerTimerInterrupt().

◆ remoteIRR

Bitfield<14> gem5::X86ISA::Interrupts::remoteIRR

protected

Definition at line 92 of file interrupts.hh.

◆ smiVector

uint8_t gem5::X86ISA::Interrupts::smiVector = 0

protected

Definition at line 109 of file interrupts.hh.

◆ startedUp

bool gem5::X86ISA::Interrupts::startedUp = false

protected

Definition at line 118 of file interrupts.hh.

◆ startupVector

uint8_t gem5::X86ISA::Interrupts::startupVector = 0

protected

Definition at line 117 of file interrupts.hh.

◆ status

Bitfield<12> gem5::X86ISA::Interrupts::status

protected

Definition at line 90 of file interrupts.hh.

◆ sys

System* gem5::X86ISA::Interrupts::sys = nullptr

protected

Definition at line 81 of file interrupts.hh.

◆ trigger

Bitfield<15> gem5::X86ISA::Interrupts::trigger

protected

Definition at line 93 of file interrupts.hh.

◆ vector

gem5::X86ISA::Interrupts::vector

protected

Definition at line 88 of file interrupts.hh.

Referenced by clearRegArrayBit(), getRegArrayBit(), and setRegArrayBit().

The documentation for this class was generated from the following files:

arch/x86/interrupts.hh
arch/x86/interrupts.cc

Public Types

Public Member Functions

Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ Params

Constructor & Destructor Documentation

◆ Interrupts()

Member Function Documentation

◆ BitUnion32()

◆ checkInterrupts()

◆ checkInterruptsRaw()

◆ clear()

◆ clearAll()

◆ clearRegArrayBit()

◆ clockPeriod()

◆ completeIPI()

◆ EndBitUnion()

◆ findRegArrayMSB()

◆ getAddrRanges()

◆ getInitialApicId()

◆ getIntAddrRange()

◆ getInterrupt()

◆ getPort()

◆ getRegArrayBit()

◆ hasPendingUnmaskable()

◆ init()

◆ lowerInterruptPin()

◆ post()

◆ processApicTimerEvent()

◆ raiseInterruptPin()

◆ read()

◆ readReg()

◆ recvMessage()

◆ requestInterrupt()

◆ serialize()

◆ setReg()

◆ setRegArrayBit()

◆ setRegNoEffect()

◆ setThreadContext()

◆ triggerTimerInterrupt()

◆ unserialize()

◆ updateIntrInfo()

◆ updateIRRV()

◆ updateISRV()

◆ write()

Member Data Documentation

◆ clockDomain

◆ deliveryMode

◆ extIntVector

◆ initialApicId

◆ initVector

◆ intRequestPort

◆ intResponsePort

◆ IRRV

◆ ISRV

◆ lint0Pin

◆ lint1Pin

◆ masked

◆ nmiVector

◆ pendingExtInt

◆ pendingInit

◆ pendingIPIs

◆ pendingNmi

◆ pendingSmi

◆ pendingStartup

◆ pendingUnmaskableInt

◆ periodic

◆ pioAddr

◆ pioDelay

◆ pioPort

◆ polarity

◆ regs

◆ remoteIRR

◆ smiVector

◆ startedUp

◆ startupVector

◆ status