50 #include "debug/Activity.hh"
51 #include "debug/O3PipeView.hh"
52 #include "debug/Rename.hh"
53 #include "params/BaseO3CPU.hh"
63 iewToRenameDelay(params.iewToRenameDelay),
64 decodeToRenameDelay(params.decodeToRenameDelay),
65 commitToRenameDelay(params.commitToRenameDelay),
66 renameWidth(params.renameWidth),
67 numThreads(params.numThreads),
71 fatal(
"renameWidth (%d) is larger than compiled limit (%d),\n"
72 "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
77 for (uint32_t tid = 0; tid <
MaxThreads; tid++) {
85 stalls[tid] = {
false,
false};
98 : statistics::
Group(parent,
"rename"),
99 ADD_STAT(squashCycles, statistics::units::Cycle::get(),
100 "Number of cycles rename is squashing"),
101 ADD_STAT(idleCycles, statistics::units::Cycle::get(),
102 "Number of cycles rename is idle"),
103 ADD_STAT(blockCycles, statistics::units::Cycle::get(),
104 "Number of cycles rename is blocking"),
105 ADD_STAT(serializeStallCycles, statistics::units::Cycle::get(),
106 "count of cycles rename stalled for serializing inst"),
107 ADD_STAT(runCycles, statistics::units::Cycle::get(),
108 "Number of cycles rename is running"),
109 ADD_STAT(unblockCycles, statistics::units::Cycle::get(),
110 "Number of cycles rename is unblocking"),
112 "Number of instructions processed by rename"),
114 "Number of squashed instructions processed by rename"),
116 "Number of times rename has blocked due to ROB full"),
118 "Number of times rename has blocked due to IQ full"),
120 "Number of times rename has blocked due to LQ full" ),
122 "Number of times rename has blocked due to SQ full"),
123 ADD_STAT(fullRegistersEvents, statistics::units::
Count::get(),
124 "Number of times there has been no free registers"),
126 "Number of destination operands rename has renamed"),
128 "Number of register rename lookups that rename has made"),
130 "Number of integer rename lookups"),
132 "Number of floating rename lookups"),
134 "Number of vector rename lookups"),
136 "Number of vector predicate rename lookups"),
138 "Number of HB maps that are committed"),
140 "Number of HB maps that are undone due to squashing"),
142 "count of serializing insts renamed"),
144 "count of temporary serializing insts renamed"),
146 "count of insts added to the skid buffer")
311 !
insts[tid].empty() ||
329 assert(
insts[tid].empty());
338 DPRINTF(
Rename,
"[tid:%i] [squash sn:%llu] Squashing instructions.\n",
353 "Rename will resume serializing after squash\n",
395 bool status_change =
false;
405 while (threads != end) {
412 rename(status_change, tid);
420 DPRINTF(Activity,
"Activity this cycle.\n");
426 while (threads != end) {
430 if (
fromCommit->commitInfo[tid].doneSeqNum != 0 &&
473 toDecode->renameUnblock[tid] =
false;
479 toDecode->renameUnblock[tid] =
false;
487 "Not blocked, so attempting to run stage.\n",
516 if (insts_available == 0) {
517 DPRINTF(
Rename,
"[tid:%i] Nothing to do, breaking out early.\n",
532 int min_free_entries = free_rob_entries;
536 if (free_iq_entries < min_free_entries) {
537 min_free_entries = free_iq_entries;
542 if (min_free_entries <= 0) {
544 "[tid:%i] Blocking due to no free ROB/IQ/ entries.\n"
545 "ROB has %i free entries.\n"
546 "IQ has %i free entries.\n",
547 tid, free_rob_entries, free_iq_entries);
556 }
else if (min_free_entries < insts_available) {
559 "Will have to block this cycle. "
560 "%i insts available, "
561 "but only %i insts can be renamed due to ROB/IQ/LSQ limits.\n",
562 tid, insts_available, min_free_entries);
564 insts_available = min_free_entries;
576 "%i available instructions to send iew.\n",
577 tid, insts_available);
581 "%i insts pipelining from Rename | "
582 "%i insts dispatched to IQ last cycle.\n",
590 }
else if (!insts_to_rename.empty()) {
591 insts_to_rename.front()->setSerializeBefore();
595 int renamed_insts = 0;
598 DPRINTF(
Rename,
"[tid:%i] Sending instructions to IEW.\n", tid);
600 assert(!insts_to_rename.empty());
609 if (inst->isLoad()) {
611 DPRINTF(
Rename,
"[tid:%i] Cannot rename due to no free LQ\n",
619 if (inst->isStore() || inst->isAtomic()) {
621 DPRINTF(
Rename,
"[tid:%i] Cannot rename due to no free SQ\n",
629 insts_to_rename.pop_front();
634 "Removing [sn:%llu] PC:%s from rename skidBuffer\n",
635 tid, inst->seqNum, inst->pcState());
638 if (inst->isSquashed()) {
641 "instruction %i with PC %s is squashed, skipping.\n",
642 tid, inst->seqNum, inst->pcState());
654 "Processing instruction [sn:%llu] with PC %s.\n",
655 tid, inst->seqNum, inst->pcState());
662 " lack of free physical registers to rename to.\n");
664 insts_to_rename.push_front(inst);
680 if (inst->isSerializeBefore() && !inst->isSerializeHandled()) {
681 DPRINTF(
Rename,
"Serialize before instruction encountered.\n");
683 if (!inst->isTempSerializeBefore()) {
685 inst->setSerializeHandled();
699 }
else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
700 !inst->isSerializeHandled()) {
701 DPRINTF(
Rename,
"Serialize after instruction encountered.\n");
705 inst->setSerializeHandled();
714 if (inst->isAtomic() || inst->isStore()) {
716 }
else if (inst->isLoad()) {
746 if (insts_available) {
752 toDecode->renameUnblock[tid] =
false;
761 while (!
insts[tid].empty()) {
762 inst =
insts[tid].front();
764 insts[tid].pop_front();
766 assert(tid == inst->threadNumber);
768 DPRINTF(
Rename,
"[tid:%i] Inserting [sn:%llu] PC: %s into Rename "
769 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
777 InstQueue::iterator it;
778 warn(
"Skidbuffer contents:\n");
780 warn(
"[tid:%i] %s [sn:%llu].\n", tid,
781 (*it)->staticInst->disassemble(
782 inst->pcState().instAddr()),
785 panic(
"Skidbuffer Exceeded Max Size");
793 for (
int i = 0;
i < insts_from_decode; ++
i) {
795 insts[inst->threadNumber].push_back(inst);
797 if (debug::O3PipeView) {
798 inst->renameTick =
curTick() - inst->fetchTick;
810 while (threads != end) {
823 bool any_unblocking =
false;
828 while (threads != end) {
832 any_unblocking =
true;
838 if (any_unblocking) {
842 DPRINTF(Activity,
"Activating stage.\n");
851 DPRINTF(Activity,
"Deactivating stage.\n");
875 toDecode->renameUnblock[tid] =
false;
901 toDecode->renameUnblock[tid] =
true;
921 hb_it->instSeqNum > squashed_seq_num) {
924 DPRINTF(
Rename,
"[tid:%i] Removing history entry with sequence "
925 "number %i (archReg: %d, newPhysReg: %d, prevPhysReg: %d).\n",
926 tid, hb_it->instSeqNum, hb_it->archReg.index(),
927 hb_it->newPhysReg->index(), hb_it->prevPhysReg->index());
935 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
959 DPRINTF(
Rename,
"[tid:%i] Removing a committed instruction from the "
960 "history buffer %u (size=%i), until [sn:%llu].\n",
970 }
else if (hb_it->instSeqNum > inst_seq_num) {
972 "Old sequence number encountered. "
973 "Ensure that a syscall happened recently.\n",
984 hb_it->instSeqNum <= inst_seq_num) {
986 DPRINTF(
Rename,
"[tid:%i] Freeing up older rename of reg %i (%s), "
988 tid, hb_it->prevPhysReg->index(),
989 hb_it->prevPhysReg->className(),
995 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
1010 unsigned num_src_regs = inst->numSrcRegs();
1015 for (
int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1016 const RegId& src_reg = inst->srcRegIdx(src_idx);
1020 renamed_reg = map->
lookup(flat_reg);
1047 "Looking up %s arch reg %i, got phys reg %i (%s)\n",
1052 inst->renameSrcReg(src_idx, renamed_reg);
1058 "Register %d (flat: %d) (%s) is ready.\n",
1062 inst->markSrcRegReady(src_idx);
1066 "Register %d (flat: %d) (%s) is not ready.\n",
1080 unsigned num_dest_regs = inst->numDestRegs();
1084 for (
int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1085 const RegId& dest_reg = inst->destRegIdx(dest_idx);
1091 rename_result = map->
rename(flat_dest_regid);
1093 inst->flattenedDestIdx(dest_idx, flat_dest_regid);
1099 "Renaming arch reg %i (%s) to physical reg %i (%i).\n",
1101 rename_result.first->index(),
1102 rename_result.first->flatIndex());
1106 rename_result.first,
1107 rename_result.second);
1112 "Adding instruction to history buffer (size=%i).\n",
1121 inst->renameDestReg(dest_idx,
1122 rename_result.first,
1123 rename_result.second);
1157 "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, "
1158 "loads dispatchedToLQ: %d\n",
1160 fromIEW->iewInfo[tid].dispatchedToLQ);
1170 "storesInProgress: %d, stores dispatchedToSQ: %d\n",
1172 fromIEW->iewInfo[tid].dispatchedToSQ);
1179 unsigned inst_count = 0;
1196 if (
fromIEW->iewUnblock[tid]) {
1205 bool ret_val =
false;
1208 DPRINTF(
Rename,
"[tid:%i] Stall from IEW stage detected.\n", tid);
1211 DPRINTF(
Rename,
"[tid:%i] Stall: ROB has 0 free entries.\n", tid);
1214 DPRINTF(
Rename,
"[tid:%i] Stall: IQ has 0 free entries.\n", tid);
1217 DPRINTF(
Rename,
"[tid:%i] Stall: LSQ has 0 free entries.\n", tid);
1219 }
else if (
renameMap[tid]->numFreeEntries() <= 0) {
1220 DPRINTF(
Rename,
"[tid:%i] Stall: RenameMap has 0 free entries.\n", tid);
1224 DPRINTF(
Rename,
"[tid:%i] Stall: Serialize stall and ROB is not "
1236 if (
fromIEW->iewInfo[tid].usedIQ)
1239 if (
fromIEW->iewInfo[tid].usedLSQ) {
1251 "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i %i)\n",
1265 DPRINTF(
Rename,
"[tid:%i] %i instructions not yet in ROB\n",
1286 DPRINTF(
Rename,
"[tid:%i] Squashing instructions due to squash from "
1299 DPRINTF(
Rename,
"[tid:%i] Done blocking, switching to unblocking.\n",
1314 "[tid:%i] Done squashing, switching to serialize.\n", tid);
1320 "[tid:%i] Done squashing, switching to unblocking.\n",
1325 DPRINTF(
Rename,
"[tid:%i] Done squashing, switching to running.\n",
1334 DPRINTF(
Rename,
"[tid:%i] Done with serialize stall, switching to "
1335 "unblocking.\n", tid);
1343 DPRINTF(
Rename,
"[tid:%i] Processing instruction [%lli] with "
1344 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1347 serial_inst->clearSerializeBefore();
1352 insts[tid].push_front(serial_inst);
1355 DPRINTF(
Rename,
"[tid:%i] Instruction must be processed by rename."
1356 " Adding to front of list.\n", tid);
1371 if (inst_list.empty()) {
1378 inst_list.front()->setSerializeBefore();
1398 panic(
"Rename full stall stat should be incremented for a reason!");
1413 cprintf(
"Seq num: %i\nArch reg[%s]: %i New phys reg:"
1414 " %i[%s] Old phys reg: %i[%s]\n",
1415 (*buf_it).instSeqNum,
1416 (*buf_it).archReg.className(),
1417 (*buf_it).archReg.index(),
1418 (*buf_it).newPhysReg->index(),
1419 (*buf_it).newPhysReg->className(),
1420 (*buf_it).prevPhysReg->index(),
1421 (*buf_it).prevPhysReg->className());
virtual std::string name() const
constexpr RegIndex index() const
Visible RegId methods.
constexpr const char * className() const
Return a const char* with the register class name.
const RegIndex & flatIndex() const
Flat index accessor.
ProbePointArg generates a point for the class of Arg.
Register ID: describe an architectural register with its class and index.
constexpr RegClassType classValue() const
void setNumPinnedWrites(int num_writes)
constexpr RegIndex index() const
Index accessors.
int getNumPinnedWrites() const
RegId flatten(const BaseISA &isa) const
constexpr const char * className() const
Return a const char* with the register class name.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual BaseISA * getIsaPtr() const =0
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
void activityThisCycle()
Records that there was time buffer activity this cycle.
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
size_t numROBFreeEntries(ThreadID tid)
Returns the number of free ROB entries for a specific thread.
InstructionQueue instQueue
Instruction queue.
LSQ ldstQueue
Load / store queue.
unsigned numFreeEntries()
Returns total number of free entries.
unsigned numFreeLoadEntries()
Returns the number of free load entries.
unsigned numFreeStoreEntries()
Returns the number of free store entries.
Rename handles both single threaded and SMT rename.
DynInstPtr serializeInst[MaxThreads]
The serialize instruction that rename has stalled on.
void incrFullStat(const FullSource &source)
Function used to increment the stat that corresponds to the source of the stall.
ThreadID numThreads
The number of threads active in rename.
TimeBuffer< RenameStruct >::wire toIEW
Wire to write any information heading to IEW.
void sortInsts()
Separates instructions from decode into individual lists of instructions sorted by thread.
ThreadStatus renameStatus[MaxThreads]
Per-thread status.
Rename(CPU *_cpu, const BaseO3CPUParams ¶ms)
Rename constructor.
TimeBuffer< TimeStruct >::wire toDecode
Wire to write infromation heading to previous stages.
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue.
unsigned commitToRenameDelay
Delay between commit and rename, in ticks.
int storesInProgress[MaxThreads]
Count of Store instructions in progress that have been sent off to the IQ and ROB,...
int instsInProgress[MaxThreads]
Count of instructions in progress that have been sent off to the IQ and ROB, but are not yet included...
int calcFreeIQEntries(ThreadID tid)
Calculates the number of free IQ entries for a specific thread.
void startupStage()
Initializes variables for the stage.
ProbePointArg< DynInstPtr > * ppRename
To probe when register renaming for an instruction is complete.
bool blockThisCycle
Whether or not rename needs to block this cycle.
void renameSrcRegs(const DynInstPtr &inst, ThreadID tid)
Renames the source registers of an instruction.
void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid)
Executes actual squash, removing squashed instructions.
void renameDestRegs(const DynInstPtr &inst, ThreadID tid)
Renames the destination registers of an instruction.
unsigned skidBufferMax
The maximum skid buffer size.
std::list< ThreadID > * activeThreads
Pointer to the list of active threads.
UnifiedFreeList * freeList
Free list interface.
void tick()
Ticks rename, which processes all input signals and attempts to rename as many instructions as possib...
void readFreeEntries(ThreadID tid)
Gets the number of free entries for a specific thread.
int calcFreeROBEntries(ThreadID tid)
Calculates the number of free ROB entries for a specific thread.
int iewToRenameDelay
Delay between iew and rename, in ticks.
RenameStatus _status
Rename status.
void renameInsts(ThreadID tid)
Renames instructions for the given thread.
void setFreeList(UnifiedFreeList *fl_ptr)
Sets pointer to the free list.
bool emptyROB[MaxThreads]
Records if the ROB is empty.
void rename(bool &status_change, ThreadID tid)
Determines what to do based on rename's current status.
TimeBuffer< TimeStruct >::wire fromIEW
Wire to get IEW's output from backwards time buffer.
std::string name() const
Returns the name of rename.
std::list< RenameHistory > historyBuffer[MaxThreads]
A per-thread list of all destination register renames, used to either undo rename mappings or free ol...
TimeBuffer< DecodeStruct >::wire fromDecode
Wire to get decode's output from decode queue.
void serializeAfter(InstQueue &inst_list, ThreadID tid)
Either serializes on the next instruction available in the InstQueue, or records that it must seriali...
gem5::o3::Rename::RenameStats stats
TimeBuffer< DecodeStruct > * decodeQueue
Decode instruction queue interface.
unsigned renameWidth
Rename width, in instructions.
bool resumeUnblocking
Whether or not rename needs to resume clearing out the skidbuffer after squashing.
InstQueue skidBuffer[MaxThreads]
Skid buffer between rename and decode.
Scoreboard * scoreboard
Pointer to the scoreboard.
void drainSanityCheck() const
Perform sanity checks after a drain.
bool skidsEmpty()
Returns if all of the skid buffers are empty.
IEW * iew_ptr
Pointer to IEW stage.
int calcFreeSQEntries(ThreadID tid)
Calculates the number of free SQ entries for a specific thread.
void dumpHistory()
Debugging function used to dump history buffer of renamings.
FullSource
Enum to record the source of a structure full stall.
UnifiedRenameMap * renameMap[MaxThreads]
Rename map interface.
bool block(ThreadID tid)
Switches rename to blocking, and signals back that rename has become blocked.
int loadsInProgress[MaxThreads]
Count of Load instructions in progress that have been sent off to the IQ and ROB, but are not yet inc...
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's output from backwards time buffer.
bool unblock(ThreadID tid)
Switches rename to unblocking if the skid buffer is empty, and signals back that rename has unblocked...
TimeBuffer< TimeStruct > * timeBuffer
Pointer to main time buffer used for backwards communication.
unsigned toIEWIndex
The index of the instruction in the time buffer to IEW that rename is currently using.
void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
Removes a committed instruction's rename history.
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the main backwards communication time buffer pointer.
void takeOverFrom()
Takes over from another CPU's thread.
void setRenameMap(UnifiedRenameMap rm_ptr[MaxThreads])
Sets pointer to rename maps (per-thread structures).
Stalls stalls[MaxThreads]
Tracks which stages are telling decode to stall.
void regProbePoints()
Registers probes.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
void resetStage()
Reset this pipeline stage.
bool checkStall(ThreadID tid)
Checks if any stages are telling rename to block.
InstQueue insts[MaxThreads]
Queue of all instructions coming from decode this cycle.
void skidInsert(ThreadID tid)
Inserts unused instructions from a given thread into the skid buffer, to be renamed once rename unblo...
void readStallSignals(ThreadID tid)
Reads signals telling rename to block/unblock.
void updateStatus()
Updates overall rename status based on all of the threads' statuses.
bool checkSignalsAndUpdate(ThreadID tid)
Checks the signals and updates the status.
void squash(const InstSeqNum &squash_seq_num, ThreadID tid)
Squashes all instructions in a thread.
bool isDrained() const
Has the stage drained?
void setScoreboard(Scoreboard *_scoreboard)
Sets pointer to the scoreboard.
FreeEntries freeEntries[MaxThreads]
Per-thread tracking of the number of free entries of back-end structures.
int calcFreeLQEntries(ThreadID tid)
Calculates the number of free LQ entries for a specific thread.
Commit * commit_ptr
Pointer to commit stage.
bool serializeOnNextInst[MaxThreads]
Records if rename needs to serialize on the next instruction for any thread.
ProbePointArg< SeqNumRegPair > * ppSquashInRename
To probe when an instruction is squashed and the register mapping for it needs to be undone.
int decodeToRenameDelay
Delay between decode and rename, in ticks.
void clearStates(ThreadID tid)
Clear all thread-specific states.
bool wroteToTimeBuffer
Variable that tracks if decode has written to the time buffer this cycle.
void setDecodeQueue(TimeBuffer< DecodeStruct > *dq_ptr)
Sets pointer to time buffer coming from decode.
bool resumeSerialize
Whether or not rename needs to resume a serialize instruction after squashing.
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets pointer to time buffer used to communicate to the next stage.
unsigned validInsts()
Returns the number of valid instructions coming from decode.
Implements a simple scoreboard to track which registers are ready.
bool getReg(PhysRegIdPtr phys_reg) const
Checks if the register is ready.
void unsetReg(PhysRegIdPtr phys_reg)
Sets the register as not ready.
FreeList class that simply holds the list of free integer and floating point registers.
void addReg(PhysRegIdPtr freed_reg)
Adds a register back to the free list.
Unified register rename map for all classes of registers.
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
PhysRegIdPtr lookup(const RegId &arch_reg) const
Look up the physical register mapped to an architectural register.
RenameInfo rename(const RegId &arch_reg)
Tell rename map to get a new free physical register to remap the specified architectural register.
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
#define panic(...)
This implements a cprintf based panic() function.
#define fatal(...)
This implements a cprintf based fatal() function.
ProbeManager * getProbeManager()
Get the probe manager for this object.
static constexpr int MaxThreads
static constexpr int MaxWidth
const FlagsType total
Print the total.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
int16_t ThreadID
Thread index/ID type.
void cprintf(const char *format, const Args &...args)
Tick curTick()
The universal simulation clock.
@ FloatRegClass
Floating-point register.
@ CCRegClass
Condition-code register.
@ VecRegClass
Vector Register.
@ IntRegClass
Integer register.
@ MiscRegClass
Control (misc) register.
@ VecElemClass
Vector Register Native Elem lane.
Holds the information for each destination register rename.
statistics::Scalar blockCycles
Stat for total number of cycles spent blocking.
statistics::Scalar ROBFullEvents
Stat for total number of times that the ROB starts a stall in rename.
statistics::Scalar renamedOperands
Stat for total number of renamed destination registers.
statistics::Scalar fpLookups
statistics::Scalar fullRegistersEvents
Stat for total number of times that rename runs out of free registers to use to rename.
statistics::Scalar squashedInsts
Stat for total number of squashed instructions that rename discards.
statistics::Scalar IQFullEvents
Stat for total number of times that the IQ starts a stall in rename.
statistics::Scalar vecPredLookups
statistics::Scalar squashCycles
Stat for total number of cycles spent squashing.
statistics::Scalar renamedInsts
Stat for total number of renamed instructions.
statistics::Scalar LQFullEvents
Stat for total number of times that the LQ starts a stall in rename.
statistics::Scalar lookups
Stat for total number of source register rename lookups.
statistics::Scalar vecLookups
statistics::Scalar tempSerializing
Number of instructions marked as temporarily serializing.
statistics::Scalar serializing
Number of serialize instructions handled.
statistics::Scalar undoneMaps
Stat for total number of mappings that were undone due to a squash.
statistics::Scalar runCycles
Stat for total number of cycles spent running normally.
statistics::Scalar committedMaps
Stat for total number of committed renaming mappings.
statistics::Scalar intLookups
statistics::Scalar unblockCycles
Stat for total number of cycles spent unblocking.
statistics::Scalar idleCycles
Stat for total number of cycles spent idle.
RenameStats(statistics::Group *parent)
statistics::Scalar SQFullEvents
Stat for total number of times that the SQ starts a stall in rename.
statistics::Scalar skidInsts
Number of instructions inserted into skid buffers.
statistics::Scalar serializeStallCycles
Stat for total number of cycles spent stalling for a serializing inst.