gem5  v21.1.0.2
cpu.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011,2013,2017-2018, 2020 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2006 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #include "cpu/checker/cpu.hh"
42 
43 #include <list>
44 #include <string>
45 
46 #include "arch/generic/tlb.hh"
47 #include "cpu/base.hh"
48 #include "cpu/simple_thread.hh"
49 #include "cpu/static_inst.hh"
50 #include "cpu/thread_context.hh"
51 #include "cpu/utils.hh"
52 #include "params/CheckerCPU.hh"
53 #include "sim/full_system.hh"
54 
55 namespace gem5
56 {
57 
58 void
60 {
63 }
64 
66  : BaseCPU(p, true),
67  zeroReg(params().isa[0]->regClasses().at(IntRegClass).zeroReg()),
68  systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
69  tc(NULL), thread(NULL),
70  unverifiedReq(nullptr),
71  unverifiedMemData(nullptr)
72 {
73  curStaticInst = NULL;
74  curMacroStaticInst = NULL;
75 
76  numInst = 0;
77  startNumInst = 0;
78  numLoad = 0;
79  startNumLoad = 0;
80  youngestSN = 0;
81 
82  changedPC = willChangePC = false;
83 
84  exitOnError = p.exitOnError;
85  warnOnlyOnLoadError = p.warnOnlyOnLoadError;
86  mmu = p.mmu;
87  workload = p.workload;
88 
89  updateOnError = true;
90 }
91 
93 {
94 }
95 
96 void
98 {
99  const Params &p = params();
100 
101  systemPtr = system;
102 
103  if (FullSystem) {
104  thread = new SimpleThread(this, 0, systemPtr, mmu, p.isa[0]);
105  } else {
106  thread = new SimpleThread(this, 0, systemPtr,
107  workload.size() ? workload[0] : NULL,
108  mmu, p.isa[0]);
109  }
110 
111  tc = thread->getTC();
112  threadContexts.push_back(tc);
113  // Thread should never be null after this
114  assert(thread != NULL);
115 }
116 
117 void
119 {
120  icachePort = icache_port;
121 }
122 
123 void
125 {
126  dcachePort = dcache_port;
127 }
128 
129 void
130 CheckerCPU::serialize(std::ostream &os) const
131 {
132 }
133 
134 void
136 {
137 }
138 
141  Request::Flags flags,
142  const std::vector<bool>& byte_enable,
143  int& frag_size, int& size_left) const
144 {
145  frag_size = std::min(
146  cacheLineSize() - addrBlockOffset(frag_addr, cacheLineSize()),
147  (Addr) size_left);
148  size_left -= frag_size;
149 
150  RequestPtr mem_req;
151 
152  // Set up byte-enable mask for the current fragment
153  auto it_start = byte_enable.cbegin() + (size - (frag_size +
154  size_left));
155  auto it_end = byte_enable.cbegin() + (size - size_left);
156  if (isAnyActiveElement(it_start, it_end)) {
157  mem_req = std::make_shared<Request>(frag_addr, frag_size,
158  flags, requestorId, thread->pcState().instAddr(),
159  tc->contextId());
160  mem_req->setByteEnable(std::vector<bool>(it_start, it_end));
161  }
162 
163  return mem_req;
164 }
165 
166 Fault
167 CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
168  Request::Flags flags,
169  const std::vector<bool>& byte_enable)
170 {
171  assert(byte_enable.size() == size);
172 
173  Fault fault = NoFault;
174  bool checked_flags = false;
175  bool flags_match = true;
176  Addr pAddr = 0x0;
177 
178  Addr frag_addr = addr;
179  int frag_size = 0;
180  int size_left = size;
181  bool predicate;
182 
183  // Need to account for multiple accesses like the Atomic and TimingSimple
184  while (1) {
185  RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
186  byte_enable, frag_size,
187  size_left);
188 
189  predicate = (mem_req != nullptr);
190 
191  // translate to physical address
192  if (predicate) {
193  fault = mmu->translateFunctional(mem_req, tc, BaseMMU::Read);
194  }
195 
196  if (predicate && !checked_flags && fault == NoFault && unverifiedReq) {
197  flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
198  mem_req->getPaddr(), mem_req->getFlags());
199  pAddr = mem_req->getPaddr();
200  checked_flags = true;
201  }
202 
203  // Now do the access
204  if (predicate && fault == NoFault &&
205  !mem_req->getFlags().isSet(Request::NO_ACCESS)) {
206  PacketPtr pkt = Packet::createRead(mem_req);
207 
208  pkt->dataStatic(data);
209 
210  if (!(mem_req->isUncacheable() || mem_req->isLocalAccess())) {
211  // Access memory to see if we have the same data
213  } else {
214  // Assume the data is correct if it's an uncached access
215  memcpy(data, unverifiedMemData, frag_size);
216  }
217 
218  delete pkt;
219  }
220 
221  if (fault != NoFault) {
222  if (mem_req->isPrefetch()) {
223  fault = NoFault;
224  }
225  break;
226  }
227 
228  //If we don't need to access a second cache line, stop now.
229  if (size_left == 0)
230  {
231  break;
232  }
233 
234  // Setup for accessing next cache line
235  frag_addr += frag_size;
236  data += frag_size;
237  unverifiedMemData += frag_size;
238  }
239 
240  if (!flags_match) {
241  warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
242  curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
243  unverifiedReq->getFlags(), frag_addr, pAddr, flags);
244  handleError();
245  }
246 
247  return fault;
248 }
249 
250 Fault
251 CheckerCPU::writeMem(uint8_t *data, unsigned size,
252  Addr addr, Request::Flags flags, uint64_t *res,
253  const std::vector<bool>& byte_enable)
254 {
255  assert(byte_enable.size() == size);
256 
257  Fault fault = NoFault;
258  bool checked_flags = false;
259  bool flags_match = true;
260  Addr pAddr = 0x0;
261  static uint8_t zero_data[64] = {};
262 
263  Addr frag_addr = addr;
264  int frag_size = 0;
265  int size_left = size;
266  bool predicate;
267 
268  // Need to account for a multiple access like Atomic and Timing CPUs
269  while (1) {
270  RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
271  byte_enable, frag_size,
272  size_left);
273 
274  predicate = (mem_req != nullptr);
275 
276  if (predicate) {
277  fault = mmu->translateFunctional(mem_req, tc, BaseMMU::Write);
278  }
279 
280  if (predicate && !checked_flags && fault == NoFault && unverifiedReq) {
281  flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
282  mem_req->getPaddr(), mem_req->getFlags());
283  pAddr = mem_req->getPaddr();
284  checked_flags = true;
285  }
286 
287  /*
288  * We don't actually check memory for the store because there
289  * is no guarantee it has left the lsq yet, and therefore we
290  * can't verify the memory on stores without lsq snooping
291  * enabled. This is left as future work for the Checker: LSQ snooping
292  * and memory validation after stores have committed.
293  */
294  bool was_prefetch = mem_req->isPrefetch();
295 
296  //If we don't need to access a second cache line, stop now.
297  if (fault != NoFault || size_left == 0)
298  {
299  if (fault != NoFault && was_prefetch) {
300  fault = NoFault;
301  }
302  break;
303  }
304 
305  frag_addr += frag_size;
306  }
307 
308  if (!flags_match) {
309  warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
310  curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
311  unverifiedReq->getFlags(), frag_addr, pAddr, flags);
312  handleError();
313  }
314 
315  // Assume the result was the same as the one passed in. This checker
316  // doesn't check if the SC should succeed or fail, it just checks the
317  // value.
318  if (unverifiedReq && res && unverifiedReq->extraDataValid())
319  *res = unverifiedReq->getExtraData();
320 
321  // Entire purpose here is to make sure we are getting the
322  // same data to send to the mem system as the CPU did.
323  // Cannot check this is actually what went to memory because
324  // there stores can be in ld/st queue or coherent operations
325  // overwriting values.
326  bool extraData = false;
327  if (unverifiedReq) {
328  extraData = unverifiedReq->extraDataValid() ?
329  unverifiedReq->getExtraData() : true;
330  }
331 
332  // If the request is to ZERO a cache block, there is no data to check
333  // against, but it's all zero. We need something to compare to, so use a
334  // const set of zeros.
335  if (flags & Request::STORE_NO_DATA) {
336  assert(!data);
337  assert(sizeof(zero_data) <= size);
338  data = zero_data;
339  }
340 
342  memcmp(data, unverifiedMemData, size) && extraData) {
343  warn("%lli: Store value does not match value sent to memory! "
344  "data: %#x inst_data: %#x", curTick(), data,
346  handleError();
347  }
348 
349  return fault;
350 }
351 
355 bool
356 CheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr,
357  Addr pAddr, int flags)
358 {
359  Addr unverifiedVAddr = unverified_req->getVaddr();
360  Addr unverifiedPAddr = unverified_req->getPaddr();
361  int unverifiedFlags = unverified_req->getFlags();
362 
363  if (unverifiedVAddr != vAddr ||
364  unverifiedPAddr != pAddr ||
365  unverifiedFlags != flags) {
366  return false;
367  }
368 
369  return true;
370 }
371 
372 void
374 {
375  warn("%lli: Checker PC:%s",
376  curTick(), thread->pcState());
377  panic("Checker found an error!");
378 }
379 
380 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::CheckerCPU::CheckerCPU
CheckerCPU(const Params &p)
Definition: cpu.cc:65
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:53
utils.hh
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::CheckerCPU::numInst
Counter numInst
Definition: cpu.hh:144
warn
#define warn(...)
Definition: logging.hh:245
gem5::CheckerCPU::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: cpu.cc:130
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::CheckerCPU::~CheckerCPU
virtual ~CheckerCPU()
Definition: cpu.cc:92
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:53
gem5::BaseCPU::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: base.hh:381
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::CheckerCPU::unverifiedReq
RequestPtr unverifiedReq
Definition: cpu.hh:545
gem5::CheckerCPU::genMemFragmentRequest
RequestPtr genMemFragmentRequest(Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
Helper function used to generate the request for a single fragment of a memory access.
Definition: cpu.cc:140
tlb.hh
gem5::CheckerCPU::workload
std::vector< Process * > workload
Definition: cpu.hh:125
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::BaseCPU::system
System * system
Definition: base.hh:376
gem5::CheckerCPU::thread
SimpleThread * thread
Definition: cpu.hh:152
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::addrBlockOffset
Addr addrBlockOffset(Addr addr, Addr block_size)
Calculates the offset of a given address wrt aligned fixed-size blocks.
Definition: utils.hh:53
std::vector< bool >
gem5::CheckerCPU::willChangePC
bool willChangePC
Definition: cpu.hh:549
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
gem5::CheckerCPU::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
Definition: cpu.cc:251
gem5::CheckerCPU::youngestSN
InstSeqNum youngestSN
Definition: cpu.hh:555
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::BaseMMU::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: mmu.cc:79
gem5::ArmISA::at
Bitfield< 35, 32 > at
Definition: misc_types.hh:154
gem5::CheckerCPU::dumpAndExit
void dumpAndExit()
Definition: cpu.cc:373
gem5::Packet::dataStatic
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
Definition: packet.hh:1134
gem5::CheckerCPU::tc
ThreadContext * tc
Definition: cpu.hh:132
gem5::Flags< FlagsType >
gem5::RequestPort::sendFunctional
void sendFunctional(PacketPtr pkt) const
Send a functional request packet, where the data is instantly updated everywhere in the memory system...
Definition: port.hh:485
gem5::System
Definition: system.hh:77
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::CheckerCPU::dcachePort
RequestPort * dcachePort
Definition: cpu.hh:130
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
cpu.hh
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::isAnyActiveElement
bool isAnyActiveElement(const std::vector< bool >::const_iterator &it_start, const std::vector< bool >::const_iterator &it_end)
Test if there is any active element in an enablement range.
Definition: utils.hh:89
gem5::BaseISA::setThreadContext
virtual void setThreadContext(ThreadContext *_tc)
Definition: isa.hh:68
gem5::BaseCPU
Definition: base.hh:107
gem5::CheckerCPU::icachePort
RequestPort * icachePort
Definition: cpu.hh:129
gem5::System::getRequestorId
RequestorID getRequestorId(const SimObject *requestor, std::string subrequestor={})
Request an id used to create a request object in the system.
Definition: system.cc:586
gem5::CheckerCPU::systemPtr
System * systemPtr
Definition: cpu.hh:127
static_inst.hh
gem5::SimpleThread::pcState
TheISA::PCState pcState() const override
Definition: simple_thread.hh:430
gem5::CheckerCPU::numLoad
Counter numLoad
Definition: cpu.hh:167
gem5::CheckerCPU::startNumInst
Counter startNumInst
Definition: cpu.hh:145
gem5::CheckerCPU::requestorId
RequestorID requestorId
id attached to all issued requests
Definition: cpu.hh:88
gem5::CheckerCPU::changedPC
bool changedPC
Definition: cpu.hh:548
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::CheckerCPU::mmu
BaseMMU * mmu
Definition: cpu.hh:134
gem5::CheckerCPU::readMem
Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Definition: cpu.cc:167
gem5::CheckerCPU::exitOnError
bool exitOnError
Definition: cpu.hh:551
full_system.hh
gem5::CheckerCPU::checkFlags
bool checkFlags(const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags)
Checks if the flags set by the Checker and Checkee match.
Definition: cpu.cc:356
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::SimpleThread::getTC
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext.
Definition: simple_thread.hh:169
gem5::Request::STORE_NO_DATA
static const FlagsType STORE_NO_DATA
Definition: request.hh:244
gem5::CheckerCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: cpu.cc:59
gem5::CheckerCPU::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: cpu.cc:135
gem5::CheckerCPU::handleError
void handleError()
Definition: cpu.hh:530
simple_thread.hh
gem5::BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:262
gem5::CheckerCPU::curStaticInst
StaticInstPtr curStaticInst
Definition: cpu.hh:140
gem5::CheckerCPU::setDcachePort
void setDcachePort(RequestPort *dcache_port)
Definition: cpu.cc:124
base.hh
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::CheckerCPU::warnOnlyOnLoadError
bool warnOnlyOnLoadError
Definition: cpu.hh:553
gem5::Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:146
gem5::CheckerCPU::startNumLoad
Counter startNumLoad
Definition: cpu.hh:168
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::CheckerCPU::setIcachePort
void setIcachePort(RequestPort *icache_port)
Definition: cpu.cc:118
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Packet::createRead
static PacketPtr createRead(const RequestPtr &req)
Constructor-like methods that return Packets based on Request objects.
Definition: packet.hh:1007
gem5::CheckerCPU::curMacroStaticInst
StaticInstPtr curMacroStaticInst
Definition: cpu.hh:141
gem5::CheckerCPU::updateOnError
bool updateOnError
Definition: cpu.hh:552
thread_context.hh
gem5::CheckerCPU::unverifiedMemData
uint8_t * unverifiedMemData
Definition: cpu.hh:546
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::CheckerCPU::setSystem
void setSystem(System *system)
Definition: cpu.cc:97

Generated on Tue Sep 21 2021 12:24:24 for gem5 by doxygen 1.8.17