gem5  v21.1.0.2
iew.cc
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41 
42 // @todo: Fix the instantaneous communication among all the stages within
43 // iew. There's a clear delay between issue and execute, yet backwards
44 // communication happens simultaneously.
45 
46 #include "cpu/o3/iew.hh"
47 
48 #include <queue>
49 
50 #include "config/the_isa.hh"
51 #include "cpu/checker/cpu.hh"
52 #include "cpu/o3/dyn_inst.hh"
53 #include "cpu/o3/fu_pool.hh"
54 #include "cpu/o3/limits.hh"
55 #include "cpu/timebuf.hh"
56 #include "debug/Activity.hh"
57 #include "debug/Drain.hh"
58 #include "debug/IEW.hh"
59 #include "debug/O3PipeView.hh"
60 #include "params/O3CPU.hh"
61 
62 namespace gem5
63 {
64 
65 namespace o3
66 {
67 
68 IEW::IEW(CPU *_cpu, const O3CPUParams &params)
69  : issueToExecQueue(params.backComSize, params.forwardComSize),
70  cpu(_cpu),
71  instQueue(_cpu, this, params),
72  ldstQueue(_cpu, this, params),
73  fuPool(params.fuPool),
74  commitToIEWDelay(params.commitToIEWDelay),
75  renameToIEWDelay(params.renameToIEWDelay),
76  issueToExecuteDelay(params.issueToExecuteDelay),
77  dispatchWidth(params.dispatchWidth),
78  issueWidth(params.issueWidth),
79  wbNumInst(0),
80  wbCycle(0),
81  wbWidth(params.wbWidth),
82  numThreads(params.numThreads),
83  iewStats(cpu)
84 {
85  if (dispatchWidth > MaxWidth)
86  fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n"
87  "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
88  dispatchWidth, static_cast<int>(MaxWidth));
89  if (issueWidth > MaxWidth)
90  fatal("issueWidth (%d) is larger than compiled limit (%d),\n"
91  "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
92  issueWidth, static_cast<int>(MaxWidth));
93  if (wbWidth > MaxWidth)
94  fatal("wbWidth (%d) is larger than compiled limit (%d),\n"
95  "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
96  wbWidth, static_cast<int>(MaxWidth));
97 
98  _status = Active;
100  wbStatus = Idle;
101 
102  // Setup wire to read instructions coming from issue.
104 
105  // Instruction queue needs the queue between issue and execute.
107 
108  for (ThreadID tid = 0; tid < MaxThreads; tid++) {
109  dispatchStatus[tid] = Running;
110  fetchRedirect[tid] = false;
111  }
112 
113  updateLSQNextCycle = false;
114 
115  skidBufferMax = (renameToIEWDelay + 1) * params.renameWidth;
116 }
117 
118 std::string
119 IEW::name() const
120 {
121  return cpu->name() + ".iew";
122 }
123 
124 void
126 {
128  cpu->getProbeManager(), "Dispatch");
130  cpu->getProbeManager(), "Mispredict");
136  cpu->getProbeManager(), "Execute");
142  cpu->getProbeManager(), "ToCommit");
143 }
144 
146  : statistics::Group(cpu),
147  ADD_STAT(idleCycles, statistics::units::Cycle::get(),
148  "Number of cycles IEW is idle"),
149  ADD_STAT(squashCycles, statistics::units::Cycle::get(),
150  "Number of cycles IEW is squashing"),
151  ADD_STAT(blockCycles, statistics::units::Cycle::get(),
152  "Number of cycles IEW is blocking"),
153  ADD_STAT(unblockCycles, statistics::units::Cycle::get(),
154  "Number of cycles IEW is unblocking"),
155  ADD_STAT(dispatchedInsts, statistics::units::Count::get(),
156  "Number of instructions dispatched to IQ"),
157  ADD_STAT(dispSquashedInsts, statistics::units::Count::get(),
158  "Number of squashed instructions skipped by dispatch"),
159  ADD_STAT(dispLoadInsts, statistics::units::Count::get(),
160  "Number of dispatched load instructions"),
161  ADD_STAT(dispStoreInsts, statistics::units::Count::get(),
162  "Number of dispatched store instructions"),
163  ADD_STAT(dispNonSpecInsts, statistics::units::Count::get(),
164  "Number of dispatched non-speculative instructions"),
165  ADD_STAT(iqFullEvents, statistics::units::Count::get(),
166  "Number of times the IQ has become full, causing a stall"),
167  ADD_STAT(lsqFullEvents, statistics::units::Count::get(),
168  "Number of times the LSQ has become full, causing a stall"),
169  ADD_STAT(memOrderViolationEvents, statistics::units::Count::get(),
170  "Number of memory order violations"),
171  ADD_STAT(predictedTakenIncorrect, statistics::units::Count::get(),
172  "Number of branches that were predicted taken incorrectly"),
173  ADD_STAT(predictedNotTakenIncorrect, statistics::units::Count::get(),
174  "Number of branches that were predicted not taken incorrectly"),
175  ADD_STAT(branchMispredicts, statistics::units::Count::get(),
176  "Number of branch mispredicts detected at execute",
177  predictedTakenIncorrect + predictedNotTakenIncorrect),
178  executedInstStats(cpu),
179  ADD_STAT(instsToCommit, statistics::units::Count::get(),
180  "Cumulative count of insts sent to commit"),
181  ADD_STAT(writebackCount, statistics::units::Count::get(),
182  "Cumulative count of insts written-back"),
183  ADD_STAT(producerInst, statistics::units::Count::get(),
184  "Number of instructions producing a value"),
185  ADD_STAT(consumerInst, statistics::units::Count::get(),
186  "Number of instructions consuming a value"),
187  ADD_STAT(wbRate, statistics::units::Rate<
188  statistics::units::Count, statistics::units::Cycle>::get(),
189  "Insts written-back per cycle"),
190  ADD_STAT(wbFanout, statistics::units::Rate<
191  statistics::units::Count, statistics::units::Count>::get(),
192  "Average fanout of values written-back")
193 {
195  .init(cpu->numThreads)
197 
199  .init(cpu->numThreads)
201 
203  .init(cpu->numThreads)
205 
207  .init(cpu->numThreads)
209 
210  wbRate
213 
214  wbFanout
217 }
218 
220  : statistics::Group(cpu),
221  ADD_STAT(numInsts, statistics::units::Count::get(),
222  "Number of executed instructions"),
223  ADD_STAT(numLoadInsts, statistics::units::Count::get(),
224  "Number of load instructions executed"),
225  ADD_STAT(numSquashedInsts, statistics::units::Count::get(),
226  "Number of squashed instructions skipped in execute"),
227  ADD_STAT(numSwp, statistics::units::Count::get(),
228  "Number of swp insts executed"),
229  ADD_STAT(numNop, statistics::units::Count::get(),
230  "Number of nop insts executed"),
231  ADD_STAT(numRefs, statistics::units::Count::get(),
232  "Number of memory reference insts executed"),
233  ADD_STAT(numBranches, statistics::units::Count::get(),
234  "Number of branches executed"),
235  ADD_STAT(numStoreInsts, statistics::units::Count::get(),
236  "Number of stores executed"),
237  ADD_STAT(numRate, statistics::units::Rate<
238  statistics::units::Count, statistics::units::Cycle>::get(),
239  "Inst execution rate", numInsts / cpu->baseStats.numCycles)
240 {
242  .init(cpu->numThreads)
244 
245  numSwp
246  .init(cpu->numThreads)
248 
249  numNop
250  .init(cpu->numThreads)
252 
253  numRefs
254  .init(cpu->numThreads)
256 
258  .init(cpu->numThreads)
260 
264 
265  numRate
267 }
268 
269 void
271 {
272  for (ThreadID tid = 0; tid < numThreads; tid++) {
273  toRename->iewInfo[tid].usedIQ = true;
274  toRename->iewInfo[tid].freeIQEntries =
276 
277  toRename->iewInfo[tid].usedLSQ = true;
278  toRename->iewInfo[tid].freeLQEntries =
280  toRename->iewInfo[tid].freeSQEntries =
282  }
283 
284  // Initialize the checker's dcache port here
285  if (cpu->checker) {
286  cpu->checker->setDcachePort(&ldstQueue.getDataPort());
287  }
288 
290 }
291 
292 void
294 {
295  toRename->iewInfo[tid].usedIQ = true;
296  toRename->iewInfo[tid].freeIQEntries =
298 
299  toRename->iewInfo[tid].usedLSQ = true;
300  toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
301  toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
302 }
303 
304 void
306 {
307  timeBuffer = tb_ptr;
308 
309  // Setup wire to read information from time buffer, from commit.
311 
312  // Setup wire to write information back to previous stages.
313  toRename = timeBuffer->getWire(0);
314 
315  toFetch = timeBuffer->getWire(0);
316 
317  // Instruction queue also needs main time buffer.
318  instQueue.setTimeBuffer(tb_ptr);
319 }
320 
321 void
323 {
324  renameQueue = rq_ptr;
325 
326  // Setup wire to read information from rename queue.
328 }
329 
330 void
332 {
333  iewQueue = iq_ptr;
334 
335  // Setup wire to write instructions to commit.
336  toCommit = iewQueue->getWire(0);
337 }
338 
339 void
341 {
342  activeThreads = at_ptr;
343 
344  ldstQueue.setActiveThreads(at_ptr);
345  instQueue.setActiveThreads(at_ptr);
346 }
347 
348 void
350 {
351  scoreboard = sb_ptr;
352 }
353 
354 bool
356 {
357  bool drained = ldstQueue.isDrained() && instQueue.isDrained();
358 
359  for (ThreadID tid = 0; tid < numThreads; tid++) {
360  if (!insts[tid].empty()) {
361  DPRINTF(Drain, "%i: Insts not empty.\n", tid);
362  drained = false;
363  }
364  if (!skidBuffer[tid].empty()) {
365  DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
366  drained = false;
367  }
368  drained = drained && dispatchStatus[tid] == Running;
369  }
370 
371  // Also check the FU pool as instructions are "stored" in FU
372  // completion events until they are done and not accounted for
373  // above
374  if (drained && !fuPool->isDrained()) {
375  DPRINTF(Drain, "FU pool still busy.\n");
376  drained = false;
377  }
378 
379  return drained;
380 }
381 
382 void
384 {
385  assert(isDrained());
386 
389 }
390 
391 void
393 {
394  // Reset all state.
395  _status = Active;
396  exeStatus = Running;
397  wbStatus = Idle;
398 
401  fuPool->takeOverFrom();
402 
403  startupStage();
405 
406  for (ThreadID tid = 0; tid < numThreads; tid++) {
407  dispatchStatus[tid] = Running;
408  fetchRedirect[tid] = false;
409  }
410 
411  updateLSQNextCycle = false;
412 
413  for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
414  issueToExecQueue.advance();
415  }
416 }
417 
418 void
420 {
421  DPRINTF(IEW, "[tid:%i] Squashing all instructions.\n", tid);
422 
423  // Tell the IQ to start squashing.
424  instQueue.squash(tid);
425 
426  // Tell the LDSTQ to start squashing.
427  ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
428  updatedQueues = true;
429 
430  // Clear the skid buffer in case it has any data in it.
431  DPRINTF(IEW,
432  "Removing skidbuffer instructions until "
433  "[sn:%llu] [tid:%i]\n",
434  fromCommit->commitInfo[tid].doneSeqNum, tid);
435 
436  while (!skidBuffer[tid].empty()) {
437  if (skidBuffer[tid].front()->isLoad()) {
438  toRename->iewInfo[tid].dispatchedToLQ++;
439  }
440  if (skidBuffer[tid].front()->isStore() ||
441  skidBuffer[tid].front()->isAtomic()) {
442  toRename->iewInfo[tid].dispatchedToSQ++;
443  }
444 
445  toRename->iewInfo[tid].dispatched++;
446 
447  skidBuffer[tid].pop();
448  }
449 
450  emptyRenameInsts(tid);
451 }
452 
453 void
455 {
456  DPRINTF(IEW, "[tid:%i] [sn:%llu] Squashing from a specific instruction,"
457  " PC: %s "
458  "\n", tid, inst->seqNum, inst->pcState() );
459 
460  if (!toCommit->squash[tid] ||
461  inst->seqNum < toCommit->squashedSeqNum[tid]) {
462  toCommit->squash[tid] = true;
463  toCommit->squashedSeqNum[tid] = inst->seqNum;
464  toCommit->branchTaken[tid] = inst->pcState().branching();
465 
466  TheISA::PCState pc = inst->pcState();
467  inst->staticInst->advancePC(pc);
468 
469  toCommit->pc[tid] = pc;
470  toCommit->mispredictInst[tid] = inst;
471  toCommit->includeSquashInst[tid] = false;
472 
473  wroteToTimeBuffer = true;
474  }
475 
476 }
477 
478 void
480 {
481  DPRINTF(IEW, "[tid:%i] Memory violation, squashing violator and younger "
482  "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum);
483  // Need to include inst->seqNum in the following comparison to cover the
484  // corner case when a branch misprediction and a memory violation for the
485  // same instruction (e.g. load PC) are detected in the same cycle. In this
486  // case the memory violator should take precedence over the branch
487  // misprediction because it requires the violator itself to be included in
488  // the squash.
489  if (!toCommit->squash[tid] ||
490  inst->seqNum <= toCommit->squashedSeqNum[tid]) {
491  toCommit->squash[tid] = true;
492 
493  toCommit->squashedSeqNum[tid] = inst->seqNum;
494  toCommit->pc[tid] = inst->pcState();
495  toCommit->mispredictInst[tid] = NULL;
496 
497  // Must include the memory violator in the squash.
498  toCommit->includeSquashInst[tid] = true;
499 
500  wroteToTimeBuffer = true;
501  }
502 }
503 
504 void
506 {
507  DPRINTF(IEW, "[tid:%i] Blocking.\n", tid);
508 
509  if (dispatchStatus[tid] != Blocked &&
510  dispatchStatus[tid] != Unblocking) {
511  toRename->iewBlock[tid] = true;
512  wroteToTimeBuffer = true;
513  }
514 
515  // Add the current inputs to the skid buffer so they can be
516  // reprocessed when this stage unblocks.
517  skidInsert(tid);
518 
519  dispatchStatus[tid] = Blocked;
520 }
521 
522 void
524 {
525  DPRINTF(IEW, "[tid:%i] Reading instructions out of the skid "
526  "buffer %u.\n",tid, tid);
527 
528  // If the skid bufffer is empty, signal back to previous stages to unblock.
529  // Also switch status to running.
530  if (skidBuffer[tid].empty()) {
531  toRename->iewUnblock[tid] = true;
532  wroteToTimeBuffer = true;
533  DPRINTF(IEW, "[tid:%i] Done unblocking.\n",tid);
534  dispatchStatus[tid] = Running;
535  }
536 }
537 
538 void
540 {
542 }
543 
544 void
546 {
548 }
549 
550 void
552 {
553  instQueue.replayMemInst(inst);
554 }
555 
556 void
558 {
559  instQueue.blockMemInst(inst);
560 }
561 
562 void
564 {
566 }
567 
568 void
570 {
571  // This function should not be called after writebackInsts in a
572  // single cycle. That will cause problems with an instruction
573  // being added to the queue to commit without being processed by
574  // writebackInsts prior to being sent to commit.
575 
576  // First check the time slot that this instruction will write
577  // to. If there are free write ports at the time, then go ahead
578  // and write the instruction to that time. If there are not,
579  // keep looking back to see where's the first time there's a
580  // free slot.
581  while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
582  ++wbNumInst;
583  if (wbNumInst == wbWidth) {
584  ++wbCycle;
585  wbNumInst = 0;
586  }
587  }
588 
589  DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
591  // Add finished instruction to queue to commit.
592  (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
593  (*iewQueue)[wbCycle].size++;
594 }
595 
596 void
598 {
599  DynInstPtr inst = NULL;
600 
601  while (!insts[tid].empty()) {
602  inst = insts[tid].front();
603 
604  insts[tid].pop();
605 
606  DPRINTF(IEW,"[tid:%i] Inserting [sn:%lli] PC:%s into "
607  "dispatch skidBuffer %i\n",tid, inst->seqNum,
608  inst->pcState(),tid);
609 
610  skidBuffer[tid].push(inst);
611  }
612 
613  assert(skidBuffer[tid].size() <= skidBufferMax &&
614  "Skidbuffer Exceeded Max Size");
615 }
616 
617 int
619 {
620  int max=0;
621 
622  std::list<ThreadID>::iterator threads = activeThreads->begin();
624 
625  while (threads != end) {
626  ThreadID tid = *threads++;
627  unsigned thread_count = skidBuffer[tid].size();
628  if (max < thread_count)
629  max = thread_count;
630  }
631 
632  return max;
633 }
634 
635 bool
637 {
638  std::list<ThreadID>::iterator threads = activeThreads->begin();
640 
641  while (threads != end) {
642  ThreadID tid = *threads++;
643 
644  if (!skidBuffer[tid].empty())
645  return false;
646  }
647 
648  return true;
649 }
650 
651 void
653 {
654  bool any_unblocking = false;
655 
656  std::list<ThreadID>::iterator threads = activeThreads->begin();
658 
659  while (threads != end) {
660  ThreadID tid = *threads++;
661 
662  if (dispatchStatus[tid] == Unblocking) {
663  any_unblocking = true;
664  break;
665  }
666  }
667 
668  // If there are no ready instructions waiting to be scheduled by the IQ,
669  // and there's no stores waiting to write back, and dispatch is not
670  // unblocking, then there is no internal activity for the IEW stage.
672  if (_status == Active && !instQueue.hasReadyInsts() &&
673  !ldstQueue.willWB() && !any_unblocking) {
674  DPRINTF(IEW, "IEW switching to idle\n");
675 
676  deactivateStage();
677 
678  _status = Inactive;
679  } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
680  ldstQueue.willWB() ||
681  any_unblocking)) {
682  // Otherwise there is internal activity. Set to active.
683  DPRINTF(IEW, "IEW switching to active\n");
684 
685  activateStage();
686 
687  _status = Active;
688  }
689 }
690 
691 bool
693 {
694  bool ret_val(false);
695 
696  if (fromCommit->commitInfo[tid].robSquashing) {
697  DPRINTF(IEW,"[tid:%i] Stall from Commit stage detected.\n",tid);
698  ret_val = true;
699  } else if (instQueue.isFull(tid)) {
700  DPRINTF(IEW,"[tid:%i] Stall: IQ is full.\n",tid);
701  ret_val = true;
702  }
703 
704  return ret_val;
705 }
706 
707 void
709 {
710  // Check if there's a squash signal, squash if there is
711  // Check stall signals, block if there is.
712  // If status was Blocked
713  // if so then go to unblocking
714  // If status was Squashing
715  // check if squashing is not high. Switch to running this cycle.
716 
717  if (fromCommit->commitInfo[tid].squash) {
718  squash(tid);
719 
720  if (dispatchStatus[tid] == Blocked ||
721  dispatchStatus[tid] == Unblocking) {
722  toRename->iewUnblock[tid] = true;
723  wroteToTimeBuffer = true;
724  }
725 
726  dispatchStatus[tid] = Squashing;
727  fetchRedirect[tid] = false;
728  return;
729  }
730 
731  if (fromCommit->commitInfo[tid].robSquashing) {
732  DPRINTF(IEW, "[tid:%i] ROB is still squashing.\n", tid);
733 
734  dispatchStatus[tid] = Squashing;
735  emptyRenameInsts(tid);
736  wroteToTimeBuffer = true;
737  }
738 
739  if (checkStall(tid)) {
740  block(tid);
741  dispatchStatus[tid] = Blocked;
742  return;
743  }
744 
745  if (dispatchStatus[tid] == Blocked) {
746  // Status from previous cycle was blocked, but there are no more stall
747  // conditions. Switch over to unblocking.
748  DPRINTF(IEW, "[tid:%i] Done blocking, switching to unblocking.\n",
749  tid);
750 
751  dispatchStatus[tid] = Unblocking;
752 
753  unblock(tid);
754 
755  return;
756  }
757 
758  if (dispatchStatus[tid] == Squashing) {
759  // Switch status to running if rename isn't being told to block or
760  // squash this cycle.
761  DPRINTF(IEW, "[tid:%i] Done squashing, switching to running.\n",
762  tid);
763 
764  dispatchStatus[tid] = Running;
765 
766  return;
767  }
768 }
769 
770 void
772 {
773  int insts_from_rename = fromRename->size;
774 #ifdef DEBUG
775  for (ThreadID tid = 0; tid < numThreads; tid++)
776  assert(insts[tid].empty());
777 #endif
778  for (int i = 0; i < insts_from_rename; ++i) {
779  insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
780  }
781 }
782 
783 void
785 {
786  DPRINTF(IEW, "[tid:%i] Removing incoming rename instructions\n", tid);
787 
788  while (!insts[tid].empty()) {
789 
790  if (insts[tid].front()->isLoad()) {
791  toRename->iewInfo[tid].dispatchedToLQ++;
792  }
793  if (insts[tid].front()->isStore() ||
794  insts[tid].front()->isAtomic()) {
795  toRename->iewInfo[tid].dispatchedToSQ++;
796  }
797 
798  toRename->iewInfo[tid].dispatched++;
799 
800  insts[tid].pop();
801  }
802 }
803 
804 void
806 {
807  cpu->wakeCPU();
808 }
809 
810 void
812 {
813  DPRINTF(Activity, "Activity this cycle.\n");
815 }
816 
817 void
819 {
820  DPRINTF(Activity, "Activating stage.\n");
822 }
823 
824 void
826 {
827  DPRINTF(Activity, "Deactivating stage.\n");
829 }
830 
831 void
833 {
834  // If status is Running or idle,
835  // call dispatchInsts()
836  // If status is Unblocking,
837  // buffer any instructions coming from rename
838  // continue trying to empty skid buffer
839  // check if stall conditions have passed
840 
841  if (dispatchStatus[tid] == Blocked) {
843 
844  } else if (dispatchStatus[tid] == Squashing) {
846  }
847 
848  // Dispatch should try to dispatch as many instructions as its bandwidth
849  // will allow, as long as it is not currently blocked.
850  if (dispatchStatus[tid] == Running ||
851  dispatchStatus[tid] == Idle) {
852  DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
853  "dispatch.\n", tid);
854 
855  dispatchInsts(tid);
856  } else if (dispatchStatus[tid] == Unblocking) {
857  // Make sure that the skid buffer has something in it if the
858  // status is unblocking.
859  assert(!skidsEmpty());
860 
861  // If the status was unblocking, then instructions from the skid
862  // buffer were used. Remove those instructions and handle
863  // the rest of unblocking.
864  dispatchInsts(tid);
865 
867 
868  if (fromRename->size != 0) {
869  // Add the current inputs to the skid buffer so they can be
870  // reprocessed when this stage unblocks.
871  skidInsert(tid);
872  }
873 
874  unblock(tid);
875  }
876 }
877 
878 void
880 {
881  // Obtain instructions from skid buffer if unblocking, or queue from rename
882  // otherwise.
883  std::queue<DynInstPtr> &insts_to_dispatch =
884  dispatchStatus[tid] == Unblocking ?
885  skidBuffer[tid] : insts[tid];
886 
887  int insts_to_add = insts_to_dispatch.size();
888 
889  DynInstPtr inst;
890  bool add_to_iq = false;
891  int dis_num_inst = 0;
892 
893  // Loop through the instructions, putting them in the instruction
894  // queue.
895  for ( ; dis_num_inst < insts_to_add &&
896  dis_num_inst < dispatchWidth;
897  ++dis_num_inst)
898  {
899  inst = insts_to_dispatch.front();
900 
901  if (dispatchStatus[tid] == Unblocking) {
902  DPRINTF(IEW, "[tid:%i] Issue: Examining instruction from skid "
903  "buffer\n", tid);
904  }
905 
906  // Make sure there's a valid instruction there.
907  assert(inst);
908 
909  DPRINTF(IEW, "[tid:%i] Issue: Adding PC %s [sn:%lli] [tid:%i] to "
910  "IQ.\n",
911  tid, inst->pcState(), inst->seqNum, inst->threadNumber);
912 
913  // Be sure to mark these instructions as ready so that the
914  // commit stage can go ahead and execute them, and mark
915  // them as issued so the IQ doesn't reprocess them.
916 
917  // Check for squashed instructions.
918  if (inst->isSquashed()) {
919  DPRINTF(IEW, "[tid:%i] Issue: Squashed instruction encountered, "
920  "not adding to IQ.\n", tid);
921 
923 
924  insts_to_dispatch.pop();
925 
926  //Tell Rename That An Instruction has been processed
927  if (inst->isLoad()) {
928  toRename->iewInfo[tid].dispatchedToLQ++;
929  }
930  if (inst->isStore() || inst->isAtomic()) {
931  toRename->iewInfo[tid].dispatchedToSQ++;
932  }
933 
934  toRename->iewInfo[tid].dispatched++;
935 
936  continue;
937  }
938 
939  // Check for full conditions.
940  if (instQueue.isFull(tid)) {
941  DPRINTF(IEW, "[tid:%i] Issue: IQ has become full.\n", tid);
942 
943  // Call function to start blocking.
944  block(tid);
945 
946  // Set unblock to false. Special case where we are using
947  // skidbuffer (unblocking) instructions but then we still
948  // get full in the IQ.
949  toRename->iewUnblock[tid] = false;
950 
952  break;
953  }
954 
955  // Check LSQ if inst is LD/ST
956  if ((inst->isAtomic() && ldstQueue.sqFull(tid)) ||
957  (inst->isLoad() && ldstQueue.lqFull(tid)) ||
958  (inst->isStore() && ldstQueue.sqFull(tid))) {
959  DPRINTF(IEW, "[tid:%i] Issue: %s has become full.\n",tid,
960  inst->isLoad() ? "LQ" : "SQ");
961 
962  // Call function to start blocking.
963  block(tid);
964 
965  // Set unblock to false. Special case where we are using
966  // skidbuffer (unblocking) instructions but then we still
967  // get full in the IQ.
968  toRename->iewUnblock[tid] = false;
969 
971  break;
972  }
973 
974  // hardware transactional memory
975  // CPU needs to track transactional state in program order.
976  const int numHtmStarts = ldstQueue.numHtmStarts(tid);
977  const int numHtmStops = ldstQueue.numHtmStops(tid);
978  const int htmDepth = numHtmStarts - numHtmStops;
979 
980  if (htmDepth > 0) {
981  inst->setHtmTransactionalState(ldstQueue.getLatestHtmUid(tid),
982  htmDepth);
983  } else {
984  inst->clearHtmTransactionalState();
985  }
986 
987 
988  // Otherwise issue the instruction just fine.
989  if (inst->isAtomic()) {
990  DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
991  "encountered, adding to LSQ.\n", tid);
992 
993  ldstQueue.insertStore(inst);
994 
996 
997  // AMOs need to be set as "canCommit()"
998  // so that commit can process them when they reach the
999  // head of commit.
1000  inst->setCanCommit();
1001  instQueue.insertNonSpec(inst);
1002  add_to_iq = false;
1003 
1005 
1006  toRename->iewInfo[tid].dispatchedToSQ++;
1007  } else if (inst->isLoad()) {
1008  DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
1009  "encountered, adding to LSQ.\n", tid);
1010 
1011  // Reserve a spot in the load store queue for this
1012  // memory access.
1013  ldstQueue.insertLoad(inst);
1014 
1016 
1017  add_to_iq = true;
1018 
1019  toRename->iewInfo[tid].dispatchedToLQ++;
1020  } else if (inst->isStore()) {
1021  DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
1022  "encountered, adding to LSQ.\n", tid);
1023 
1024  ldstQueue.insertStore(inst);
1025 
1027 
1028  if (inst->isStoreConditional()) {
1029  // Store conditionals need to be set as "canCommit()"
1030  // so that commit can process them when they reach the
1031  // head of commit.
1032  // @todo: This is somewhat specific to Alpha.
1033  inst->setCanCommit();
1034  instQueue.insertNonSpec(inst);
1035  add_to_iq = false;
1036 
1038  } else {
1039  add_to_iq = true;
1040  }
1041 
1042  toRename->iewInfo[tid].dispatchedToSQ++;
1043  } else if (inst->isReadBarrier() || inst->isWriteBarrier()) {
1044  // Same as non-speculative stores.
1045  inst->setCanCommit();
1046  instQueue.insertBarrier(inst);
1047  add_to_iq = false;
1048  } else if (inst->isNop()) {
1049  DPRINTF(IEW, "[tid:%i] Issue: Nop instruction encountered, "
1050  "skipping.\n", tid);
1051 
1052  inst->setIssued();
1053  inst->setExecuted();
1054  inst->setCanCommit();
1055 
1056  instQueue.recordProducer(inst);
1057 
1059 
1060  add_to_iq = false;
1061  } else {
1062  assert(!inst->isExecuted());
1063  add_to_iq = true;
1064  }
1065 
1066  if (add_to_iq && inst->isNonSpeculative()) {
1067  DPRINTF(IEW, "[tid:%i] Issue: Nonspeculative instruction "
1068  "encountered, skipping.\n", tid);
1069 
1070  // Same as non-speculative stores.
1071  inst->setCanCommit();
1072 
1073  // Specifically insert it as nonspeculative.
1074  instQueue.insertNonSpec(inst);
1075 
1077 
1078  add_to_iq = false;
1079  }
1080 
1081  // If the instruction queue is not full, then add the
1082  // instruction.
1083  if (add_to_iq) {
1084  instQueue.insert(inst);
1085  }
1086 
1087  insts_to_dispatch.pop();
1088 
1089  toRename->iewInfo[tid].dispatched++;
1090 
1092 
1093 #if TRACING_ON
1094  inst->dispatchTick = curTick() - inst->fetchTick;
1095 #endif
1096  ppDispatch->notify(inst);
1097  }
1098 
1099  if (!insts_to_dispatch.empty()) {
1100  DPRINTF(IEW,"[tid:%i] Issue: Bandwidth Full. Blocking.\n", tid);
1101  block(tid);
1102  toRename->iewUnblock[tid] = false;
1103  }
1104 
1105  if (dispatchStatus[tid] == Idle && dis_num_inst) {
1106  dispatchStatus[tid] = Running;
1107 
1108  updatedQueues = true;
1109  }
1110 
1111  dis_num_inst = 0;
1112 }
1113 
1114 void
1116 {
1117  int inst = 0;
1118 
1119  std::cout << "Available Instructions: ";
1120 
1121  while (fromIssue->insts[inst]) {
1122 
1123  if (inst%3==0) std::cout << "\n\t";
1124 
1125  std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1126  << " TN: " << fromIssue->insts[inst]->threadNumber
1127  << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1128 
1129  inst++;
1130 
1131  }
1132 
1133  std::cout << "\n";
1134 }
1135 
1136 void
1138 {
1139  wbNumInst = 0;
1140  wbCycle = 0;
1141 
1142  std::list<ThreadID>::iterator threads = activeThreads->begin();
1144 
1145  while (threads != end) {
1146  ThreadID tid = *threads++;
1147  fetchRedirect[tid] = false;
1148  }
1149 
1150  // Uncomment this if you want to see all available instructions.
1151  // @todo This doesn't actually work anymore, we should fix it.
1152 // printAvailableInsts();
1153 
1154  // Execute/writeback any instructions that are available.
1155  int insts_to_execute = fromIssue->size;
1156  int inst_num = 0;
1157  for (; inst_num < insts_to_execute;
1158  ++inst_num) {
1159 
1160  DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1161 
1163 
1164  DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%llu].\n",
1165  inst->pcState(), inst->threadNumber,inst->seqNum);
1166 
1167  // Notify potential listeners that this instruction has started
1168  // executing
1169  ppExecute->notify(inst);
1170 
1171  // Check if the instruction is squashed; if so then skip it
1172  if (inst->isSquashed()) {
1173  DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1174  " [sn:%llu]\n", inst->pcState(), inst->threadNumber,
1175  inst->seqNum);
1176 
1177  // Consider this instruction executed so that commit can go
1178  // ahead and retire the instruction.
1179  inst->setExecuted();
1180 
1181  // Not sure if I should set this here or just let commit try to
1182  // commit any squashed instructions. I like the latter a bit more.
1183  inst->setCanCommit();
1184 
1186 
1187  continue;
1188  }
1189 
1190  Fault fault = NoFault;
1191 
1192  // Execute instruction.
1193  // Note that if the instruction faults, it will be handled
1194  // at the commit stage.
1195  if (inst->isMemRef()) {
1196  DPRINTF(IEW, "Execute: Calculating address for memory "
1197  "reference.\n");
1198 
1199  // Tell the LDSTQ to execute this instruction (if it is a load).
1200  if (inst->isAtomic()) {
1201  // AMOs are treated like store requests
1202  fault = ldstQueue.executeStore(inst);
1203 
1204  if (inst->isTranslationDelayed() &&
1205  fault == NoFault) {
1206  // A hw page table walk is currently going on; the
1207  // instruction must be deferred.
1208  DPRINTF(IEW, "Execute: Delayed translation, deferring "
1209  "store.\n");
1210  instQueue.deferMemInst(inst);
1211  continue;
1212  }
1213  } else if (inst->isLoad()) {
1214  // Loads will mark themselves as executed, and their writeback
1215  // event adds the instruction to the queue to commit
1216  fault = ldstQueue.executeLoad(inst);
1217 
1218  if (inst->isTranslationDelayed() &&
1219  fault == NoFault) {
1220  // A hw page table walk is currently going on; the
1221  // instruction must be deferred.
1222  DPRINTF(IEW, "Execute: Delayed translation, deferring "
1223  "load.\n");
1224  instQueue.deferMemInst(inst);
1225  continue;
1226  }
1227 
1228  if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1229  inst->fault = NoFault;
1230  }
1231  } else if (inst->isStore()) {
1232  fault = ldstQueue.executeStore(inst);
1233 
1234  if (inst->isTranslationDelayed() &&
1235  fault == NoFault) {
1236  // A hw page table walk is currently going on; the
1237  // instruction must be deferred.
1238  DPRINTF(IEW, "Execute: Delayed translation, deferring "
1239  "store.\n");
1240  instQueue.deferMemInst(inst);
1241  continue;
1242  }
1243 
1244  // If the store had a fault then it may not have a mem req
1245  if (fault != NoFault || !inst->readPredicate() ||
1246  !inst->isStoreConditional()) {
1247  // If the instruction faulted, then we need to send it
1248  // along to commit without the instruction completing.
1249  // Send this instruction to commit, also make sure iew
1250  // stage realizes there is activity.
1251  inst->setExecuted();
1252  instToCommit(inst);
1254  }
1255 
1256  // Store conditionals will mark themselves as
1257  // executed, and their writeback event will add the
1258  // instruction to the queue to commit.
1259  } else {
1260  panic("Unexpected memory type!\n");
1261  }
1262 
1263  } else {
1264  // If the instruction has already faulted, then skip executing it.
1265  // Such case can happen when it faulted during ITLB translation.
1266  // If we execute the instruction (even if it's a nop) the fault
1267  // will be replaced and we will lose it.
1268  if (inst->getFault() == NoFault) {
1269  inst->execute();
1270  if (!inst->readPredicate())
1271  inst->forwardOldRegs();
1272  }
1273 
1274  inst->setExecuted();
1275 
1276  instToCommit(inst);
1277  }
1278 
1279  updateExeInstStats(inst);
1280 
1281  // Check if branch prediction was correct, if not then we need
1282  // to tell commit to squash in flight instructions. Only
1283  // handle this if there hasn't already been something that
1284  // redirects fetch in this group of instructions.
1285 
1286  // This probably needs to prioritize the redirects if a different
1287  // scheduler is used. Currently the scheduler schedules the oldest
1288  // instruction first, so the branch resolution order will be correct.
1289  ThreadID tid = inst->threadNumber;
1290 
1291  if (!fetchRedirect[tid] ||
1292  !toCommit->squash[tid] ||
1293  toCommit->squashedSeqNum[tid] > inst->seqNum) {
1294 
1295  // Prevent testing for misprediction on load instructions,
1296  // that have not been executed.
1297  bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1298 
1299  if (inst->mispredicted() && !loadNotExecuted) {
1300  fetchRedirect[tid] = true;
1301 
1302  DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1303  "Branch mispredict detected.\n",
1304  tid,inst->seqNum);
1305  DPRINTF(IEW, "[tid:%i] [sn:%llu] "
1306  "Predicted target was PC: %s\n",
1307  tid,inst->seqNum,inst->readPredTarg());
1308  DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1309  "Redirecting fetch to PC: %s\n",
1310  tid,inst->seqNum,inst->pcState());
1311  // If incorrect, then signal the ROB that it must be squashed.
1312  squashDueToBranch(inst, tid);
1313 
1314  ppMispredict->notify(inst);
1315 
1316  if (inst->readPredTaken()) {
1318  } else {
1320  }
1321  } else if (ldstQueue.violation(tid)) {
1322  assert(inst->isMemRef());
1323  // If there was an ordering violation, then get the
1324  // DynInst that caused the violation. Note that this
1325  // clears the violation signal.
1326  DynInstPtr violator;
1327  violator = ldstQueue.getMemDepViolator(tid);
1328 
1329  DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1330  "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1331  violator->pcState(), violator->seqNum,
1332  inst->pcState(), inst->seqNum, inst->physEffAddr);
1333 
1334  fetchRedirect[tid] = true;
1335 
1336  // Tell the instruction queue that a violation has occured.
1337  instQueue.violation(inst, violator);
1338 
1339  // Squash.
1340  squashDueToMemOrder(violator, tid);
1341 
1343  }
1344  } else {
1345  // Reset any state associated with redirects that will not
1346  // be used.
1347  if (ldstQueue.violation(tid)) {
1348  assert(inst->isMemRef());
1349 
1350  DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1351 
1352  DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1353  "%s, inst PC: %s. Addr is: %#x.\n",
1354  violator->pcState(), inst->pcState(),
1355  inst->physEffAddr);
1356  DPRINTF(IEW, "Violation will not be handled because "
1357  "already squashing\n");
1358 
1360  }
1361  }
1362  }
1363 
1364  // Update and record activity if we processed any instructions.
1365  if (inst_num) {
1366  if (exeStatus == Idle) {
1367  exeStatus = Running;
1368  }
1369 
1370  updatedQueues = true;
1371 
1373  }
1374 
1375  // Need to reset this in case a writeback event needs to write into the
1376  // iew queue. That way the writeback event will write into the correct
1377  // spot in the queue.
1378  wbNumInst = 0;
1379 
1380 }
1381 
1382 void
1384 {
1385  // Loop through the head of the time buffer and wake any
1386  // dependents. These instructions are about to write back. Also
1387  // mark scoreboard that this instruction is finally complete.
1388  // Either have IEW have direct access to scoreboard, or have this
1389  // as part of backwards communication.
1390  for (int inst_num = 0; inst_num < wbWidth &&
1391  toCommit->insts[inst_num]; inst_num++) {
1392  DynInstPtr inst = toCommit->insts[inst_num];
1393  ThreadID tid = inst->threadNumber;
1394 
1395  DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1396  inst->seqNum, inst->pcState());
1397 
1398  iewStats.instsToCommit[tid]++;
1399  // Notify potential listeners that execution is complete for this
1400  // instruction.
1401  ppToCommit->notify(inst);
1402 
1403  // Some instructions will be sent to commit without having
1404  // executed because they need commit to handle them.
1405  // E.g. Strictly ordered loads have not actually executed when they
1406  // are first sent to commit. Instead commit must tell the LSQ
1407  // when it's ready to execute the strictly ordered load.
1408  if (!inst->isSquashed() && inst->isExecuted() &&
1409  inst->getFault() == NoFault) {
1410  int dependents = instQueue.wakeDependents(inst);
1411 
1412  for (int i = 0; i < inst->numDestRegs(); i++) {
1413  // Mark register as ready if not pinned
1414  if (inst->regs.renamedDestIdx(i)->
1415  getNumPinnedWritesToComplete() == 0) {
1416  DPRINTF(IEW,"Setting Destination Register %i (%s)\n",
1417  inst->regs.renamedDestIdx(i)->index(),
1418  inst->regs.renamedDestIdx(i)->className());
1419  scoreboard->setReg(inst->regs.renamedDestIdx(i));
1420  }
1421  }
1422 
1423  if (dependents) {
1424  iewStats.producerInst[tid]++;
1425  iewStats.consumerInst[tid]+= dependents;
1426  }
1427  iewStats.writebackCount[tid]++;
1428  }
1429  }
1430 }
1431 
1432 void
1434 {
1435  wbNumInst = 0;
1436  wbCycle = 0;
1437 
1438  wroteToTimeBuffer = false;
1439  updatedQueues = false;
1440 
1441  ldstQueue.tick();
1442 
1443  sortInsts();
1444 
1445  // Free function units marked as being freed this cycle.
1447 
1448  std::list<ThreadID>::iterator threads = activeThreads->begin();
1450 
1451  // Check stall and squash signals, dispatch any instructions.
1452  while (threads != end) {
1453  ThreadID tid = *threads++;
1454 
1455  DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1456 
1457  checkSignalsAndUpdate(tid);
1458  dispatch(tid);
1459  }
1460 
1461  if (exeStatus != Squashing) {
1462  executeInsts();
1463 
1464  writebackInsts();
1465 
1466  // Have the instruction queue try to schedule any ready instructions.
1467  // (In actuality, this scheduling is for instructions that will
1468  // be executed next cycle.)
1470 
1471  // Also should advance its own time buffers if the stage ran.
1472  // Not the best place for it, but this works (hopefully).
1473  issueToExecQueue.advance();
1474  }
1475 
1476  bool broadcast_free_entries = false;
1477 
1479  exeStatus = Idle;
1480  updateLSQNextCycle = false;
1481 
1482  broadcast_free_entries = true;
1483  }
1484 
1485  // Writeback any stores using any leftover bandwidth.
1487 
1488  // Check the committed load/store signals to see if there's a load
1489  // or store to commit. Also check if it's being told to execute a
1490  // nonspeculative instruction.
1491  // This is pretty inefficient...
1492 
1493  threads = activeThreads->begin();
1494  while (threads != end) {
1495  ThreadID tid = (*threads++);
1496 
1497  DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1498 
1499  // Update structures based on instructions committed.
1500  if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1501  !fromCommit->commitInfo[tid].squash &&
1502  !fromCommit->commitInfo[tid].robSquashing) {
1503 
1504  ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1505 
1506  ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1507 
1508  updateLSQNextCycle = true;
1509  instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1510  }
1511 
1512  if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1513 
1514  //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1515  if (fromCommit->commitInfo[tid].strictlyOrdered) {
1517  fromCommit->commitInfo[tid].strictlyOrderedLoad);
1518  fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit();
1519  } else {
1521  fromCommit->commitInfo[tid].nonSpecSeqNum);
1522  }
1523  }
1524 
1525  if (broadcast_free_entries) {
1526  toFetch->iewInfo[tid].iqCount =
1527  instQueue.getCount(tid);
1528  toFetch->iewInfo[tid].ldstqCount =
1529  ldstQueue.getCount(tid);
1530 
1531  toRename->iewInfo[tid].usedIQ = true;
1532  toRename->iewInfo[tid].freeIQEntries =
1534  toRename->iewInfo[tid].usedLSQ = true;
1535 
1536  toRename->iewInfo[tid].freeLQEntries =
1538  toRename->iewInfo[tid].freeSQEntries =
1540 
1541  wroteToTimeBuffer = true;
1542  }
1543 
1544  DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1545  tid, toRename->iewInfo[tid].dispatched);
1546  }
1547 
1548  DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1549  "LQ has %i free entries. SQ has %i free entries.\n",
1552 
1553  updateStatus();
1554 
1555  if (wroteToTimeBuffer) {
1556  DPRINTF(Activity, "Activity this cycle.\n");
1558  }
1559 }
1560 
1561 void
1563 {
1564  ThreadID tid = inst->threadNumber;
1565 
1567 
1568 #if TRACING_ON
1569  if (debug::O3PipeView) {
1570  inst->completeTick = curTick() - inst->fetchTick;
1571  }
1572 #endif
1573 
1574  //
1575  // Control operations
1576  //
1577  if (inst->isControl())
1579 
1580  //
1581  // Memory operations
1582  //
1583  if (inst->isMemRef()) {
1585 
1586  if (inst->isLoad()) {
1588  }
1589  }
1590 }
1591 
1592 void
1594 {
1595  ThreadID tid = inst->threadNumber;
1596 
1597  if (!fetchRedirect[tid] ||
1598  !toCommit->squash[tid] ||
1599  toCommit->squashedSeqNum[tid] > inst->seqNum) {
1600 
1601  if (inst->mispredicted()) {
1602  fetchRedirect[tid] = true;
1603 
1604  DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1605  "Branch mispredict detected.\n",
1606  tid,inst->seqNum);
1607  DPRINTF(IEW, "[tid:%i] [sn:%llu] Predicted target "
1608  "was PC:%#x, NPC:%#x\n",
1609  tid,inst->seqNum,
1610  inst->predInstAddr(), inst->predNextInstAddr());
1611  DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1612  "Redirecting fetch to PC: %#x, "
1613  "NPC: %#x.\n",
1614  tid,inst->seqNum,
1615  inst->nextInstAddr(),
1616  inst->nextInstAddr());
1617  // If incorrect, then signal the ROB that it must be squashed.
1618  squashDueToBranch(inst, tid);
1619 
1620  if (inst->readPredTaken()) {
1622  } else {
1624  }
1625  }
1626  }
1627 }
1628 
1629 } // namespace o3
1630 } // namespace gem5
gem5::o3::InstructionQueue::rescheduleMemInst
void rescheduleMemInst(const DynInstPtr &resched_inst)
Reschedules a memory instruction.
Definition: inst_queue.cc:1085
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::o3::LSQ::insertStore
void insertStore(const DynInstPtr &store_inst)
Inserts a store into the LSQ.
Definition: lsq.cc:237
gem5::o3::InstructionQueue::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: inst_queue.cc:461
gem5::o3::IEW::skidCount
int skidCount()
Returns the max of the number of entries in all of the skid buffers.
Definition: iew.cc:618
gem5::o3::IEW::IEWStats::unblockCycles
statistics::Scalar unblockCycles
Stat for total number of unblocking cycles.
Definition: iew.hh:429
gem5::o3::IEW::IEWStats::dispStoreInsts
statistics::Scalar dispStoreInsts
Stat for total number of dispatched store instructions.
Definition: iew.hh:437
gem5::o3::LSQ::commitLoads
void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
Commits loads up until the given sequence number for a specific thread.
Definition: lsq.cc:261
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::o3::IEW::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets main time buffer used for backwards communication.
Definition: iew.cc:305
gem5::o3::IEW::toFetch
TimeBuffer< TimeStruct >::wire toFetch
Wire to write information heading to previous stages.
Definition: iew.hh:303
gem5::o3::IEW::insts
std::queue< DynInstPtr > insts[MaxThreads]
Queue of all instructions coming from rename this cycle.
Definition: iew.hh:333
gem5::o3::IEW::skidsEmpty
bool skidsEmpty()
Returns if all of the skid buffers are empty.
Definition: iew.cc:636
gem5::o3::IEW::IEWStats::executedInstStats
gem5::o3::IEW::IEWStats::ExecutedInstStats executedInstStats
gem5::o3::IEW::ppToCommit
ProbePointArg< DynInstPtr > * ppToCommit
To probe when instruction execution is complete.
Definition: iew.hh:126
gem5::o3::IEW::IEWStats::wbRate
statistics::Formula wbRate
Number of instructions per cycle written back.
Definition: iew.hh:488
gem5::o3::IEW::renameQueue
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue interface.
Definition: iew.hh:312
gem5::o3::IEW::IEWStats::blockCycles
statistics::Scalar blockCycles
Stat for total number of blocking cycles.
Definition: iew.hh:427
gem5::o3::InstructionQueue::isFull
bool isFull()
Returns whether or not the IQ is full.
Definition: inst_queue.cc:523
gem5::o3::IEW::IEWStats::producerInst
statistics::Vector producerInst
Number of instructions that wake consumers.
Definition: iew.hh:484
gem5::o3::IEW::checkSignalsAndUpdate
void checkSignalsAndUpdate(ThreadID tid)
Processes inputs and changes state accordingly.
Definition: iew.cc:708
gem5::o3::IEW::updateExeInstStats
void updateExeInstStats(const DynInstPtr &inst)
Updates execution stats based on the instruction.
Definition: iew.cc:1562
gem5::o3::LSQ::getCount
int getCount()
Returns the number of instructions in all of the queues.
Definition: lsq.cc:464
gem5::o3::LSQ::writebackStores
void writebackStores()
Attempts to write back stores until all cache ports are used or the interface becomes blocked.
Definition: lsq.cc:273
gem5::o3::LSQ::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets the pointer to the list of active threads.
Definition: lsq.cc:138
gem5::o3::IEW::dispatchStatus
StageStatus dispatchStatus[MaxThreads]
Dispatch status.
Definition: iew.hh:114
gem5::o3::IEW::updateStatus
void updateStatus()
Updates overall IEW status based on all of the stages' statuses.
Definition: iew.cc:652
gem5::o3::IEW::replayMemInst
void replayMemInst(const DynInstPtr &inst)
Re-executes all rescheduled memory instructions.
Definition: iew.cc:551
gem5::o3::IEW::IEWStats::ExecutedInstStats::numStoreInsts
statistics::Formula numStoreInsts
Number of executed store instructions.
Definition: iew.hh:474
gem5::o3::IEW::IEWStats::ExecutedInstStats::numRefs
statistics::Vector numRefs
Number of executed meomory references.
Definition: iew.hh:470
gem5::o3::IEW::ppMispredict
ProbePointArg< DynInstPtr > * ppMispredict
Probe points.
Definition: iew.hh:121
gem5::o3::IEW::Active
@ Active
Definition: iew.hh:95
gem5::o3::IEW::Unblocking
@ Unblocking
Definition: iew.hh:107
gem5::o3::IEW::IEWStats::predictedNotTakenIncorrect
statistics::Scalar predictedNotTakenIncorrect
Stat for total number of incorrect predicted not taken branches.
Definition: iew.hh:449
gem5::o3::FUPool::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: fu_pool.hh:182
gem5::o3::IEW::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: iew.cc:392
gem5::o3::IEW::checkMisprediction
void checkMisprediction(const DynInstPtr &inst)
Check misprediction
Definition: iew.cc:1593
gem5::o3::IEW::fromRename
TimeBuffer< RenameStruct >::wire fromRename
Wire to get rename's output from rename queue.
Definition: iew.hh:315
gem5::o3::IEW::iewStats
gem5::o3::IEW::IEWStats iewStats
gem5::o3::InstructionQueue::commit
void commit(const InstSeqNum &inst, ThreadID tid=0)
Commits all instructions up to and including the given sequence number, for a specific thread.
Definition: inst_queue.cc:945
gem5::o3::IEW::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: iew.cc:293
gem5::o3::IEW::wakeDependents
void wakeDependents(const DynInstPtr &inst)
Wakes all dependents of a completed instruction.
Definition: iew.cc:539
gem5::o3::IEW::commitToIEWDelay
Cycles commitToIEWDelay
Commit to IEW delay.
Definition: iew.hh:377
gem5::o3::IEW::IEWStats::iqFullEvents
statistics::Scalar iqFullEvents
Stat for number of times the IQ becomes full.
Definition: iew.hh:441
gem5::o3::IEW::issueToExecQueue
TimeBuffer< IssueStruct > issueToExecQueue
Issue stage queue.
Definition: iew.hh:318
gem5::o3::IEW::IEWStats::wbFanout
statistics::Formula wbFanout
Average number of woken instructions per writeback.
Definition: iew.hh:490
gem5::o3::Scoreboard
Implements a simple scoreboard to track which registers are ready.
Definition: scoreboard.hh:53
gem5::o3::IEW::skidInsert
void skidInsert(ThreadID tid)
Inserts unused instructions of a thread into the skid buffer.
Definition: iew.cc:597
gem5::o3::IEW::writebackInsts
void writebackInsts()
Writebacks instructions.
Definition: iew.cc:1383
gem5::o3::InstructionQueue::IQIOStats::intInstQueueReads
statistics::Scalar intInstQueueReads
Definition: inst_queue.hh:549
gem5::o3::IEW::emptyRenameInsts
void emptyRenameInsts(ThreadID tid)
Removes instructions from rename from a thread's instruction list.
Definition: iew.cc:784
gem5::o3::IEW::activeThreads
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Definition: iew.hh:412
dyn_inst.hh
gem5::o3::IEW::exeStatus
StageStatus exeStatus
Execute status.
Definition: iew.hh:116
gem5::o3::IEW::toCommit
TimeBuffer< IEWStruct >::wire toCommit
Wire to write infromation heading to commit.
Definition: iew.hh:330
gem5::o3::IEW::dispatchInsts
void dispatchInsts(ThreadID tid)
Dispatches instructions to IQ and LSQ.
Definition: iew.cc:879
gem5::o3::IEW::sortInsts
void sortInsts()
Sorts instructions coming from rename into lists separated by thread.
Definition: iew.cc:771
gem5::o3::IEW::checkStall
bool checkStall(ThreadID tid)
Checks if any of the stall conditions are currently true.
Definition: iew.cc:692
gem5::o3::InstructionQueue::recordProducer
void recordProducer(const DynInstPtr &inst)
Records the instruction as the producer of a register without adding it to the rest of the IQ.
Definition: inst_queue.hh:214
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
iew.hh
gem5::o3::InstructionQueue::cacheUnblocked
void cacheUnblocked()
Notify instruction queue that a previous blockage has resolved.
Definition: inst_queue.cc:1121
gem5::o3::InstructionQueue::takeOverFrom
void takeOverFrom()
Takes over execution from another CPU's thread.
Definition: inst_queue.cc:470
gem5::o3::IEW::toRename
TimeBuffer< TimeStruct >::wire toRename
Wire to write information heading to previous stages.
Definition: iew.hh:309
gem5::o3::IEW::squash
void squash(ThreadID tid)
Squashes instructions in IEW for a specific thread.
Definition: iew.cc:419
gem5::o3::IEW::IEWStats::ExecutedInstStats::numSquashedInsts
statistics::Scalar numSquashedInsts
Stat for total number of squashed instructions skipped at execute.
Definition: iew.hh:464
gem5::o3::IEW::IEWStats::writebackCount
statistics::Vector writebackCount
Number of instructions that writeback.
Definition: iew.hh:482
gem5::o3::InstructionQueue::setIssueToExecuteQueue
void setIssueToExecuteQueue(TimeBuffer< IssueStruct > *i2eQueue)
Sets the timer buffer between issue and execute.
Definition: inst_queue.cc:435
gem5::o3::IEW::Inactive
@ Inactive
Definition: iew.hh:96
gem5::o3::LSQ::executeStore
Fault executeStore(const DynInstPtr &inst)
Executes a store.
Definition: lsq.cc:253
gem5::o3::IEW::wakeCPU
void wakeCPU()
Tells the CPU to wakeup if it has descheduled itself due to no activity.
Definition: iew.cc:805
gem5::o3::IEW::Blocked
@ Blocked
Definition: iew.hh:103
gem5::o3::IEW::startupStage
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
Definition: iew.cc:270
gem5::RefCountingPtr< DynInst >
gem5::o3::IEW::rescheduleMemInst
void rescheduleMemInst(const DynInstPtr &inst)
Tells memory dependence unit that a memory instruction needs to be rescheduled.
Definition: iew.cc:545
gem5::TimeBuffer
Definition: timebuf.hh:40
gem5::o3::LSQ::sqFull
bool sqFull()
Returns if any of the SQs are full.
Definition: lsq.cc:653
gem5::o3::IEW::Squashing
@ Squashing
Definition: iew.hh:106
gem5::o3::CPU::checker
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
Definition: cpu.hh:602
gem5::o3::LSQ::violation
bool violation()
Returns whether or not there was a memory ordering violation.
Definition: lsq.cc:297
gem5::o3::InstructionQueue::wakeDependents
int wakeDependents(const DynInstPtr &completed_inst)
Wakes all dependents of a completed instruction.
Definition: inst_queue.cc:962
gem5::o3::CPU::deactivateStage
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
Definition: cpu.hh:576
gem5::o3::IEW::wroteToTimeBuffer
bool wroteToTimeBuffer
Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if th...
Definition: iew.hh:348
gem5::o3::InstructionQueue::iqIOStats
gem5::o3::InstructionQueue::IQIOStats iqIOStats
gem5::o3::IEW::fromCommit
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's output from backwards time buffer.
Definition: iew.hh:306
timebuf.hh
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
gem5::o3::IEW::IEWStats::ExecutedInstStats::numLoadInsts
statistics::Vector numLoadInsts
Stat for total number of executed load instructions.
Definition: iew.hh:461
gem5::o3::IEW::instQueue
InstructionQueue instQueue
Instruction queue.
Definition: iew.hh:355
gem5::o3::LSQ::numHtmStarts
int numHtmStarts(ThreadID tid) const
Definition: lsq.cc:352
gem5::o3::IEW::IEWStats::consumerInst
statistics::Vector consumerInst
Number of instructions that wake up from producers.
Definition: iew.hh:486
gem5::o3::IEW::block
void block(ThreadID tid)
Sets Dispatch to blocked, and signals back to other stages to block.
Definition: iew.cc:505
gem5::o3::IEW::IEWStats::dispSquashedInsts
statistics::Scalar dispSquashedInsts
Stat for total number of squashed instructions dispatch skips.
Definition: iew.hh:433
gem5::BaseCPU::baseStats
gem5::BaseCPU::BaseCPUStats baseStats
gem5::o3::IEW::_status
Status _status
Overall stage status.
Definition: iew.hh:112
gem5::o3::CPU::IEWIdx
@ IEWIdx
Definition: cpu.hh:540
gem5::o3::FUPool::isDrained
bool isDrained() const
Have all the FUs drained?
Definition: fu_pool.cc:244
gem5::o3::LSQ::tick
void tick()
Ticks the LSQ.
Definition: lsq.cc:183
gem5::o3::IEW::IEWStats::instsToCommit
statistics::Vector instsToCommit
Number of instructions sent to commit.
Definition: iew.hh:480
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::IEW::isDrained
bool isDrained() const
Has the stage drained?
Definition: iew.cc:355
gem5::o3::InstructionQueue::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the global time buffer.
Definition: inst_queue.cc:441
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::LSQ::isDrained
bool isDrained() const
Has the LSQ drained?
Definition: lsq.cc:154
gem5::o3::IEW::squashDueToBranch
void squashDueToBranch(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a branch mispredict.
Definition: iew.cc:454
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::o3::Scoreboard::setReg
void setReg(PhysRegIdPtr phys_reg)
Sets the register as ready.
Definition: scoreboard.hh:105
gem5::o3::IEW::IEW
IEW(CPU *_cpu, const O3CPUParams &params)
Constructs a IEW with the given parameters.
Definition: iew.cc:68
gem5::BaseCPU::BaseCPUStats::numCycles
statistics::Scalar numCycles
Definition: base.hh:597
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::o3::InstructionQueue::deferMemInst
void deferMemInst(const DynInstPtr &deferred_inst)
Defers a memory instruction when its DTB translation incurs a hw page table walk.
Definition: inst_queue.cc:1104
cpu.hh
gem5::o3::IEW::skidBuffer
std::queue< DynInstPtr > skidBuffer[MaxThreads]
Skid buffer between rename and IEW.
Definition: iew.hh:336
gem5::o3::IEW::fuPool
FUPool * fuPool
Pointer to the functional unit pool.
Definition: iew.hh:361
gem5::o3::CPU::activateStage
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
Definition: cpu.hh:572
gem5::o3::LSQ::getLatestHtmUid
uint64_t getLatestHtmUid(ThreadID tid) const
Definition: lsq.cc:376
gem5::o3::LSQ::willWB
bool willWB()
Returns if the LSQ will write back to memory this cycle.
Definition: lsq.cc:733
gem5::o3::LSQ::numFreeLoadEntries
unsigned numFreeLoadEntries()
Returns the number of free load entries.
Definition: lsq.cc:515
gem5::o3::InstructionQueue::numFreeEntries
unsigned numFreeEntries()
Returns total number of free entries.
Definition: inst_queue.cc:509
gem5::o3::IEW::IEWStats::ExecutedInstStats::numInsts
statistics::Scalar numInsts
Stat for total number of executed instructions.
Definition: iew.hh:459
gem5::o3::IEW::wbStatus
StageStatus wbStatus
Writeback status.
Definition: iew.hh:118
gem5::o3::IEW::activityThisCycle
void activityThisCycle()
Reports to the CPU that there is activity this cycle.
Definition: iew.cc:811
gem5::o3::CPU::wakeCPU
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
Definition: cpu.cc:1594
gem5::o3::IEW::renameToIEWDelay
Cycles renameToIEWDelay
Rename to IEW delay.
Definition: iew.hh:380
gem5::o3::IEW::iewQueue
TimeBuffer< IEWStruct > * iewQueue
IEW stage time buffer.
Definition: iew.hh:327
gem5::o3::FUPool::processFreeUnits
void processFreeUnits()
Frees all FUs on the list.
Definition: fu_pool.cc:197
gem5::o3::MaxWidth
static constexpr int MaxWidth
Definition: limits.hh:37
fu_pool.hh
gem5::o3::IEW::dispatchWidth
unsigned dispatchWidth
Width of dispatch, in instructions.
Definition: iew.hh:390
gem5::o3::IEW::Running
@ Running
Definition: iew.hh:102
gem5::o3::InstructionQueue::scheduleNonSpec
void scheduleNonSpec(const InstSeqNum &inst)
Schedules a single specific non-speculative instruction.
Definition: inst_queue.cc:918
gem5::o3::IEW::IEWStats::memOrderViolationEvents
statistics::Scalar memOrderViolationEvents
Stat for total number of memory ordering violation events.
Definition: iew.hh:445
gem5::o3::IEW::tick
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle.
Definition: iew.cc:1433
gem5::o3::IEW::IEWStats::dispatchedInsts
statistics::Scalar dispatchedInsts
Stat for total number of instructions dispatched.
Definition: iew.hh:431
gem5::o3::IEW::printAvailableInsts
void printAvailableInsts()
Debug function to print instructions that are issued this cycle.
Definition: iew.cc:1115
gem5::o3::IEW::IEWStats::ExecutedInstStats::ExecutedInstStats
ExecutedInstStats(CPU *cpu)
Definition: iew.cc:219
gem5::o3::IEW::IEWStats::ExecutedInstStats::numNop
statistics::Vector numNop
Number of executed nops.
Definition: iew.hh:468
gem5::o3::IEW::cpu
CPU * cpu
CPU pointer.
Definition: iew.hh:343
gem5::o3::LSQ::getMemDepViolator
DynInstPtr getMemDepViolator(ThreadID tid)
Gets the instruction that caused the memory ordering violation.
Definition: lsq.cc:316
gem5::o3::InstructionQueue::getInstToExecute
DynInstPtr getInstToExecute()
Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to exe...
Definition: inst_queue.cc:658
gem5::o3::IEW::wbWidth
unsigned wbWidth
Writeback width.
Definition: iew.hh:406
gem5::o3::LSQ::squash
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squash instructions from a thread until the specified sequence number.
Definition: lsq.cc:291
gem5::o3::IEW::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
Pointer to main time buffer used for backwards communication.
Definition: iew.hh:300
gem5::o3::LSQ::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: lsq.cc:145
gem5::o3::IEW::IEWStats::predictedTakenIncorrect
statistics::Scalar predictedTakenIncorrect
Stat for total number of incorrect predicted taken branches.
Definition: iew.hh:447
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::o3::IEW::fetchRedirect
bool fetchRedirect[MaxThreads]
Records if there is a fetch redirect on this cycle for each thread.
Definition: iew.hh:369
gem5::o3::IEW::IEWStats::squashCycles
statistics::Scalar squashCycles
Stat for total number of squashing cycles.
Definition: iew.hh:425
gem5::o3::InstructionQueue::insertBarrier
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly.
Definition: inst_queue.cc:650
gem5::o3::IEW::IEWStats::dispLoadInsts
statistics::Scalar dispLoadInsts
Stat for total number of dispatched load instructions.
Definition: iew.hh:435
gem5::SimObject::getProbeManager
ProbeManager * getProbeManager()
Get the probe manager for this object.
Definition: sim_object.cc:120
gem5::o3::IEW::fromIssue
TimeBuffer< IssueStruct >::wire fromIssue
Wire to read information from the issue stage time queue.
Definition: iew.hh:321
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::CPU::activityThisCycle
void activityThisCycle()
Records that there was time buffer activity this cycle.
Definition: cpu.hh:569
gem5::o3::IEW::unblock
void unblock(ThreadID tid)
Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock.
Definition: iew.cc:523
gem5::o3::InstructionQueue::squash
void squash(ThreadID tid)
Squashes instructions for a thread.
Definition: inst_queue.cc:1165
gem5::o3::IEW::issueWidth
unsigned issueWidth
Width of issue, in instructions.
Definition: iew.hh:393
gem5::o3::LSQ::insertLoad
void insertLoad(const DynInstPtr &load_inst)
Inserts a load into the LSQ.
Definition: lsq.cc:229
gem5::o3::IEW::instToCommit
void instToCommit(const DynInstPtr &inst)
Sends an instruction to commit through the time buffer.
Definition: iew.cc:569
gem5::o3::IEW::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: iew.cc:383
gem5::o3::IEW::ppExecute
ProbePointArg< DynInstPtr > * ppExecute
To probe when instruction execution begins.
Definition: iew.hh:124
gem5::o3::IEW::IEWStats::dispNonSpecInsts
statistics::Scalar dispNonSpecInsts
Stat for total number of dispatched non speculative insts.
Definition: iew.hh:439
gem5::o3::IEW::blockMemInst
void blockMemInst(const DynInstPtr &inst)
Moves memory instruction onto the list of cache blocked instructions.
Definition: iew.cc:557
gem5::o3::IEW::wbCycle
unsigned wbCycle
Cycle number within the queue of instructions being written back.
Definition: iew.hh:403
gem5::o3::IEW::cacheUnblocked
void cacheUnblocked()
Notifies that the cache has become unblocked.
Definition: iew.cc:563
gem5::o3::InstructionQueue::isDrained
bool isDrained() const
Determine if we are drained.
Definition: inst_queue.cc:449
gem5::o3::IEW::IEWStats::lsqFullEvents
statistics::Scalar lsqFullEvents
Stat for number of times the LSQ becomes full.
Definition: iew.hh:443
gem5::o3::InstructionQueue::insertNonSpec
void insertNonSpec(const DynInstPtr &new_inst)
Inserts a new, non-speculative instruction into the IQ.
Definition: inst_queue.cc:604
gem5::o3::InstructionQueue::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets active threads list.
Definition: inst_queue.cc:429
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::o3::InstructionQueue::blockMemInst
void blockMemInst(const DynInstPtr &blocked_inst)
Defers a memory instruction when it is cache blocked.
Definition: inst_queue.cc:1110
gem5::o3::LSQ::numFreeStoreEntries
unsigned numFreeStoreEntries()
Returns the number of free store entries.
Definition: lsq.cc:532
gem5::o3::IEW::wbNumInst
unsigned wbNumInst
Index into queue of instructions being written back.
Definition: iew.hh:396
gem5::o3::IEW::skidBufferMax
unsigned skidBufferMax
Maximum size of the skid buffer.
Definition: iew.hh:415
gem5::o3::IEW::deactivateStage
void deactivateStage()
Tells CPU that the IEW stage is inactive and idle.
Definition: iew.cc:825
gem5::o3::IEW::scoreboard
Scoreboard * scoreboard
Scoreboard pointer.
Definition: iew.hh:339
gem5::o3::IEW::ppDispatch
ProbePointArg< DynInstPtr > * ppDispatch
Definition: iew.hh:122
gem5::o3::IEW::setRenameQueue
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets time buffer for getting instructions coming from rename.
Definition: iew.cc:322
gem5::o3::InstructionQueue::insert
void insert(const DynInstPtr &new_inst)
Inserts a new instruction into the IQ.
Definition: inst_queue.cc:559
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::IEW::updateLSQNextCycle
bool updateLSQNextCycle
Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity...
Definition: iew.hh:365
gem5::o3::InstructionQueue::replayMemInst
void replayMemInst(const DynInstPtr &replay_inst)
Replays a memory instruction.
Definition: inst_queue.cc:1098
gem5::o3::IEW::numThreads
ThreadID numThreads
Number of active threads.
Definition: iew.hh:409
gem5::o3::IEW::IEWStats::ExecutedInstStats::numSwp
statistics::Vector numSwp
Number of executed software prefetches.
Definition: iew.hh:466
gem5::o3::IEW::IEWStats::IEWStats
IEWStats(CPU *cpu)
Definition: iew.cc:145
gem5::o3::IEW::squashDueToMemOrder
void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a memory order violation.
Definition: iew.cc:479
gem5::o3::LSQ::getDataPort
RequestPort & getDataPort()
Definition: lsq.hh:1010
gem5::o3::LSQ::takeOverFrom
void takeOverFrom()
Takes over execution from another CPU's thread.
Definition: lsq.cc:172
gem5::o3::LSQ::commitStores
void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
Commits stores up until the given sequence number for a specific thread.
Definition: lsq.cc:267
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:355
gem5::o3::InstructionQueue::scheduleReadyInsts
void scheduleReadyInsts()
Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute.
Definition: inst_queue.cc:748
gem5::o3::IEW::ldstQueue
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:358
std::list< ThreadID >
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::o3::IEW::setIEWQueue
void setIEWQueue(TimeBuffer< IEWStruct > *iq_ptr)
Sets time buffer to pass on instructions to commit.
Definition: iew.cc:331
limits.hh
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1037
gem5::o3::LSQ::lqFull
bool lqFull()
Returns if any of the LQs are full.
Definition: lsq.cc:626
gem5::o3::IEW::dispatch
void dispatch(ThreadID tid)
Determines proper actions to take given Dispatch's status.
Definition: iew.cc:832
gem5::o3::LSQ::numHtmStops
int numHtmStops(ThreadID tid) const
Definition: lsq.cc:360
gem5::o3::IEW::updatedQueues
bool updatedQueues
Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast th...
Definition: iew.hh:374
gem5::o3::IEW::issueToExecuteDelay
Cycles issueToExecuteDelay
Issue to execute delay.
Definition: iew.hh:387
gem5::o3::IEW::Idle
@ Idle
Definition: iew.hh:104
gem5::o3::LSQ::executeLoad
Fault executeLoad(const DynInstPtr &inst)
Executes a load.
Definition: lsq.cc:245
gem5::o3::IEW::IEWStats::ExecutedInstStats::numBranches
statistics::Vector numBranches
Number of executed branches.
Definition: iew.hh:472
gem5::o3::IEW::activateStage
void activateStage()
Tells CPU that the IEW stage is active and running.
Definition: iew.cc:818
gem5::o3::IEW::IEWStats::ExecutedInstStats::numRate
statistics::Formula numRate
Number of instructions executed per cycle.
Definition: iew.hh:476
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::IEW::name
std::string name() const
Returns the name of the IEW stage.
Definition: iew.cc:119
gem5::o3::InstructionQueue::violation
void violation(const DynInstPtr &store, const DynInstPtr &faulting_load)
Indicates an ordering violation between a store and a load.
Definition: inst_queue.cc:1157
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::o3::IEW::setScoreboard
void setScoreboard(Scoreboard *sb_ptr)
Sets pointer to the scoreboard.
Definition: iew.cc:349
gem5::o3::IEW::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition: iew.cc:340
gem5::o3::InstructionQueue::hasReadyInsts
bool hasReadyInsts()
Returns if there are any ready instructions in the IQ.
Definition: inst_queue.cc:543
gem5::o3::IEW::executeInsts
void executeInsts()
Executes instructions.
Definition: iew.cc:1137
gem5::o3::IEW::regProbePoints
void regProbePoints()
Registers probes.
Definition: iew.cc:125
gem5::o3::InstructionQueue::getCount
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
Definition: inst_queue.hh:274

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