gem5  v22.0.0.2
iew.cc
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41 
42 // @todo: Fix the instantaneous communication among all the stages within
43 // iew. There's a clear delay between issue and execute, yet backwards
44 // communication happens simultaneously.
45 
46 #include "cpu/o3/iew.hh"
47 
48 #include <queue>
49 
50 #include "config/the_isa.hh"
51 #include "cpu/checker/cpu.hh"
52 #include "cpu/o3/dyn_inst.hh"
53 #include "cpu/o3/fu_pool.hh"
54 #include "cpu/o3/limits.hh"
55 #include "cpu/timebuf.hh"
56 #include "debug/Activity.hh"
57 #include "debug/Drain.hh"
58 #include "debug/IEW.hh"
59 #include "debug/O3PipeView.hh"
60 #include "params/BaseO3CPU.hh"
61 
62 namespace gem5
63 {
64 
65 namespace o3
66 {
67 
68 IEW::IEW(CPU *_cpu, const BaseO3CPUParams &params)
69  : issueToExecQueue(params.backComSize, params.forwardComSize),
70  cpu(_cpu),
71  instQueue(_cpu, this, params),
72  ldstQueue(_cpu, this, params),
73  fuPool(params.fuPool),
74  commitToIEWDelay(params.commitToIEWDelay),
75  renameToIEWDelay(params.renameToIEWDelay),
76  issueToExecuteDelay(params.issueToExecuteDelay),
77  dispatchWidth(params.dispatchWidth),
78  issueWidth(params.issueWidth),
79  wbNumInst(0),
80  wbCycle(0),
81  wbWidth(params.wbWidth),
82  numThreads(params.numThreads),
83  iewStats(cpu)
84 {
85  if (dispatchWidth > MaxWidth)
86  fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n"
87  "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
88  dispatchWidth, static_cast<int>(MaxWidth));
89  if (issueWidth > MaxWidth)
90  fatal("issueWidth (%d) is larger than compiled limit (%d),\n"
91  "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
92  issueWidth, static_cast<int>(MaxWidth));
93  if (wbWidth > MaxWidth)
94  fatal("wbWidth (%d) is larger than compiled limit (%d),\n"
95  "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
96  wbWidth, static_cast<int>(MaxWidth));
97 
98  _status = Active;
100  wbStatus = Idle;
101 
102  // Setup wire to read instructions coming from issue.
104 
105  // Instruction queue needs the queue between issue and execute.
107 
108  for (ThreadID tid = 0; tid < MaxThreads; tid++) {
109  dispatchStatus[tid] = Running;
110  fetchRedirect[tid] = false;
111  }
112 
113  updateLSQNextCycle = false;
114 
115  skidBufferMax = (renameToIEWDelay + 1) * params.renameWidth;
116 }
117 
118 std::string
119 IEW::name() const
120 {
121  return cpu->name() + ".iew";
122 }
123 
124 void
126 {
128  cpu->getProbeManager(), "Dispatch");
130  cpu->getProbeManager(), "Mispredict");
136  cpu->getProbeManager(), "Execute");
142  cpu->getProbeManager(), "ToCommit");
143 }
144 
146  : statistics::Group(cpu, "iew"),
147  ADD_STAT(idleCycles, statistics::units::Cycle::get(),
148  "Number of cycles IEW is idle"),
149  ADD_STAT(squashCycles, statistics::units::Cycle::get(),
150  "Number of cycles IEW is squashing"),
151  ADD_STAT(blockCycles, statistics::units::Cycle::get(),
152  "Number of cycles IEW is blocking"),
153  ADD_STAT(unblockCycles, statistics::units::Cycle::get(),
154  "Number of cycles IEW is unblocking"),
155  ADD_STAT(dispatchedInsts, statistics::units::Count::get(),
156  "Number of instructions dispatched to IQ"),
157  ADD_STAT(dispSquashedInsts, statistics::units::Count::get(),
158  "Number of squashed instructions skipped by dispatch"),
159  ADD_STAT(dispLoadInsts, statistics::units::Count::get(),
160  "Number of dispatched load instructions"),
161  ADD_STAT(dispStoreInsts, statistics::units::Count::get(),
162  "Number of dispatched store instructions"),
163  ADD_STAT(dispNonSpecInsts, statistics::units::Count::get(),
164  "Number of dispatched non-speculative instructions"),
165  ADD_STAT(iqFullEvents, statistics::units::Count::get(),
166  "Number of times the IQ has become full, causing a stall"),
167  ADD_STAT(lsqFullEvents, statistics::units::Count::get(),
168  "Number of times the LSQ has become full, causing a stall"),
169  ADD_STAT(memOrderViolationEvents, statistics::units::Count::get(),
170  "Number of memory order violations"),
171  ADD_STAT(predictedTakenIncorrect, statistics::units::Count::get(),
172  "Number of branches that were predicted taken incorrectly"),
173  ADD_STAT(predictedNotTakenIncorrect, statistics::units::Count::get(),
174  "Number of branches that were predicted not taken incorrectly"),
175  ADD_STAT(branchMispredicts, statistics::units::Count::get(),
176  "Number of branch mispredicts detected at execute",
177  predictedTakenIncorrect + predictedNotTakenIncorrect),
178  executedInstStats(cpu),
179  ADD_STAT(instsToCommit, statistics::units::Count::get(),
180  "Cumulative count of insts sent to commit"),
181  ADD_STAT(writebackCount, statistics::units::Count::get(),
182  "Cumulative count of insts written-back"),
183  ADD_STAT(producerInst, statistics::units::Count::get(),
184  "Number of instructions producing a value"),
185  ADD_STAT(consumerInst, statistics::units::Count::get(),
186  "Number of instructions consuming a value"),
187  ADD_STAT(wbRate, statistics::units::Rate<
188  statistics::units::Count, statistics::units::Cycle>::get(),
189  "Insts written-back per cycle"),
190  ADD_STAT(wbFanout, statistics::units::Rate<
191  statistics::units::Count, statistics::units::Count>::get(),
192  "Average fanout of values written-back")
193 {
195  .init(cpu->numThreads)
197 
199  .init(cpu->numThreads)
201 
203  .init(cpu->numThreads)
205 
207  .init(cpu->numThreads)
209 
210  wbRate
212  wbRate = writebackCount / cpu->baseStats.numCycles;
213 
214  wbFanout
217 }
218 
220  : statistics::Group(cpu),
221  ADD_STAT(numInsts, statistics::units::Count::get(),
222  "Number of executed instructions"),
223  ADD_STAT(numLoadInsts, statistics::units::Count::get(),
224  "Number of load instructions executed"),
225  ADD_STAT(numSquashedInsts, statistics::units::Count::get(),
226  "Number of squashed instructions skipped in execute"),
227  ADD_STAT(numSwp, statistics::units::Count::get(),
228  "Number of swp insts executed"),
229  ADD_STAT(numNop, statistics::units::Count::get(),
230  "Number of nop insts executed"),
231  ADD_STAT(numRefs, statistics::units::Count::get(),
232  "Number of memory reference insts executed"),
233  ADD_STAT(numBranches, statistics::units::Count::get(),
234  "Number of branches executed"),
235  ADD_STAT(numStoreInsts, statistics::units::Count::get(),
236  "Number of stores executed"),
237  ADD_STAT(numRate, statistics::units::Rate<
238  statistics::units::Count, statistics::units::Cycle>::get(),
239  "Inst execution rate", numInsts / cpu->baseStats.numCycles)
240 {
242  .init(cpu->numThreads)
244 
245  numSwp
246  .init(cpu->numThreads)
248 
249  numNop
250  .init(cpu->numThreads)
252 
253  numRefs
254  .init(cpu->numThreads)
256 
258  .init(cpu->numThreads)
260 
264 
265  numRate
267 }
268 
269 void
271 {
272  for (ThreadID tid = 0; tid < numThreads; tid++) {
273  toRename->iewInfo[tid].usedIQ = true;
274  toRename->iewInfo[tid].freeIQEntries =
276 
277  toRename->iewInfo[tid].usedLSQ = true;
278  toRename->iewInfo[tid].freeLQEntries =
280  toRename->iewInfo[tid].freeSQEntries =
282  }
283 
284  // Initialize the checker's dcache port here
285  if (cpu->checker) {
286  cpu->checker->setDcachePort(&ldstQueue.getDataPort());
287  }
288 
290 }
291 
292 void
294 {
295  toRename->iewInfo[tid].usedIQ = true;
296  toRename->iewInfo[tid].freeIQEntries =
298 
299  toRename->iewInfo[tid].usedLSQ = true;
300  toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
301  toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
302 }
303 
304 void
306 {
307  timeBuffer = tb_ptr;
308 
309  // Setup wire to read information from time buffer, from commit.
311 
312  // Setup wire to write information back to previous stages.
313  toRename = timeBuffer->getWire(0);
314 
315  toFetch = timeBuffer->getWire(0);
316 
317  // Instruction queue also needs main time buffer.
318  instQueue.setTimeBuffer(tb_ptr);
319 }
320 
321 void
323 {
324  renameQueue = rq_ptr;
325 
326  // Setup wire to read information from rename queue.
328 }
329 
330 void
332 {
333  iewQueue = iq_ptr;
334 
335  // Setup wire to write instructions to commit.
336  toCommit = iewQueue->getWire(0);
337 }
338 
339 void
341 {
342  activeThreads = at_ptr;
343 
344  ldstQueue.setActiveThreads(at_ptr);
345  instQueue.setActiveThreads(at_ptr);
346 }
347 
348 void
350 {
351  scoreboard = sb_ptr;
352 }
353 
354 bool
356 {
357  bool drained = ldstQueue.isDrained() && instQueue.isDrained();
358 
359  for (ThreadID tid = 0; tid < numThreads; tid++) {
360  if (!insts[tid].empty()) {
361  DPRINTF(Drain, "%i: Insts not empty.\n", tid);
362  drained = false;
363  }
364  if (!skidBuffer[tid].empty()) {
365  DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
366  drained = false;
367  }
368  drained = drained && dispatchStatus[tid] == Running;
369  }
370 
371  // Also check the FU pool as instructions are "stored" in FU
372  // completion events until they are done and not accounted for
373  // above
374  if (drained && !fuPool->isDrained()) {
375  DPRINTF(Drain, "FU pool still busy.\n");
376  drained = false;
377  }
378 
379  return drained;
380 }
381 
382 void
384 {
385  assert(isDrained());
386 
389 }
390 
391 void
393 {
394  // Reset all state.
395  _status = Active;
396  exeStatus = Running;
397  wbStatus = Idle;
398 
401  fuPool->takeOverFrom();
402 
403  startupStage();
405 
406  for (ThreadID tid = 0; tid < numThreads; tid++) {
407  dispatchStatus[tid] = Running;
408  fetchRedirect[tid] = false;
409  }
410 
411  updateLSQNextCycle = false;
412 
413  for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
414  issueToExecQueue.advance();
415  }
416 }
417 
418 void
420 {
421  DPRINTF(IEW, "[tid:%i] Squashing all instructions.\n", tid);
422 
423  // Tell the IQ to start squashing.
424  instQueue.squash(tid);
425 
426  // Tell the LDSTQ to start squashing.
427  ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
428  updatedQueues = true;
429 
430  // Clear the skid buffer in case it has any data in it.
431  DPRINTF(IEW,
432  "Removing skidbuffer instructions until "
433  "[sn:%llu] [tid:%i]\n",
434  fromCommit->commitInfo[tid].doneSeqNum, tid);
435 
436  while (!skidBuffer[tid].empty()) {
437  if (skidBuffer[tid].front()->isLoad()) {
438  toRename->iewInfo[tid].dispatchedToLQ++;
439  }
440  if (skidBuffer[tid].front()->isStore() ||
441  skidBuffer[tid].front()->isAtomic()) {
442  toRename->iewInfo[tid].dispatchedToSQ++;
443  }
444 
445  toRename->iewInfo[tid].dispatched++;
446 
447  skidBuffer[tid].pop();
448  }
449 
450  emptyRenameInsts(tid);
451 }
452 
453 void
455 {
456  DPRINTF(IEW, "[tid:%i] [sn:%llu] Squashing from a specific instruction,"
457  " PC: %s "
458  "\n", tid, inst->seqNum, inst->pcState() );
459 
460  if (!toCommit->squash[tid] ||
461  inst->seqNum < toCommit->squashedSeqNum[tid]) {
462  toCommit->squash[tid] = true;
463  toCommit->squashedSeqNum[tid] = inst->seqNum;
464  toCommit->branchTaken[tid] = inst->pcState().branching();
465 
466  set(toCommit->pc[tid], inst->pcState());
467  inst->staticInst->advancePC(*toCommit->pc[tid]);
468 
469  toCommit->mispredictInst[tid] = inst;
470  toCommit->includeSquashInst[tid] = false;
471 
472  wroteToTimeBuffer = true;
473  }
474 
475 }
476 
477 void
479 {
480  DPRINTF(IEW, "[tid:%i] Memory violation, squashing violator and younger "
481  "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum);
482  // Need to include inst->seqNum in the following comparison to cover the
483  // corner case when a branch misprediction and a memory violation for the
484  // same instruction (e.g. load PC) are detected in the same cycle. In this
485  // case the memory violator should take precedence over the branch
486  // misprediction because it requires the violator itself to be included in
487  // the squash.
488  if (!toCommit->squash[tid] ||
489  inst->seqNum <= toCommit->squashedSeqNum[tid]) {
490  toCommit->squash[tid] = true;
491 
492  toCommit->squashedSeqNum[tid] = inst->seqNum;
493  set(toCommit->pc[tid], inst->pcState());
494  toCommit->mispredictInst[tid] = NULL;
495 
496  // Must include the memory violator in the squash.
497  toCommit->includeSquashInst[tid] = true;
498 
499  wroteToTimeBuffer = true;
500  }
501 }
502 
503 void
505 {
506  DPRINTF(IEW, "[tid:%i] Blocking.\n", tid);
507 
508  if (dispatchStatus[tid] != Blocked &&
509  dispatchStatus[tid] != Unblocking) {
510  toRename->iewBlock[tid] = true;
511  wroteToTimeBuffer = true;
512  }
513 
514  // Add the current inputs to the skid buffer so they can be
515  // reprocessed when this stage unblocks.
516  skidInsert(tid);
517 
518  dispatchStatus[tid] = Blocked;
519 }
520 
521 void
523 {
524  DPRINTF(IEW, "[tid:%i] Reading instructions out of the skid "
525  "buffer %u.\n",tid, tid);
526 
527  // If the skid bufffer is empty, signal back to previous stages to unblock.
528  // Also switch status to running.
529  if (skidBuffer[tid].empty()) {
530  toRename->iewUnblock[tid] = true;
531  wroteToTimeBuffer = true;
532  DPRINTF(IEW, "[tid:%i] Done unblocking.\n",tid);
533  dispatchStatus[tid] = Running;
534  }
535 }
536 
537 void
539 {
541 }
542 
543 void
545 {
547 }
548 
549 void
551 {
552  instQueue.replayMemInst(inst);
553 }
554 
555 void
557 {
558  instQueue.blockMemInst(inst);
559 }
560 
561 void
563 {
565 }
566 
567 void
569 {
570  // This function should not be called after writebackInsts in a
571  // single cycle. That will cause problems with an instruction
572  // being added to the queue to commit without being processed by
573  // writebackInsts prior to being sent to commit.
574 
575  // First check the time slot that this instruction will write
576  // to. If there are free write ports at the time, then go ahead
577  // and write the instruction to that time. If there are not,
578  // keep looking back to see where's the first time there's a
579  // free slot.
580  while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
581  ++wbNumInst;
582  if (wbNumInst == wbWidth) {
583  ++wbCycle;
584  wbNumInst = 0;
585  }
586  }
587 
588  DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
590  // Add finished instruction to queue to commit.
591  (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
592  (*iewQueue)[wbCycle].size++;
593 }
594 
595 void
597 {
598  DynInstPtr inst = NULL;
599 
600  while (!insts[tid].empty()) {
601  inst = insts[tid].front();
602 
603  insts[tid].pop();
604 
605  DPRINTF(IEW,"[tid:%i] Inserting [sn:%lli] PC:%s into "
606  "dispatch skidBuffer %i\n",tid, inst->seqNum,
607  inst->pcState(),tid);
608 
609  skidBuffer[tid].push(inst);
610  }
611 
612  assert(skidBuffer[tid].size() <= skidBufferMax &&
613  "Skidbuffer Exceeded Max Size");
614 }
615 
616 int
618 {
619  int max=0;
620 
621  std::list<ThreadID>::iterator threads = activeThreads->begin();
623 
624  while (threads != end) {
625  ThreadID tid = *threads++;
626  unsigned thread_count = skidBuffer[tid].size();
627  if (max < thread_count)
628  max = thread_count;
629  }
630 
631  return max;
632 }
633 
634 bool
636 {
637  std::list<ThreadID>::iterator threads = activeThreads->begin();
639 
640  while (threads != end) {
641  ThreadID tid = *threads++;
642 
643  if (!skidBuffer[tid].empty())
644  return false;
645  }
646 
647  return true;
648 }
649 
650 void
652 {
653  bool any_unblocking = false;
654 
655  std::list<ThreadID>::iterator threads = activeThreads->begin();
657 
658  while (threads != end) {
659  ThreadID tid = *threads++;
660 
661  if (dispatchStatus[tid] == Unblocking) {
662  any_unblocking = true;
663  break;
664  }
665  }
666 
667  // If there are no ready instructions waiting to be scheduled by the IQ,
668  // and there's no stores waiting to write back, and dispatch is not
669  // unblocking, then there is no internal activity for the IEW stage.
671  if (_status == Active && !instQueue.hasReadyInsts() &&
672  !ldstQueue.willWB() && !any_unblocking) {
673  DPRINTF(IEW, "IEW switching to idle\n");
674 
675  deactivateStage();
676 
677  _status = Inactive;
678  } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
679  ldstQueue.willWB() ||
680  any_unblocking)) {
681  // Otherwise there is internal activity. Set to active.
682  DPRINTF(IEW, "IEW switching to active\n");
683 
684  activateStage();
685 
686  _status = Active;
687  }
688 }
689 
690 bool
692 {
693  bool ret_val(false);
694 
695  if (fromCommit->commitInfo[tid].robSquashing) {
696  DPRINTF(IEW,"[tid:%i] Stall from Commit stage detected.\n",tid);
697  ret_val = true;
698  } else if (instQueue.isFull(tid)) {
699  DPRINTF(IEW,"[tid:%i] Stall: IQ is full.\n",tid);
700  ret_val = true;
701  }
702 
703  return ret_val;
704 }
705 
706 void
708 {
709  // Check if there's a squash signal, squash if there is
710  // Check stall signals, block if there is.
711  // If status was Blocked
712  // if so then go to unblocking
713  // If status was Squashing
714  // check if squashing is not high. Switch to running this cycle.
715 
716  if (fromCommit->commitInfo[tid].squash) {
717  squash(tid);
718 
719  if (dispatchStatus[tid] == Blocked ||
720  dispatchStatus[tid] == Unblocking) {
721  toRename->iewUnblock[tid] = true;
722  wroteToTimeBuffer = true;
723  }
724 
725  dispatchStatus[tid] = Squashing;
726  fetchRedirect[tid] = false;
727  return;
728  }
729 
730  if (fromCommit->commitInfo[tid].robSquashing) {
731  DPRINTF(IEW, "[tid:%i] ROB is still squashing.\n", tid);
732 
733  dispatchStatus[tid] = Squashing;
734  emptyRenameInsts(tid);
735  wroteToTimeBuffer = true;
736  }
737 
738  if (checkStall(tid)) {
739  block(tid);
740  dispatchStatus[tid] = Blocked;
741  return;
742  }
743 
744  if (dispatchStatus[tid] == Blocked) {
745  // Status from previous cycle was blocked, but there are no more stall
746  // conditions. Switch over to unblocking.
747  DPRINTF(IEW, "[tid:%i] Done blocking, switching to unblocking.\n",
748  tid);
749 
750  dispatchStatus[tid] = Unblocking;
751 
752  unblock(tid);
753 
754  return;
755  }
756 
757  if (dispatchStatus[tid] == Squashing) {
758  // Switch status to running if rename isn't being told to block or
759  // squash this cycle.
760  DPRINTF(IEW, "[tid:%i] Done squashing, switching to running.\n",
761  tid);
762 
763  dispatchStatus[tid] = Running;
764 
765  return;
766  }
767 }
768 
769 void
771 {
772  int insts_from_rename = fromRename->size;
773 #ifdef DEBUG
774  for (ThreadID tid = 0; tid < numThreads; tid++)
775  assert(insts[tid].empty());
776 #endif
777  for (int i = 0; i < insts_from_rename; ++i) {
778  insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
779  }
780 }
781 
782 void
784 {
785  DPRINTF(IEW, "[tid:%i] Removing incoming rename instructions\n", tid);
786 
787  while (!insts[tid].empty()) {
788 
789  if (insts[tid].front()->isLoad()) {
790  toRename->iewInfo[tid].dispatchedToLQ++;
791  }
792  if (insts[tid].front()->isStore() ||
793  insts[tid].front()->isAtomic()) {
794  toRename->iewInfo[tid].dispatchedToSQ++;
795  }
796 
797  toRename->iewInfo[tid].dispatched++;
798 
799  insts[tid].pop();
800  }
801 }
802 
803 void
805 {
806  cpu->wakeCPU();
807 }
808 
809 void
811 {
812  DPRINTF(Activity, "Activity this cycle.\n");
814 }
815 
816 void
818 {
819  DPRINTF(Activity, "Activating stage.\n");
821 }
822 
823 void
825 {
826  DPRINTF(Activity, "Deactivating stage.\n");
828 }
829 
830 void
832 {
833  // If status is Running or idle,
834  // call dispatchInsts()
835  // If status is Unblocking,
836  // buffer any instructions coming from rename
837  // continue trying to empty skid buffer
838  // check if stall conditions have passed
839 
840  if (dispatchStatus[tid] == Blocked) {
842 
843  } else if (dispatchStatus[tid] == Squashing) {
845  }
846 
847  // Dispatch should try to dispatch as many instructions as its bandwidth
848  // will allow, as long as it is not currently blocked.
849  if (dispatchStatus[tid] == Running ||
850  dispatchStatus[tid] == Idle) {
851  DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
852  "dispatch.\n", tid);
853 
854  dispatchInsts(tid);
855  } else if (dispatchStatus[tid] == Unblocking) {
856  // Make sure that the skid buffer has something in it if the
857  // status is unblocking.
858  assert(!skidsEmpty());
859 
860  // If the status was unblocking, then instructions from the skid
861  // buffer were used. Remove those instructions and handle
862  // the rest of unblocking.
863  dispatchInsts(tid);
864 
866 
867  if (fromRename->size != 0) {
868  // Add the current inputs to the skid buffer so they can be
869  // reprocessed when this stage unblocks.
870  skidInsert(tid);
871  }
872 
873  unblock(tid);
874  }
875 }
876 
877 void
879 {
880  // Obtain instructions from skid buffer if unblocking, or queue from rename
881  // otherwise.
882  std::queue<DynInstPtr> &insts_to_dispatch =
883  dispatchStatus[tid] == Unblocking ?
884  skidBuffer[tid] : insts[tid];
885 
886  int insts_to_add = insts_to_dispatch.size();
887 
888  DynInstPtr inst;
889  bool add_to_iq = false;
890  int dis_num_inst = 0;
891 
892  // Loop through the instructions, putting them in the instruction
893  // queue.
894  for ( ; dis_num_inst < insts_to_add &&
895  dis_num_inst < dispatchWidth;
896  ++dis_num_inst)
897  {
898  inst = insts_to_dispatch.front();
899 
900  if (dispatchStatus[tid] == Unblocking) {
901  DPRINTF(IEW, "[tid:%i] Issue: Examining instruction from skid "
902  "buffer\n", tid);
903  }
904 
905  // Make sure there's a valid instruction there.
906  assert(inst);
907 
908  DPRINTF(IEW, "[tid:%i] Issue: Adding PC %s [sn:%lli] [tid:%i] to "
909  "IQ.\n",
910  tid, inst->pcState(), inst->seqNum, inst->threadNumber);
911 
912  // Be sure to mark these instructions as ready so that the
913  // commit stage can go ahead and execute them, and mark
914  // them as issued so the IQ doesn't reprocess them.
915 
916  // Check for squashed instructions.
917  if (inst->isSquashed()) {
918  DPRINTF(IEW, "[tid:%i] Issue: Squashed instruction encountered, "
919  "not adding to IQ.\n", tid);
920 
922 
923  insts_to_dispatch.pop();
924 
925  //Tell Rename That An Instruction has been processed
926  if (inst->isLoad()) {
927  toRename->iewInfo[tid].dispatchedToLQ++;
928  }
929  if (inst->isStore() || inst->isAtomic()) {
930  toRename->iewInfo[tid].dispatchedToSQ++;
931  }
932 
933  toRename->iewInfo[tid].dispatched++;
934 
935  continue;
936  }
937 
938  // Check for full conditions.
939  if (instQueue.isFull(tid)) {
940  DPRINTF(IEW, "[tid:%i] Issue: IQ has become full.\n", tid);
941 
942  // Call function to start blocking.
943  block(tid);
944 
945  // Set unblock to false. Special case where we are using
946  // skidbuffer (unblocking) instructions but then we still
947  // get full in the IQ.
948  toRename->iewUnblock[tid] = false;
949 
951  break;
952  }
953 
954  // Check LSQ if inst is LD/ST
955  if ((inst->isAtomic() && ldstQueue.sqFull(tid)) ||
956  (inst->isLoad() && ldstQueue.lqFull(tid)) ||
957  (inst->isStore() && ldstQueue.sqFull(tid))) {
958  DPRINTF(IEW, "[tid:%i] Issue: %s has become full.\n",tid,
959  inst->isLoad() ? "LQ" : "SQ");
960 
961  // Call function to start blocking.
962  block(tid);
963 
964  // Set unblock to false. Special case where we are using
965  // skidbuffer (unblocking) instructions but then we still
966  // get full in the IQ.
967  toRename->iewUnblock[tid] = false;
968 
970  break;
971  }
972 
973  // hardware transactional memory
974  // CPU needs to track transactional state in program order.
975  const int numHtmStarts = ldstQueue.numHtmStarts(tid);
976  const int numHtmStops = ldstQueue.numHtmStops(tid);
977  const int htmDepth = numHtmStarts - numHtmStops;
978 
979  if (htmDepth > 0) {
980  inst->setHtmTransactionalState(ldstQueue.getLatestHtmUid(tid),
981  htmDepth);
982  } else {
983  inst->clearHtmTransactionalState();
984  }
985 
986 
987  // Otherwise issue the instruction just fine.
988  if (inst->isAtomic()) {
989  DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
990  "encountered, adding to LSQ.\n", tid);
991 
992  ldstQueue.insertStore(inst);
993 
995 
996  // AMOs need to be set as "canCommit()"
997  // so that commit can process them when they reach the
998  // head of commit.
999  inst->setCanCommit();
1000  instQueue.insertNonSpec(inst);
1001  add_to_iq = false;
1002 
1004 
1005  toRename->iewInfo[tid].dispatchedToSQ++;
1006  } else if (inst->isLoad()) {
1007  DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
1008  "encountered, adding to LSQ.\n", tid);
1009 
1010  // Reserve a spot in the load store queue for this
1011  // memory access.
1012  ldstQueue.insertLoad(inst);
1013 
1015 
1016  add_to_iq = true;
1017 
1018  toRename->iewInfo[tid].dispatchedToLQ++;
1019  } else if (inst->isStore()) {
1020  DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
1021  "encountered, adding to LSQ.\n", tid);
1022 
1023  ldstQueue.insertStore(inst);
1024 
1026 
1027  if (inst->isStoreConditional()) {
1028  // Store conditionals need to be set as "canCommit()"
1029  // so that commit can process them when they reach the
1030  // head of commit.
1031  // @todo: This is somewhat specific to Alpha.
1032  inst->setCanCommit();
1033  instQueue.insertNonSpec(inst);
1034  add_to_iq = false;
1035 
1037  } else {
1038  add_to_iq = true;
1039  }
1040 
1041  toRename->iewInfo[tid].dispatchedToSQ++;
1042  } else if (inst->isReadBarrier() || inst->isWriteBarrier()) {
1043  // Same as non-speculative stores.
1044  inst->setCanCommit();
1045  instQueue.insertBarrier(inst);
1046  add_to_iq = false;
1047  } else if (inst->isNop()) {
1048  DPRINTF(IEW, "[tid:%i] Issue: Nop instruction encountered, "
1049  "skipping.\n", tid);
1050 
1051  inst->setIssued();
1052  inst->setExecuted();
1053  inst->setCanCommit();
1054 
1055  instQueue.recordProducer(inst);
1056 
1058 
1059  add_to_iq = false;
1060  } else {
1061  assert(!inst->isExecuted());
1062  add_to_iq = true;
1063  }
1064 
1065  if (add_to_iq && inst->isNonSpeculative()) {
1066  DPRINTF(IEW, "[tid:%i] Issue: Nonspeculative instruction "
1067  "encountered, skipping.\n", tid);
1068 
1069  // Same as non-speculative stores.
1070  inst->setCanCommit();
1071 
1072  // Specifically insert it as nonspeculative.
1073  instQueue.insertNonSpec(inst);
1074 
1076 
1077  add_to_iq = false;
1078  }
1079 
1080  // If the instruction queue is not full, then add the
1081  // instruction.
1082  if (add_to_iq) {
1083  instQueue.insert(inst);
1084  }
1085 
1086  insts_to_dispatch.pop();
1087 
1088  toRename->iewInfo[tid].dispatched++;
1089 
1091 
1092 #if TRACING_ON
1093  inst->dispatchTick = curTick() - inst->fetchTick;
1094 #endif
1095  ppDispatch->notify(inst);
1096  }
1097 
1098  if (!insts_to_dispatch.empty()) {
1099  DPRINTF(IEW,"[tid:%i] Issue: Bandwidth Full. Blocking.\n", tid);
1100  block(tid);
1101  toRename->iewUnblock[tid] = false;
1102  }
1103 
1104  if (dispatchStatus[tid] == Idle && dis_num_inst) {
1105  dispatchStatus[tid] = Running;
1106 
1107  updatedQueues = true;
1108  }
1109 
1110  dis_num_inst = 0;
1111 }
1112 
1113 void
1115 {
1116  int inst = 0;
1117 
1118  std::cout << "Available Instructions: ";
1119 
1120  while (fromIssue->insts[inst]) {
1121 
1122  if (inst%3==0) std::cout << "\n\t";
1123 
1124  std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1125  << " TN: " << fromIssue->insts[inst]->threadNumber
1126  << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1127 
1128  inst++;
1129 
1130  }
1131 
1132  std::cout << "\n";
1133 }
1134 
1135 void
1137 {
1138  wbNumInst = 0;
1139  wbCycle = 0;
1140 
1141  std::list<ThreadID>::iterator threads = activeThreads->begin();
1143 
1144  while (threads != end) {
1145  ThreadID tid = *threads++;
1146  fetchRedirect[tid] = false;
1147  }
1148 
1149  // Uncomment this if you want to see all available instructions.
1150  // @todo This doesn't actually work anymore, we should fix it.
1151 // printAvailableInsts();
1152 
1153  // Execute/writeback any instructions that are available.
1154  int insts_to_execute = fromIssue->size;
1155  int inst_num = 0;
1156  for (; inst_num < insts_to_execute;
1157  ++inst_num) {
1158 
1159  DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1160 
1162 
1163  DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%llu].\n",
1164  inst->pcState(), inst->threadNumber,inst->seqNum);
1165 
1166  // Notify potential listeners that this instruction has started
1167  // executing
1168  ppExecute->notify(inst);
1169 
1170  // Check if the instruction is squashed; if so then skip it
1171  if (inst->isSquashed()) {
1172  DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1173  " [sn:%llu]\n", inst->pcState(), inst->threadNumber,
1174  inst->seqNum);
1175 
1176  // Consider this instruction executed so that commit can go
1177  // ahead and retire the instruction.
1178  inst->setExecuted();
1179 
1180  // Not sure if I should set this here or just let commit try to
1181  // commit any squashed instructions. I like the latter a bit more.
1182  inst->setCanCommit();
1183 
1185 
1186  continue;
1187  }
1188 
1189  Fault fault = NoFault;
1190 
1191  // Execute instruction.
1192  // Note that if the instruction faults, it will be handled
1193  // at the commit stage.
1194  if (inst->isMemRef()) {
1195  DPRINTF(IEW, "Execute: Calculating address for memory "
1196  "reference.\n");
1197 
1198  // Tell the LDSTQ to execute this instruction (if it is a load).
1199  if (inst->isAtomic()) {
1200  // AMOs are treated like store requests
1201  fault = ldstQueue.executeStore(inst);
1202 
1203  if (inst->isTranslationDelayed() &&
1204  fault == NoFault) {
1205  // A hw page table walk is currently going on; the
1206  // instruction must be deferred.
1207  DPRINTF(IEW, "Execute: Delayed translation, deferring "
1208  "store.\n");
1209  instQueue.deferMemInst(inst);
1210  continue;
1211  }
1212  } else if (inst->isLoad()) {
1213  // Loads will mark themselves as executed, and their writeback
1214  // event adds the instruction to the queue to commit
1215  fault = ldstQueue.executeLoad(inst);
1216 
1217  if (inst->isTranslationDelayed() &&
1218  fault == NoFault) {
1219  // A hw page table walk is currently going on; the
1220  // instruction must be deferred.
1221  DPRINTF(IEW, "Execute: Delayed translation, deferring "
1222  "load.\n");
1223  instQueue.deferMemInst(inst);
1224  continue;
1225  }
1226 
1227  if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1228  inst->fault = NoFault;
1229  }
1230  } else if (inst->isStore()) {
1231  fault = ldstQueue.executeStore(inst);
1232 
1233  if (inst->isTranslationDelayed() &&
1234  fault == NoFault) {
1235  // A hw page table walk is currently going on; the
1236  // instruction must be deferred.
1237  DPRINTF(IEW, "Execute: Delayed translation, deferring "
1238  "store.\n");
1239  instQueue.deferMemInst(inst);
1240  continue;
1241  }
1242 
1243  // If the store had a fault then it may not have a mem req
1244  if (fault != NoFault || !inst->readPredicate() ||
1245  !inst->isStoreConditional()) {
1246  // If the instruction faulted, then we need to send it
1247  // along to commit without the instruction completing.
1248  // Send this instruction to commit, also make sure iew
1249  // stage realizes there is activity.
1250  inst->setExecuted();
1251  instToCommit(inst);
1253  }
1254 
1255  // Store conditionals will mark themselves as
1256  // executed, and their writeback event will add the
1257  // instruction to the queue to commit.
1258  } else {
1259  panic("Unexpected memory type!\n");
1260  }
1261 
1262  } else {
1263  // If the instruction has already faulted, then skip executing it.
1264  // Such case can happen when it faulted during ITLB translation.
1265  // If we execute the instruction (even if it's a nop) the fault
1266  // will be replaced and we will lose it.
1267  if (inst->getFault() == NoFault) {
1268  inst->execute();
1269  if (!inst->readPredicate())
1270  inst->forwardOldRegs();
1271  }
1272 
1273  inst->setExecuted();
1274 
1275  instToCommit(inst);
1276  }
1277 
1278  updateExeInstStats(inst);
1279 
1280  // Check if branch prediction was correct, if not then we need
1281  // to tell commit to squash in flight instructions. Only
1282  // handle this if there hasn't already been something that
1283  // redirects fetch in this group of instructions.
1284 
1285  // This probably needs to prioritize the redirects if a different
1286  // scheduler is used. Currently the scheduler schedules the oldest
1287  // instruction first, so the branch resolution order will be correct.
1288  ThreadID tid = inst->threadNumber;
1289 
1290  if (!fetchRedirect[tid] ||
1291  !toCommit->squash[tid] ||
1292  toCommit->squashedSeqNum[tid] > inst->seqNum) {
1293 
1294  // Prevent testing for misprediction on load instructions,
1295  // that have not been executed.
1296  bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1297 
1298  if (inst->mispredicted() && !loadNotExecuted) {
1299  fetchRedirect[tid] = true;
1300 
1301  DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1302  "Branch mispredict detected.\n",
1303  tid, inst->seqNum);
1304  DPRINTF(IEW, "[tid:%i] [sn:%llu] "
1305  "Predicted target was PC: %s\n",
1306  tid, inst->seqNum, inst->readPredTarg());
1307  DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1308  "Redirecting fetch to PC: %s\n",
1309  tid, inst->seqNum, inst->pcState());
1310  // If incorrect, then signal the ROB that it must be squashed.
1311  squashDueToBranch(inst, tid);
1312 
1313  ppMispredict->notify(inst);
1314 
1315  if (inst->readPredTaken()) {
1317  } else {
1319  }
1320  } else if (ldstQueue.violation(tid)) {
1321  assert(inst->isMemRef());
1322  // If there was an ordering violation, then get the
1323  // DynInst that caused the violation. Note that this
1324  // clears the violation signal.
1325  DynInstPtr violator;
1326  violator = ldstQueue.getMemDepViolator(tid);
1327 
1328  DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1329  "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1330  violator->pcState(), violator->seqNum,
1331  inst->pcState(), inst->seqNum, inst->physEffAddr);
1332 
1333  fetchRedirect[tid] = true;
1334 
1335  // Tell the instruction queue that a violation has occured.
1336  instQueue.violation(inst, violator);
1337 
1338  // Squash.
1339  squashDueToMemOrder(violator, tid);
1340 
1342  }
1343  } else {
1344  // Reset any state associated with redirects that will not
1345  // be used.
1346  if (ldstQueue.violation(tid)) {
1347  assert(inst->isMemRef());
1348 
1349  DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1350 
1351  DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
1352  "%s, inst PC: %s. Addr is: %#x.\n",
1353  violator->pcState(), inst->pcState(),
1354  inst->physEffAddr);
1355  DPRINTF(IEW, "Violation will not be handled because "
1356  "already squashing\n");
1357 
1359  }
1360  }
1361  }
1362 
1363  // Update and record activity if we processed any instructions.
1364  if (inst_num) {
1365  if (exeStatus == Idle) {
1366  exeStatus = Running;
1367  }
1368 
1369  updatedQueues = true;
1370 
1372  }
1373 
1374  // Need to reset this in case a writeback event needs to write into the
1375  // iew queue. That way the writeback event will write into the correct
1376  // spot in the queue.
1377  wbNumInst = 0;
1378 
1379 }
1380 
1381 void
1383 {
1384  // Loop through the head of the time buffer and wake any
1385  // dependents. These instructions are about to write back. Also
1386  // mark scoreboard that this instruction is finally complete.
1387  // Either have IEW have direct access to scoreboard, or have this
1388  // as part of backwards communication.
1389  for (int inst_num = 0; inst_num < wbWidth &&
1390  toCommit->insts[inst_num]; inst_num++) {
1391  DynInstPtr inst = toCommit->insts[inst_num];
1392  ThreadID tid = inst->threadNumber;
1393 
1394  DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1395  inst->seqNum, inst->pcState());
1396 
1397  iewStats.instsToCommit[tid]++;
1398  // Notify potential listeners that execution is complete for this
1399  // instruction.
1400  ppToCommit->notify(inst);
1401 
1402  // Some instructions will be sent to commit without having
1403  // executed because they need commit to handle them.
1404  // E.g. Strictly ordered loads have not actually executed when they
1405  // are first sent to commit. Instead commit must tell the LSQ
1406  // when it's ready to execute the strictly ordered load.
1407  if (!inst->isSquashed() && inst->isExecuted() &&
1408  inst->getFault() == NoFault) {
1409  int dependents = instQueue.wakeDependents(inst);
1410 
1411  for (int i = 0; i < inst->numDestRegs(); i++) {
1412  // Mark register as ready if not pinned
1413  if (inst->renamedDestIdx(i)->
1414  getNumPinnedWritesToComplete() == 0) {
1415  DPRINTF(IEW,"Setting Destination Register %i (%s)\n",
1416  inst->renamedDestIdx(i)->index(),
1417  inst->renamedDestIdx(i)->className());
1418  scoreboard->setReg(inst->renamedDestIdx(i));
1419  }
1420  }
1421 
1422  if (dependents) {
1423  iewStats.producerInst[tid]++;
1424  iewStats.consumerInst[tid]+= dependents;
1425  }
1426  iewStats.writebackCount[tid]++;
1427  }
1428  }
1429 }
1430 
1431 void
1433 {
1434  wbNumInst = 0;
1435  wbCycle = 0;
1436 
1437  wroteToTimeBuffer = false;
1438  updatedQueues = false;
1439 
1440  ldstQueue.tick();
1441 
1442  sortInsts();
1443 
1444  // Free function units marked as being freed this cycle.
1446 
1447  std::list<ThreadID>::iterator threads = activeThreads->begin();
1449 
1450  // Check stall and squash signals, dispatch any instructions.
1451  while (threads != end) {
1452  ThreadID tid = *threads++;
1453 
1454  DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1455 
1456  checkSignalsAndUpdate(tid);
1457  dispatch(tid);
1458  }
1459 
1460  if (exeStatus != Squashing) {
1461  executeInsts();
1462 
1463  writebackInsts();
1464 
1465  // Have the instruction queue try to schedule any ready instructions.
1466  // (In actuality, this scheduling is for instructions that will
1467  // be executed next cycle.)
1469 
1470  // Also should advance its own time buffers if the stage ran.
1471  // Not the best place for it, but this works (hopefully).
1472  issueToExecQueue.advance();
1473  }
1474 
1475  bool broadcast_free_entries = false;
1476 
1478  exeStatus = Idle;
1479  updateLSQNextCycle = false;
1480 
1481  broadcast_free_entries = true;
1482  }
1483 
1484  // Writeback any stores using any leftover bandwidth.
1486 
1487  // Check the committed load/store signals to see if there's a load
1488  // or store to commit. Also check if it's being told to execute a
1489  // nonspeculative instruction.
1490  // This is pretty inefficient...
1491 
1492  threads = activeThreads->begin();
1493  while (threads != end) {
1494  ThreadID tid = (*threads++);
1495 
1496  DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1497 
1498  // Update structures based on instructions committed.
1499  if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1500  !fromCommit->commitInfo[tid].squash &&
1501  !fromCommit->commitInfo[tid].robSquashing) {
1502 
1503  ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1504 
1505  ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1506 
1507  updateLSQNextCycle = true;
1508  instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1509  }
1510 
1511  if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1512 
1513  //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1514  if (fromCommit->commitInfo[tid].strictlyOrdered) {
1516  fromCommit->commitInfo[tid].strictlyOrderedLoad);
1517  fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit();
1518  } else {
1520  fromCommit->commitInfo[tid].nonSpecSeqNum);
1521  }
1522  }
1523 
1524  if (broadcast_free_entries) {
1525  toFetch->iewInfo[tid].iqCount =
1526  instQueue.getCount(tid);
1527  toFetch->iewInfo[tid].ldstqCount =
1528  ldstQueue.getCount(tid);
1529 
1530  toRename->iewInfo[tid].usedIQ = true;
1531  toRename->iewInfo[tid].freeIQEntries =
1533  toRename->iewInfo[tid].usedLSQ = true;
1534 
1535  toRename->iewInfo[tid].freeLQEntries =
1537  toRename->iewInfo[tid].freeSQEntries =
1539 
1540  wroteToTimeBuffer = true;
1541  }
1542 
1543  DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1544  tid, toRename->iewInfo[tid].dispatched);
1545  }
1546 
1547  DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
1548  "LQ has %i free entries. SQ has %i free entries.\n",
1551 
1552  updateStatus();
1553 
1554  if (wroteToTimeBuffer) {
1555  DPRINTF(Activity, "Activity this cycle.\n");
1557  }
1558 }
1559 
1560 void
1562 {
1563  ThreadID tid = inst->threadNumber;
1564 
1566 
1567 #if TRACING_ON
1568  if (debug::O3PipeView) {
1569  inst->completeTick = curTick() - inst->fetchTick;
1570  }
1571 #endif
1572 
1573  //
1574  // Control operations
1575  //
1576  if (inst->isControl())
1578 
1579  //
1580  // Memory operations
1581  //
1582  if (inst->isMemRef()) {
1584 
1585  if (inst->isLoad()) {
1587  }
1588  }
1589 }
1590 
1591 void
1593 {
1594  ThreadID tid = inst->threadNumber;
1595 
1596  if (!fetchRedirect[tid] ||
1597  !toCommit->squash[tid] ||
1598  toCommit->squashedSeqNum[tid] > inst->seqNum) {
1599 
1600  if (inst->mispredicted()) {
1601  fetchRedirect[tid] = true;
1602 
1603  DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1604  "Branch mispredict detected.\n",
1605  tid, inst->seqNum);
1606  DPRINTF(IEW, "[tid:%i] [sn:%llu] Predicted target was PC: %s\n",
1607  tid, inst->seqNum, inst->readPredTarg());
1608  DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1609  "Redirecting fetch to PC: %s\n",
1610  tid, inst->seqNum, inst->pcState());
1611  // If incorrect, then signal the ROB that it must be squashed.
1612  squashDueToBranch(inst, tid);
1613 
1614  if (inst->readPredTaken()) {
1616  } else {
1618  }
1619  }
1620  }
1621 }
1622 
1623 } // namespace o3
1624 } // namespace gem5
gem5::o3::InstructionQueue::rescheduleMemInst
void rescheduleMemInst(const DynInstPtr &resched_inst)
Reschedules a memory instruction.
Definition: inst_queue.cc:1088
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::o3::LSQ::insertStore
void insertStore(const DynInstPtr &store_inst)
Inserts a store into the LSQ.
Definition: lsq.cc:229
gem5::o3::InstructionQueue::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: inst_queue.cc:464
gem5::o3::IEW::skidCount
int skidCount()
Returns the max of the number of entries in all of the skid buffers.
Definition: iew.cc:617
gem5::o3::IEW::IEWStats::unblockCycles
statistics::Scalar unblockCycles
Stat for total number of unblocking cycles.
Definition: iew.hh:429
gem5::o3::IEW::IEWStats::dispStoreInsts
statistics::Scalar dispStoreInsts
Stat for total number of dispatched store instructions.
Definition: iew.hh:437
gem5::o3::LSQ::commitLoads
void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
Commits loads up until the given sequence number for a specific thread.
Definition: lsq.cc:253
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::o3::IEW::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets main time buffer used for backwards communication.
Definition: iew.cc:305
gem5::o3::IEW::toFetch
TimeBuffer< TimeStruct >::wire toFetch
Wire to write information heading to previous stages.
Definition: iew.hh:303
gem5::o3::IEW::insts
std::queue< DynInstPtr > insts[MaxThreads]
Queue of all instructions coming from rename this cycle.
Definition: iew.hh:333
gem5::o3::IEW::skidsEmpty
bool skidsEmpty()
Returns if all of the skid buffers are empty.
Definition: iew.cc:635
gem5::o3::IEW::IEWStats::executedInstStats
gem5::o3::IEW::IEWStats::ExecutedInstStats executedInstStats
gem5::o3::IEW::ppToCommit
ProbePointArg< DynInstPtr > * ppToCommit
To probe when instruction execution is complete.
Definition: iew.hh:126
gem5::o3::IEW::IEWStats::wbRate
statistics::Formula wbRate
Number of instructions per cycle written back.
Definition: iew.hh:488
gem5::o3::IEW::renameQueue
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue interface.
Definition: iew.hh:312
gem5::o3::IEW::IEWStats::blockCycles
statistics::Scalar blockCycles
Stat for total number of blocking cycles.
Definition: iew.hh:427
gem5::o3::InstructionQueue::isFull
bool isFull()
Returns whether or not the IQ is full.
Definition: inst_queue.cc:526
gem5::o3::IEW::IEWStats::producerInst
statistics::Vector producerInst
Number of instructions that wake consumers.
Definition: iew.hh:484
gem5::o3::IEW::checkSignalsAndUpdate
void checkSignalsAndUpdate(ThreadID tid)
Processes inputs and changes state accordingly.
Definition: iew.cc:707
gem5::o3::IEW::updateExeInstStats
void updateExeInstStats(const DynInstPtr &inst)
Updates execution stats based on the instruction.
Definition: iew.cc:1561
gem5::o3::LSQ::getCount
int getCount()
Returns the number of instructions in all of the queues.
Definition: lsq.cc:473
gem5::o3::LSQ::writebackStores
void writebackStores()
Attempts to write back stores until all cache ports are used or the interface becomes blocked.
Definition: lsq.cc:265
gem5::o3::LSQ::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets the pointer to the list of active threads.
Definition: lsq.cc:130
gem5::o3::IEW::dispatchStatus
StageStatus dispatchStatus[MaxThreads]
Dispatch status.
Definition: iew.hh:114
gem5::o3::IEW::updateStatus
void updateStatus()
Updates overall IEW status based on all of the stages' statuses.
Definition: iew.cc:651
gem5::o3::IEW::replayMemInst
void replayMemInst(const DynInstPtr &inst)
Re-executes all rescheduled memory instructions.
Definition: iew.cc:550
gem5::o3::IEW::IEWStats::ExecutedInstStats::numStoreInsts
statistics::Formula numStoreInsts
Number of executed store instructions.
Definition: iew.hh:474
gem5::o3::IEW::IEWStats::ExecutedInstStats::numRefs
statistics::Vector numRefs
Number of executed meomory references.
Definition: iew.hh:470
gem5::o3::IEW::ppMispredict
ProbePointArg< DynInstPtr > * ppMispredict
Probe points.
Definition: iew.hh:121
gem5::o3::IEW::Active
@ Active
Definition: iew.hh:95
gem5::o3::IEW::Unblocking
@ Unblocking
Definition: iew.hh:107
gem5::ArmISA::set
Bitfield< 12, 11 > set
Definition: misc_types.hh:703
gem5::o3::IEW::IEWStats::predictedNotTakenIncorrect
statistics::Scalar predictedNotTakenIncorrect
Stat for total number of incorrect predicted not taken branches.
Definition: iew.hh:449
gem5::o3::FUPool::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: fu_pool.hh:182
gem5::o3::IEW::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: iew.cc:392
gem5::o3::IEW::checkMisprediction
void checkMisprediction(const DynInstPtr &inst)
Check misprediction
Definition: iew.cc:1592
gem5::o3::IEW::fromRename
TimeBuffer< RenameStruct >::wire fromRename
Wire to get rename's output from rename queue.
Definition: iew.hh:315
gem5::o3::IEW::iewStats
gem5::o3::IEW::IEWStats iewStats
gem5::o3::InstructionQueue::commit
void commit(const InstSeqNum &inst, ThreadID tid=0)
Commits all instructions up to and including the given sequence number, for a specific thread.
Definition: inst_queue.cc:948
gem5::o3::IEW::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: iew.cc:293
gem5::o3::IEW::wakeDependents
void wakeDependents(const DynInstPtr &inst)
Wakes all dependents of a completed instruction.
Definition: iew.cc:538
gem5::o3::IEW::commitToIEWDelay
Cycles commitToIEWDelay
Commit to IEW delay.
Definition: iew.hh:377
gem5::o3::IEW::IEWStats::iqFullEvents
statistics::Scalar iqFullEvents
Stat for number of times the IQ becomes full.
Definition: iew.hh:441
gem5::o3::IEW::issueToExecQueue
TimeBuffer< IssueStruct > issueToExecQueue
Issue stage queue.
Definition: iew.hh:318
gem5::o3::IEW::IEWStats::wbFanout
statistics::Formula wbFanout
Average number of woken instructions per writeback.
Definition: iew.hh:490
gem5::o3::Scoreboard
Implements a simple scoreboard to track which registers are ready.
Definition: scoreboard.hh:54
gem5::o3::IEW::skidInsert
void skidInsert(ThreadID tid)
Inserts unused instructions of a thread into the skid buffer.
Definition: iew.cc:596
gem5::o3::IEW::writebackInsts
void writebackInsts()
Writebacks instructions.
Definition: iew.cc:1382
gem5::o3::InstructionQueue::IQIOStats::intInstQueueReads
statistics::Scalar intInstQueueReads
Definition: inst_queue.hh:550
gem5::o3::IEW::emptyRenameInsts
void emptyRenameInsts(ThreadID tid)
Removes instructions from rename from a thread's instruction list.
Definition: iew.cc:783
gem5::o3::IEW::activeThreads
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Definition: iew.hh:412
dyn_inst.hh
gem5::o3::IEW::exeStatus
StageStatus exeStatus
Execute status.
Definition: iew.hh:116
gem5::o3::IEW::toCommit
TimeBuffer< IEWStruct >::wire toCommit
Wire to write infromation heading to commit.
Definition: iew.hh:330
gem5::o3::IEW::dispatchInsts
void dispatchInsts(ThreadID tid)
Dispatches instructions to IQ and LSQ.
Definition: iew.cc:878
gem5::o3::IEW::sortInsts
void sortInsts()
Sorts instructions coming from rename into lists separated by thread.
Definition: iew.cc:770
gem5::o3::IEW::IEW
IEW(CPU *_cpu, const BaseO3CPUParams &params)
Constructs a IEW with the given parameters.
Definition: iew.cc:68
gem5::o3::IEW::checkStall
bool checkStall(ThreadID tid)
Checks if any of the stall conditions are currently true.
Definition: iew.cc:691
gem5::o3::InstructionQueue::recordProducer
void recordProducer(const DynInstPtr &inst)
Records the instruction as the producer of a register without adding it to the rest of the IQ.
Definition: inst_queue.hh:215
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
iew.hh
gem5::o3::InstructionQueue::cacheUnblocked
void cacheUnblocked()
Notify instruction queue that a previous blockage has resolved.
Definition: inst_queue.cc:1124
gem5::o3::InstructionQueue::takeOverFrom
void takeOverFrom()
Takes over execution from another CPU's thread.
Definition: inst_queue.cc:473
gem5::o3::IEW::toRename
TimeBuffer< TimeStruct >::wire toRename
Wire to write information heading to previous stages.
Definition: iew.hh:309
gem5::o3::IEW::squash
void squash(ThreadID tid)
Squashes instructions in IEW for a specific thread.
Definition: iew.cc:419
gem5::o3::IEW::IEWStats::ExecutedInstStats::numSquashedInsts
statistics::Scalar numSquashedInsts
Stat for total number of squashed instructions skipped at execute.
Definition: iew.hh:464
gem5::o3::IEW::IEWStats::writebackCount
statistics::Vector writebackCount
Number of instructions that writeback.
Definition: iew.hh:482
gem5::o3::InstructionQueue::setIssueToExecuteQueue
void setIssueToExecuteQueue(TimeBuffer< IssueStruct > *i2eQueue)
Sets the timer buffer between issue and execute.
Definition: inst_queue.cc:438
gem5::o3::IEW::Inactive
@ Inactive
Definition: iew.hh:96
gem5::o3::LSQ::executeStore
Fault executeStore(const DynInstPtr &inst)
Executes a store.
Definition: lsq.cc:245
gem5::o3::IEW::wakeCPU
void wakeCPU()
Tells the CPU to wakeup if it has descheduled itself due to no activity.
Definition: iew.cc:804
gem5::o3::IEW::Blocked
@ Blocked
Definition: iew.hh:103
gem5::o3::IEW::startupStage
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
Definition: iew.cc:270
gem5::RefCountingPtr< DynInst >
gem5::o3::IEW::rescheduleMemInst
void rescheduleMemInst(const DynInstPtr &inst)
Tells memory dependence unit that a memory instruction needs to be rescheduled.
Definition: iew.cc:544
gem5::TimeBuffer
Definition: timebuf.hh:40
gem5::o3::LSQ::sqFull
bool sqFull()
Returns if any of the SQs are full.
Definition: lsq.cc:662
gem5::o3::IEW::Squashing
@ Squashing
Definition: iew.hh:106
gem5::o3::CPU::checker
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
Definition: cpu.hh:525
gem5::o3::LSQ::violation
bool violation()
Returns whether or not there was a memory ordering violation.
Definition: lsq.cc:289
gem5::o3::InstructionQueue::wakeDependents
int wakeDependents(const DynInstPtr &completed_inst)
Wakes all dependents of a completed instruction.
Definition: inst_queue.cc:965
gem5::o3::CPU::deactivateStage
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
Definition: cpu.hh:497
gem5::o3::IEW::wroteToTimeBuffer
bool wroteToTimeBuffer
Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if th...
Definition: iew.hh:348
gem5::o3::InstructionQueue::iqIOStats
gem5::o3::InstructionQueue::IQIOStats iqIOStats
gem5::o3::IEW::fromCommit
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's output from backwards time buffer.
Definition: iew.hh:306
timebuf.hh
gem5::o3::IEW::IEWStats::ExecutedInstStats::numLoadInsts
statistics::Vector numLoadInsts
Stat for total number of executed load instructions.
Definition: iew.hh:461
gem5::o3::IEW::instQueue
InstructionQueue instQueue
Instruction queue.
Definition: iew.hh:355
gem5::o3::LSQ::numHtmStarts
int numHtmStarts(ThreadID tid) const
Definition: lsq.cc:344
gem5::o3::IEW::IEWStats::consumerInst
statistics::Vector consumerInst
Number of instructions that wake up from producers.
Definition: iew.hh:486
gem5::o3::IEW::block
void block(ThreadID tid)
Sets Dispatch to blocked, and signals back to other stages to block.
Definition: iew.cc:504
gem5::o3::IEW::IEWStats::dispSquashedInsts
statistics::Scalar dispSquashedInsts
Stat for total number of squashed instructions dispatch skips.
Definition: iew.hh:433
gem5::o3::IEW::_status
Status _status
Overall stage status.
Definition: iew.hh:112
gem5::o3::CPU::IEWIdx
@ IEWIdx
Definition: cpu.hh:457
gem5::o3::FUPool::isDrained
bool isDrained() const
Have all the FUs drained?
Definition: fu_pool.cc:244
gem5::o3::LSQ::tick
void tick()
Ticks the LSQ.
Definition: lsq.cc:175
gem5::o3::IEW::IEWStats::instsToCommit
statistics::Vector instsToCommit
Number of instructions sent to commit.
Definition: iew.hh:480
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::o3::IEW::isDrained
bool isDrained() const
Has the stage drained?
Definition: iew.cc:355
gem5::o3::InstructionQueue::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the global time buffer.
Definition: inst_queue.cc:444
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::o3::LSQ::isDrained
bool isDrained() const
Has the LSQ drained?
Definition: lsq.cc:146
gem5::o3::IEW::squashDueToBranch
void squashDueToBranch(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a branch mispredict.
Definition: iew.cc:454
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::o3::Scoreboard::setReg
void setReg(PhysRegIdPtr phys_reg)
Sets the register as ready.
Definition: scoreboard.hh:97
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::o3::InstructionQueue::deferMemInst
void deferMemInst(const DynInstPtr &deferred_inst)
Defers a memory instruction when its DTB translation incurs a hw page table walk.
Definition: inst_queue.cc:1107
cpu.hh
gem5::o3::IEW::skidBuffer
std::queue< DynInstPtr > skidBuffer[MaxThreads]
Skid buffer between rename and IEW.
Definition: iew.hh:336
gem5::o3::IEW::fuPool
FUPool * fuPool
Pointer to the functional unit pool.
Definition: iew.hh:361
gem5::o3::CPU::activateStage
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
Definition: cpu.hh:490
gem5::o3::LSQ::getLatestHtmUid
uint64_t getLatestHtmUid(ThreadID tid) const
Definition: lsq.cc:368
gem5::o3::LSQ::willWB
bool willWB()
Returns if the LSQ will write back to memory this cycle.
Definition: lsq.cc:742
gem5::o3::LSQ::numFreeLoadEntries
unsigned numFreeLoadEntries()
Returns the number of free load entries.
Definition: lsq.cc:524
gem5::o3::InstructionQueue::numFreeEntries
unsigned numFreeEntries()
Returns total number of free entries.
Definition: inst_queue.cc:512
gem5::o3::IEW::IEWStats::ExecutedInstStats::numInsts
statistics::Scalar numInsts
Stat for total number of executed instructions.
Definition: iew.hh:459
gem5::o3::IEW::wbStatus
StageStatus wbStatus
Writeback status.
Definition: iew.hh:118
gem5::o3::IEW::activityThisCycle
void activityThisCycle()
Reports to the CPU that there is activity this cycle.
Definition: iew.cc:810
gem5::o3::CPU::wakeCPU
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
Definition: cpu.cc:1397
gem5::o3::IEW::renameToIEWDelay
Cycles renameToIEWDelay
Rename to IEW delay.
Definition: iew.hh:380
gem5::o3::IEW::iewQueue
TimeBuffer< IEWStruct > * iewQueue
IEW stage time buffer.
Definition: iew.hh:327
gem5::o3::FUPool::processFreeUnits
void processFreeUnits()
Frees all FUs on the list.
Definition: fu_pool.cc:197
gem5::o3::MaxWidth
static constexpr int MaxWidth
Definition: limits.hh:37
fu_pool.hh
gem5::o3::IEW::dispatchWidth
unsigned dispatchWidth
Width of dispatch, in instructions.
Definition: iew.hh:390
gem5::o3::IEW::Running
@ Running
Definition: iew.hh:102
gem5::o3::InstructionQueue::scheduleNonSpec
void scheduleNonSpec(const InstSeqNum &inst)
Schedules a single specific non-speculative instruction.
Definition: inst_queue.cc:921
gem5::o3::IEW::IEWStats::memOrderViolationEvents
statistics::Scalar memOrderViolationEvents
Stat for total number of memory ordering violation events.
Definition: iew.hh:445
gem5::o3::IEW::tick
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle.
Definition: iew.cc:1432
gem5::o3::IEW::IEWStats::dispatchedInsts
statistics::Scalar dispatchedInsts
Stat for total number of instructions dispatched.
Definition: iew.hh:431
gem5::o3::IEW::printAvailableInsts
void printAvailableInsts()
Debug function to print instructions that are issued this cycle.
Definition: iew.cc:1114
gem5::o3::IEW::IEWStats::ExecutedInstStats::ExecutedInstStats
ExecutedInstStats(CPU *cpu)
Definition: iew.cc:219
gem5::o3::IEW::IEWStats::ExecutedInstStats::numNop
statistics::Vector numNop
Number of executed nops.
Definition: iew.hh:468
gem5::o3::IEW::cpu
CPU * cpu
CPU pointer.
Definition: iew.hh:343
gem5::o3::LSQ::getMemDepViolator
DynInstPtr getMemDepViolator(ThreadID tid)
Gets the instruction that caused the memory ordering violation.
Definition: lsq.cc:308
gem5::o3::InstructionQueue::getInstToExecute
DynInstPtr getInstToExecute()
Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to exe...
Definition: inst_queue.cc:661
gem5::o3::IEW::wbWidth
unsigned wbWidth
Writeback width.
Definition: iew.hh:406
gem5::o3::LSQ::squash
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squash instructions from a thread until the specified sequence number.
Definition: lsq.cc:283
gem5::o3::IEW::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
Pointer to main time buffer used for backwards communication.
Definition: iew.hh:300
gem5::o3::LSQ::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: lsq.cc:137
gem5::o3::IEW::IEWStats::predictedTakenIncorrect
statistics::Scalar predictedTakenIncorrect
Stat for total number of incorrect predicted taken branches.
Definition: iew.hh:447
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::o3::IEW::fetchRedirect
bool fetchRedirect[MaxThreads]
Records if there is a fetch redirect on this cycle for each thread.
Definition: iew.hh:369
gem5::o3::IEW::IEWStats::squashCycles
statistics::Scalar squashCycles
Stat for total number of squashing cycles.
Definition: iew.hh:425
gem5::o3::InstructionQueue::insertBarrier
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly.
Definition: inst_queue.cc:653
gem5::o3::IEW::IEWStats::dispLoadInsts
statistics::Scalar dispLoadInsts
Stat for total number of dispatched load instructions.
Definition: iew.hh:435
gem5::o3::IEW::fromIssue
TimeBuffer< IssueStruct >::wire fromIssue
Wire to read information from the issue stage time queue.
Definition: iew.hh:321
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::CPU::activityThisCycle
void activityThisCycle()
Records that there was time buffer activity this cycle.
Definition: cpu.hh:486
gem5::o3::IEW::unblock
void unblock(ThreadID tid)
Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock.
Definition: iew.cc:522
gem5::o3::InstructionQueue::squash
void squash(ThreadID tid)
Squashes instructions for a thread.
Definition: inst_queue.cc:1168
gem5::o3::IEW::issueWidth
unsigned issueWidth
Width of issue, in instructions.
Definition: iew.hh:393
gem5::o3::LSQ::insertLoad
void insertLoad(const DynInstPtr &load_inst)
Inserts a load into the LSQ.
Definition: lsq.cc:221
gem5::o3::IEW::instToCommit
void instToCommit(const DynInstPtr &inst)
Sends an instruction to commit through the time buffer.
Definition: iew.cc:568
gem5::o3::IEW::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: iew.cc:383
gem5::o3::IEW::ppExecute
ProbePointArg< DynInstPtr > * ppExecute
To probe when instruction execution begins.
Definition: iew.hh:124
gem5::o3::IEW::IEWStats::dispNonSpecInsts
statistics::Scalar dispNonSpecInsts
Stat for total number of dispatched non speculative insts.
Definition: iew.hh:439
gem5::o3::IEW::blockMemInst
void blockMemInst(const DynInstPtr &inst)
Moves memory instruction onto the list of cache blocked instructions.
Definition: iew.cc:556
gem5::o3::IEW::wbCycle
unsigned wbCycle
Cycle number within the queue of instructions being written back.
Definition: iew.hh:403
gem5::o3::IEW::cacheUnblocked
void cacheUnblocked()
Notifies that the cache has become unblocked.
Definition: iew.cc:562
gem5::o3::InstructionQueue::isDrained
bool isDrained() const
Determine if we are drained.
Definition: inst_queue.cc:452
gem5::o3::IEW::IEWStats::lsqFullEvents
statistics::Scalar lsqFullEvents
Stat for number of times the LSQ becomes full.
Definition: iew.hh:443
gem5::o3::InstructionQueue::insertNonSpec
void insertNonSpec(const DynInstPtr &new_inst)
Inserts a new, non-speculative instruction into the IQ.
Definition: inst_queue.cc:607
gem5::o3::InstructionQueue::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets active threads list.
Definition: inst_queue.cc:432
gem5::o3::InstructionQueue::blockMemInst
void blockMemInst(const DynInstPtr &blocked_inst)
Defers a memory instruction when it is cache blocked.
Definition: inst_queue.cc:1113
gem5::o3::LSQ::numFreeStoreEntries
unsigned numFreeStoreEntries()
Returns the number of free store entries.
Definition: lsq.cc:541
gem5::o3::IEW::wbNumInst
unsigned wbNumInst
Index into queue of instructions being written back.
Definition: iew.hh:396
gem5::o3::IEW::skidBufferMax
unsigned skidBufferMax
Maximum size of the skid buffer.
Definition: iew.hh:415
gem5::o3::IEW::deactivateStage
void deactivateStage()
Tells CPU that the IEW stage is inactive and idle.
Definition: iew.cc:824
gem5::o3::IEW::scoreboard
Scoreboard * scoreboard
Scoreboard pointer.
Definition: iew.hh:339
gem5::o3::IEW::ppDispatch
ProbePointArg< DynInstPtr > * ppDispatch
Definition: iew.hh:122
gem5::o3::IEW::setRenameQueue
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets time buffer for getting instructions coming from rename.
Definition: iew.cc:322
gem5::o3::InstructionQueue::insert
void insert(const DynInstPtr &new_inst)
Inserts a new instruction into the IQ.
Definition: inst_queue.cc:562
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::IEW::updateLSQNextCycle
bool updateLSQNextCycle
Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity...
Definition: iew.hh:365
gem5::o3::InstructionQueue::replayMemInst
void replayMemInst(const DynInstPtr &replay_inst)
Replays a memory instruction.
Definition: inst_queue.cc:1101
gem5::o3::IEW::numThreads
ThreadID numThreads
Number of active threads.
Definition: iew.hh:409
gem5::o3::IEW::IEWStats::ExecutedInstStats::numSwp
statistics::Vector numSwp
Number of executed software prefetches.
Definition: iew.hh:466
gem5::o3::IEW::IEWStats::IEWStats
IEWStats(CPU *cpu)
Definition: iew.cc:145
gem5::o3::IEW::squashDueToMemOrder
void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a memory order violation.
Definition: iew.cc:478
gem5::o3::LSQ::getDataPort
RequestPort & getDataPort()
Definition: lsq.hh:892
gem5::o3::LSQ::takeOverFrom
void takeOverFrom()
Takes over execution from another CPU's thread.
Definition: lsq.cc:164
gem5::o3::LSQ::commitStores
void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
Commits stores up until the given sequence number for a specific thread.
Definition: lsq.cc:259
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:358
gem5::o3::InstructionQueue::scheduleReadyInsts
void scheduleReadyInsts()
Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute.
Definition: inst_queue.cc:751
gem5::o3::IEW::ldstQueue
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:358
std::list< ThreadID >
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::o3::IEW::setIEWQueue
void setIEWQueue(TimeBuffer< IEWStruct > *iq_ptr)
Sets time buffer to pass on instructions to commit.
Definition: iew.cc:331
limits.hh
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1040
gem5::o3::LSQ::lqFull
bool lqFull()
Returns if any of the LQs are full.
Definition: lsq.cc:635
gem5::o3::IEW::dispatch
void dispatch(ThreadID tid)
Determines proper actions to take given Dispatch's status.
Definition: iew.cc:831
gem5::o3::LSQ::numHtmStops
int numHtmStops(ThreadID tid) const
Definition: lsq.cc:352
gem5::o3::IEW::updatedQueues
bool updatedQueues
Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast th...
Definition: iew.hh:374
gem5::o3::IEW::issueToExecuteDelay
Cycles issueToExecuteDelay
Issue to execute delay.
Definition: iew.hh:387
gem5::o3::IEW::Idle
@ Idle
Definition: iew.hh:104
gem5::o3::LSQ::executeLoad
Fault executeLoad(const DynInstPtr &inst)
Executes a load.
Definition: lsq.cc:237
gem5::o3::IEW::IEWStats::ExecutedInstStats::numBranches
statistics::Vector numBranches
Number of executed branches.
Definition: iew.hh:472
gem5::o3::IEW::activateStage
void activateStage()
Tells CPU that the IEW stage is active and running.
Definition: iew.cc:817
gem5::o3::IEW::IEWStats::ExecutedInstStats::numRate
statistics::Formula numRate
Number of instructions executed per cycle.
Definition: iew.hh:476
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
gem5::o3::IEW::name
std::string name() const
Returns the name of the IEW stage.
Definition: iew.cc:119
gem5::o3::InstructionQueue::violation
void violation(const DynInstPtr &store, const DynInstPtr &faulting_load)
Indicates an ordering violation between a store and a load.
Definition: inst_queue.cc:1160
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::o3::IEW::setScoreboard
void setScoreboard(Scoreboard *sb_ptr)
Sets pointer to the scoreboard.
Definition: iew.cc:349
gem5::o3::IEW::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition: iew.cc:340
gem5::o3::InstructionQueue::hasReadyInsts
bool hasReadyInsts()
Returns if there are any ready instructions in the IQ.
Definition: inst_queue.cc:546
gem5::o3::IEW::executeInsts
void executeInsts()
Executes instructions.
Definition: iew.cc:1136
gem5::o3::IEW::regProbePoints
void regProbePoints()
Registers probes.
Definition: iew.cc:125
gem5::o3::InstructionQueue::getCount
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
Definition: inst_queue.hh:275

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