55 #include "debug/Activity.hh"
56 #include "debug/Drain.hh"
57 #include "debug/IEW.hh"
58 #include "debug/O3PipeView.hh"
59 #include "params/BaseO3CPU.hh"
68 : issueToExecQueue(params.backComSize, params.forwardComSize),
70 instQueue(_cpu, this, params),
71 ldstQueue(_cpu, this, params),
72 fuPool(params.fuPool),
73 commitToIEWDelay(params.commitToIEWDelay),
74 renameToIEWDelay(params.renameToIEWDelay),
75 issueToExecuteDelay(params.issueToExecuteDelay),
76 dispatchWidth(params.dispatchWidth),
77 issueWidth(params.issueWidth),
80 wbWidth(params.wbWidth),
81 numThreads(params.numThreads),
85 fatal(
"dispatchWidth (%d) is larger than compiled limit (%d),\n"
86 "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
89 fatal(
"issueWidth (%d) is larger than compiled limit (%d),\n"
90 "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
93 fatal(
"wbWidth (%d) is larger than compiled limit (%d),\n"
94 "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
145 : statistics::
Group(cpu,
"iew"),
146 ADD_STAT(idleCycles, statistics::units::Cycle::get(),
147 "Number of cycles IEW is idle"),
148 ADD_STAT(squashCycles, statistics::units::Cycle::get(),
149 "Number of cycles IEW is squashing"),
150 ADD_STAT(blockCycles, statistics::units::Cycle::get(),
151 "Number of cycles IEW is blocking"),
152 ADD_STAT(unblockCycles, statistics::units::Cycle::get(),
153 "Number of cycles IEW is unblocking"),
155 "Number of instructions dispatched to IQ"),
157 "Number of squashed instructions skipped by dispatch"),
159 "Number of dispatched load instructions"),
161 "Number of dispatched store instructions"),
163 "Number of dispatched non-speculative instructions"),
165 "Number of times the IQ has become full, causing a stall"),
167 "Number of times the LSQ has become full, causing a stall"),
168 ADD_STAT(memOrderViolationEvents, statistics::units::
Count::get(),
169 "Number of memory order violations"),
170 ADD_STAT(predictedTakenIncorrect, statistics::units::
Count::get(),
171 "Number of branches that were predicted taken incorrectly"),
172 ADD_STAT(predictedNotTakenIncorrect, statistics::units::
Count::get(),
173 "Number of branches that were predicted not taken incorrectly"),
175 "Number of branch mispredicts detected at execute",
176 predictedTakenIncorrect + predictedNotTakenIncorrect),
177 executedInstStats(cpu),
179 "Cumulative count of insts sent to commit"),
181 "Cumulative count of insts written-back"),
183 "Number of instructions producing a value"),
185 "Number of instructions consuming a value"),
186 ADD_STAT(wbRate, statistics::units::Rate<
187 statistics::units::
Count, statistics::units::Cycle>::get(),
188 "Insts written-back per cycle"),
189 ADD_STAT(wbFanout, statistics::units::Rate<
190 statistics::units::
Count, statistics::units::
Count>::get(),
191 "Average fanout of values written-back")
221 "Number of executed instructions"),
223 "Number of load instructions executed"),
225 "Number of squashed instructions skipped in execute"),
227 "Number of swp insts executed"),
229 "Number of nop insts executed"),
231 "Number of memory reference insts executed"),
233 "Number of branches executed"),
235 "Number of stores executed"),
236 ADD_STAT(numRate, statistics::units::Rate<
237 statistics::units::
Count, statistics::units::Cycle>::get(),
238 "Inst execution rate", numInsts /
cpu->baseStats.numCycles)
272 toRename->iewInfo[tid].usedIQ =
true;
273 toRename->iewInfo[tid].freeIQEntries =
276 toRename->iewInfo[tid].usedLSQ =
true;
277 toRename->iewInfo[tid].freeLQEntries =
279 toRename->iewInfo[tid].freeSQEntries =
294 toRename->iewInfo[tid].usedIQ =
true;
295 toRename->iewInfo[tid].freeIQEntries =
298 toRename->iewInfo[tid].usedLSQ =
true;
359 if (!
insts[tid].empty()) {
360 DPRINTF(Drain,
"%i: Insts not empty.\n", tid);
364 DPRINTF(Drain,
"%i: Skid buffer not empty.\n", tid);
374 DPRINTF(Drain,
"FU pool still busy.\n");
420 DPRINTF(
IEW,
"[tid:%i] Squashing all instructions.\n", tid);
431 "Removing skidbuffer instructions until "
432 "[sn:%llu] [tid:%i]\n",
437 toRename->iewInfo[tid].dispatchedToLQ++;
441 toRename->iewInfo[tid].dispatchedToSQ++;
444 toRename->iewInfo[tid].dispatched++;
455 DPRINTF(
IEW,
"[tid:%i] [sn:%llu] Squashing from a specific instruction,"
457 "\n", tid, inst->seqNum, inst->pcState() );
460 inst->seqNum <
toCommit->squashedSeqNum[tid]) {
462 toCommit->squashedSeqNum[tid] = inst->seqNum;
463 toCommit->branchTaken[tid] = inst->pcState().branching();
466 inst->staticInst->advancePC(*
toCommit->pc[tid]);
468 toCommit->mispredictInst[tid] = inst;
469 toCommit->includeSquashInst[tid] =
false;
479 DPRINTF(
IEW,
"[tid:%i] Memory violation, squashing violator and younger "
480 "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum);
488 inst->seqNum <=
toCommit->squashedSeqNum[tid]) {
491 toCommit->squashedSeqNum[tid] = inst->seqNum;
493 toCommit->mispredictInst[tid] = NULL;
496 toCommit->includeSquashInst[tid] =
true;
523 DPRINTF(
IEW,
"[tid:%i] Reading instructions out of the skid "
524 "buffer %u.\n",tid, tid);
531 DPRINTF(
IEW,
"[tid:%i] Done unblocking.\n",tid);
587 DPRINTF(
IEW,
"Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
599 while (!
insts[tid].empty()) {
600 inst =
insts[tid].front();
604 DPRINTF(
IEW,
"[tid:%i] Inserting [sn:%lli] PC:%s into "
605 "dispatch skidBuffer %i\n",tid, inst->seqNum,
606 inst->pcState(),tid);
612 "Skidbuffer Exceeded Max Size");
623 while (threads != end) {
625 unsigned thread_count =
skidBuffer[tid].size();
626 if (max < thread_count)
639 while (threads != end) {
652 bool any_unblocking =
false;
657 while (threads != end) {
661 any_unblocking =
true;
694 if (
fromCommit->commitInfo[tid].robSquashing) {
695 DPRINTF(
IEW,
"[tid:%i] Stall from Commit stage detected.\n",tid);
698 DPRINTF(
IEW,
"[tid:%i] Stall: IQ is full.\n",tid);
729 if (
fromCommit->commitInfo[tid].robSquashing) {
730 DPRINTF(
IEW,
"[tid:%i] ROB is still squashing.\n", tid);
746 DPRINTF(
IEW,
"[tid:%i] Done blocking, switching to unblocking.\n",
759 DPRINTF(
IEW,
"[tid:%i] Done squashing, switching to running.\n",
774 assert(
insts[tid].empty());
776 for (
int i = 0;
i < insts_from_rename; ++
i) {
784 DPRINTF(
IEW,
"[tid:%i] Removing incoming rename instructions\n", tid);
786 while (!
insts[tid].empty()) {
788 if (
insts[tid].front()->isLoad()) {
789 toRename->iewInfo[tid].dispatchedToLQ++;
791 if (
insts[tid].front()->isStore() ||
792 insts[tid].front()->isAtomic()) {
793 toRename->iewInfo[tid].dispatchedToSQ++;
796 toRename->iewInfo[tid].dispatched++;
811 DPRINTF(Activity,
"Activity this cycle.\n");
818 DPRINTF(Activity,
"Activating stage.\n");
825 DPRINTF(Activity,
"Deactivating stage.\n");
850 DPRINTF(
IEW,
"[tid:%i] Not blocked, so attempting to run "
881 std::queue<DynInstPtr> &insts_to_dispatch =
885 int insts_to_add = insts_to_dispatch.size();
888 bool add_to_iq =
false;
889 int dis_num_inst = 0;
893 for ( ; dis_num_inst < insts_to_add &&
897 inst = insts_to_dispatch.front();
900 DPRINTF(
IEW,
"[tid:%i] Issue: Examining instruction from skid "
907 DPRINTF(
IEW,
"[tid:%i] Issue: Adding PC %s [sn:%lli] [tid:%i] to "
909 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
916 if (inst->isSquashed()) {
917 DPRINTF(
IEW,
"[tid:%i] Issue: Squashed instruction encountered, "
918 "not adding to IQ.\n", tid);
922 insts_to_dispatch.pop();
925 if (inst->isLoad()) {
926 toRename->iewInfo[tid].dispatchedToLQ++;
928 if (inst->isStore() || inst->isAtomic()) {
929 toRename->iewInfo[tid].dispatchedToSQ++;
932 toRename->iewInfo[tid].dispatched++;
939 DPRINTF(
IEW,
"[tid:%i] Issue: IQ has become full.\n", tid);
957 DPRINTF(
IEW,
"[tid:%i] Issue: %s has become full.\n",tid,
958 inst->isLoad() ?
"LQ" :
"SQ");
976 const int htmDepth = numHtmStarts - numHtmStops;
982 inst->clearHtmTransactionalState();
987 if (inst->isAtomic()) {
988 DPRINTF(
IEW,
"[tid:%i] Issue: Memory instruction "
989 "encountered, adding to LSQ.\n", tid);
998 inst->setCanCommit();
1004 toRename->iewInfo[tid].dispatchedToSQ++;
1005 }
else if (inst->isLoad()) {
1006 DPRINTF(
IEW,
"[tid:%i] Issue: Memory instruction "
1007 "encountered, adding to LSQ.\n", tid);
1017 toRename->iewInfo[tid].dispatchedToLQ++;
1018 }
else if (inst->isStore()) {
1019 DPRINTF(
IEW,
"[tid:%i] Issue: Memory instruction "
1020 "encountered, adding to LSQ.\n", tid);
1026 if (inst->isStoreConditional()) {
1031 inst->setCanCommit();
1040 toRename->iewInfo[tid].dispatchedToSQ++;
1041 }
else if (inst->isReadBarrier() || inst->isWriteBarrier()) {
1043 inst->setCanCommit();
1046 }
else if (inst->isNop()) {
1047 DPRINTF(
IEW,
"[tid:%i] Issue: Nop instruction encountered, "
1048 "skipping.\n", tid);
1051 inst->setExecuted();
1052 inst->setCanCommit();
1060 assert(!inst->isExecuted());
1064 if (add_to_iq && inst->isNonSpeculative()) {
1065 DPRINTF(
IEW,
"[tid:%i] Issue: Nonspeculative instruction "
1066 "encountered, skipping.\n", tid);
1069 inst->setCanCommit();
1085 insts_to_dispatch.pop();
1087 toRename->iewInfo[tid].dispatched++;
1092 inst->dispatchTick =
curTick() - inst->fetchTick;
1097 if (!insts_to_dispatch.empty()) {
1098 DPRINTF(
IEW,
"[tid:%i] Issue: Bandwidth Full. Blocking.\n", tid);
1117 std::cout <<
"Available Instructions: ";
1121 if (inst%3==0) std::cout <<
"\n\t";
1123 std::cout <<
"PC: " <<
fromIssue->insts[inst]->pcState()
1124 <<
" TN: " <<
fromIssue->insts[inst]->threadNumber
1125 <<
" SN: " <<
fromIssue->insts[inst]->seqNum <<
" | ";
1143 while (threads != end) {
1155 for (; inst_num < insts_to_execute;
1158 DPRINTF(
IEW,
"Execute: Executing instructions from IQ.\n");
1162 DPRINTF(
IEW,
"Execute: Processing PC %s, [tid:%i] [sn:%llu].\n",
1163 inst->pcState(), inst->threadNumber,inst->seqNum);
1170 if (inst->isSquashed()) {
1171 DPRINTF(
IEW,
"Execute: Instruction was squashed. PC: %s, [tid:%i]"
1172 " [sn:%llu]\n", inst->pcState(), inst->threadNumber,
1177 inst->setExecuted();
1181 inst->setCanCommit();
1193 if (inst->isMemRef()) {
1194 DPRINTF(
IEW,
"Execute: Calculating address for memory "
1198 if (inst->isAtomic()) {
1202 if (inst->isTranslationDelayed() &&
1206 DPRINTF(
IEW,
"Execute: Delayed translation, deferring "
1211 }
else if (inst->isLoad()) {
1216 if (inst->isTranslationDelayed() &&
1220 DPRINTF(
IEW,
"Execute: Delayed translation, deferring "
1226 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1229 }
else if (inst->isStore()) {
1232 if (inst->isTranslationDelayed() &&
1236 DPRINTF(
IEW,
"Execute: Delayed translation, deferring "
1243 if (fault !=
NoFault || !inst->readPredicate() ||
1244 !inst->isStoreConditional()) {
1249 inst->setExecuted();
1258 panic(
"Unexpected memory type!\n");
1266 if (inst->getFault() ==
NoFault) {
1268 if (!inst->readPredicate())
1269 inst->forwardOldRegs();
1272 inst->setExecuted();
1291 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1295 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1297 if (inst->mispredicted() && !loadNotExecuted) {
1301 "Branch mispredict detected.\n",
1304 "Predicted target was PC: %s\n",
1305 tid, inst->seqNum, inst->readPredTarg());
1307 "Redirecting fetch to PC: %s\n",
1308 tid, inst->seqNum, inst->pcState());
1314 if (inst->readPredTaken()) {
1320 assert(inst->isMemRef());
1327 DPRINTF(
IEW,
"LDSTQ detected a violation. Violator PC: %s "
1328 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1329 violator->pcState(), violator->seqNum,
1330 inst->pcState(), inst->seqNum, inst->physEffAddr);
1346 assert(inst->isMemRef());
1350 DPRINTF(
IEW,
"LDSTQ detected a violation. Violator PC: "
1351 "%s, inst PC: %s. Addr is: %#x.\n",
1352 violator->pcState(), inst->pcState(),
1354 DPRINTF(
IEW,
"Violation will not be handled because "
1355 "already squashing\n");
1388 for (
int inst_num = 0; inst_num <
wbWidth &&
1389 toCommit->insts[inst_num]; inst_num++) {
1393 DPRINTF(
IEW,
"Sending instructions to commit, [sn:%lli] PC %s.\n",
1394 inst->seqNum, inst->pcState());
1406 if (!inst->isSquashed() && inst->isExecuted() &&
1407 inst->getFault() ==
NoFault) {
1410 for (
int i = 0;
i < inst->numDestRegs();
i++) {
1412 if (inst->renamedDestIdx(
i)->
1413 getNumPinnedWritesToComplete() == 0) {
1414 DPRINTF(
IEW,
"Setting Destination Register %i (%s)\n",
1415 inst->renamedDestIdx(
i)->index(),
1416 inst->renamedDestIdx(
i)->className());
1450 while (threads != end) {
1453 DPRINTF(
IEW,
"Issue: Processing [tid:%i]\n",tid);
1474 bool broadcast_free_entries =
false;
1480 broadcast_free_entries =
true;
1492 while (threads != end) {
1498 if (
fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1510 if (
fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1513 if (
fromCommit->commitInfo[tid].strictlyOrdered) {
1515 fromCommit->commitInfo[tid].strictlyOrderedLoad);
1516 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit();
1523 if (broadcast_free_entries) {
1524 toFetch->iewInfo[tid].iqCount =
1526 toFetch->iewInfo[tid].ldstqCount =
1529 toRename->iewInfo[tid].usedIQ =
true;
1530 toRename->iewInfo[tid].freeIQEntries =
1532 toRename->iewInfo[tid].usedLSQ =
true;
1534 toRename->iewInfo[tid].freeLQEntries =
1536 toRename->iewInfo[tid].freeSQEntries =
1542 DPRINTF(
IEW,
"[tid:%i], Dispatch dispatched %i instructions.\n",
1543 tid,
toRename->iewInfo[tid].dispatched);
1546 DPRINTF(
IEW,
"IQ has %i free entries (Can schedule: %i). "
1547 "LQ has %i free entries. SQ has %i free entries.\n",
1554 DPRINTF(Activity,
"Activity this cycle.\n");
1567 if (debug::O3PipeView) {
1568 inst->completeTick =
curTick() - inst->fetchTick;
1575 if (inst->isControl())
1581 if (inst->isMemRef()) {
1584 if (inst->isLoad()) {
1597 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1599 if (inst->mispredicted()) {
1603 "Branch mispredict detected.\n",
1605 DPRINTF(
IEW,
"[tid:%i] [sn:%llu] Predicted target was PC: %s\n",
1606 tid, inst->seqNum, inst->readPredTarg());
1608 "Redirecting fetch to PC: %s\n",
1609 tid, inst->seqNum, inst->pcState());
1613 if (inst->readPredTaken()) {
gem5::BaseCPU::BaseCPUStats baseStats
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
virtual std::string name() const
ProbePointArg generates a point for the class of Arg.
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
void activityThisCycle()
Records that there was time buffer activity this cycle.
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
void processFreeUnits()
Frees all FUs on the list.
bool isDrained() const
Have all the FUs drained?
void takeOverFrom()
Takes over from another CPU's thread.
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
void printAvailableInsts()
Debug function to print instructions that are issued this cycle.
void updateStatus()
Updates overall IEW status based on all of the stages' statuses.
void deactivateStage()
Tells CPU that the IEW stage is inactive and idle.
TimeBuffer< IEWStruct > * iewQueue
IEW stage time buffer.
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's output from backwards time buffer.
StageStatus dispatchStatus[MaxThreads]
Dispatch status.
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
void takeOverFrom()
Takes over from another CPU's thread.
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets main time buffer used for backwards communication.
int skidCount()
Returns the max of the number of entries in all of the skid buffers.
void instToCommit(const DynInstPtr &inst)
Sends an instruction to commit through the time buffer.
FUPool * fuPool
Pointer to the functional unit pool.
void squashDueToBranch(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a branch mispredict.
void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a memory order violation.
unsigned wbWidth
Writeback width.
std::queue< DynInstPtr > insts[MaxThreads]
Queue of all instructions coming from rename this cycle.
void block(ThreadID tid)
Sets Dispatch to blocked, and signals back to other stages to block.
StageStatus exeStatus
Execute status.
void clearStates(ThreadID tid)
Clear all thread-specific states.
void dispatch(ThreadID tid)
Determines proper actions to take given Dispatch's status.
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
void blockMemInst(const DynInstPtr &inst)
Moves memory instruction onto the list of cache blocked instructions.
void unblock(ThreadID tid)
Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock.
void sortInsts()
Sorts instructions coming from rename into lists separated by thread.
void wakeDependents(const DynInstPtr &inst)
Wakes all dependents of a completed instruction.
unsigned issueWidth
Width of issue, in instructions.
void updateExeInstStats(const DynInstPtr &inst)
Updates execution stats based on the instruction.
void dispatchInsts(ThreadID tid)
Dispatches instructions to IQ and LSQ.
void drainSanityCheck() const
Perform sanity checks after a drain.
TimeBuffer< IssueStruct > issueToExecQueue
Issue stage queue.
void checkSignalsAndUpdate(ThreadID tid)
Processes inputs and changes state accordingly.
void activateStage()
Tells CPU that the IEW stage is active and running.
TimeBuffer< TimeStruct >::wire toRename
Wire to write information heading to previous stages.
bool wroteToTimeBuffer
Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if th...
void activityThisCycle()
Reports to the CPU that there is activity this cycle.
void setScoreboard(Scoreboard *sb_ptr)
Sets pointer to the scoreboard.
Scoreboard * scoreboard
Scoreboard pointer.
std::queue< DynInstPtr > skidBuffer[MaxThreads]
Skid buffer between rename and IEW.
TimeBuffer< IssueStruct >::wire fromIssue
Wire to read information from the issue stage time queue.
Cycles renameToIEWDelay
Rename to IEW delay.
TimeBuffer< TimeStruct > * timeBuffer
Pointer to main time buffer used for backwards communication.
void writebackInsts()
Writebacks instructions.
void wakeCPU()
Tells the CPU to wakeup if it has descheduled itself due to no activity.
void squash(ThreadID tid)
Squashes instructions in IEW for a specific thread.
void setIEWQueue(TimeBuffer< IEWStruct > *iq_ptr)
Sets time buffer to pass on instructions to commit.
ProbePointArg< DynInstPtr > * ppExecute
To probe when instruction execution begins.
void rescheduleMemInst(const DynInstPtr &inst)
Tells memory dependence unit that a memory instruction needs to be rescheduled.
ThreadID numThreads
Number of active threads.
unsigned skidBufferMax
Maximum size of the skid buffer.
Status _status
Overall stage status.
TimeBuffer< RenameStruct >::wire fromRename
Wire to get rename's output from rename queue.
ProbePointArg< DynInstPtr > * ppMispredict
Probe points.
TimeBuffer< TimeStruct >::wire toFetch
Wire to write information heading to previous stages.
gem5::o3::IEW::IEWStats iewStats
bool isDrained() const
Has the stage drained?
InstructionQueue instQueue
Instruction queue.
bool fetchRedirect[MaxThreads]
Records if there is a fetch redirect on this cycle for each thread.
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue interface.
IEW(CPU *_cpu, const BaseO3CPUParams ¶ms)
Constructs a IEW with the given parameters.
unsigned dispatchWidth
Width of dispatch, in instructions.
ProbePointArg< DynInstPtr > * ppDispatch
std::string name() const
Returns the name of the IEW stage.
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle.
ProbePointArg< DynInstPtr > * ppToCommit
To probe when instruction execution is complete.
bool updatedQueues
Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast th...
void checkMisprediction(const DynInstPtr &inst)
Check misprediction
LSQ ldstQueue
Load / store queue.
Cycles issueToExecuteDelay
Issue to execute delay.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
bool skidsEmpty()
Returns if all of the skid buffers are empty.
bool updateLSQNextCycle
Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity...
void emptyRenameInsts(ThreadID tid)
Removes instructions from rename from a thread's instruction list.
void replayMemInst(const DynInstPtr &inst)
Re-executes all rescheduled memory instructions.
Cycles commitToIEWDelay
Commit to IEW delay.
unsigned wbCycle
Cycle number within the queue of instructions being written back.
void skidInsert(ThreadID tid)
Inserts unused instructions of a thread into the skid buffer.
void cacheUnblocked()
Notifies that the cache has become unblocked.
TimeBuffer< IEWStruct >::wire toCommit
Wire to write infromation heading to commit.
void regProbePoints()
Registers probes.
bool checkStall(ThreadID tid)
Checks if any of the stall conditions are currently true.
void executeInsts()
Executes instructions.
unsigned wbNumInst
Index into queue of instructions being written back.
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets time buffer for getting instructions coming from rename.
StageStatus wbStatus
Writeback status.
void commit(const InstSeqNum &inst, ThreadID tid=0)
Commits all instructions up to and including the given sequence number, for a specific thread.
void deferMemInst(const DynInstPtr &deferred_inst)
Defers a memory instruction when its DTB translation incurs a hw page table walk.
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly.
int wakeDependents(const DynInstPtr &completed_inst)
Wakes all dependents of a completed instruction.
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the global time buffer.
unsigned numFreeEntries()
Returns total number of free entries.
void rescheduleMemInst(const DynInstPtr &resched_inst)
Reschedules a memory instruction.
void insertNonSpec(const DynInstPtr &new_inst)
Inserts a new, non-speculative instruction into the IQ.
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
void replayMemInst(const DynInstPtr &replay_inst)
Replays a memory instruction.
void recordProducer(const DynInstPtr &inst)
Records the instruction as the producer of a register without adding it to the rest of the IQ.
bool isDrained() const
Determine if we are drained.
void cacheUnblocked()
Notify instruction queue that a previous blockage has resolved.
void blockMemInst(const DynInstPtr &blocked_inst)
Defers a memory instruction when it is cache blocked.
void drainSanityCheck() const
Perform sanity checks after a drain.
void takeOverFrom()
Takes over execution from another CPU's thread.
gem5::o3::InstructionQueue::IQIOStats iqIOStats
void violation(const DynInstPtr &store, const DynInstPtr &faulting_load)
Indicates an ordering violation between a store and a load.
bool hasReadyInsts()
Returns if there are any ready instructions in the IQ.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets active threads list.
void scheduleNonSpec(const InstSeqNum &inst)
Schedules a single specific non-speculative instruction.
void scheduleReadyInsts()
Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute.
bool isFull()
Returns whether or not the IQ is full.
void squash(ThreadID tid)
Squashes instructions for a thread.
void setIssueToExecuteQueue(TimeBuffer< IssueStruct > *i2eQueue)
Sets the timer buffer between issue and execute.
void insert(const DynInstPtr &new_inst)
Inserts a new instruction into the IQ.
DynInstPtr getInstToExecute()
Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to exe...
bool isDrained() const
Has the LSQ drained?
int numHtmStarts(ThreadID tid) const
void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
Commits stores up until the given sequence number for a specific thread.
RequestPort & getDataPort()
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squash instructions from a thread until the specified sequence number.
unsigned numFreeLoadEntries()
Returns the number of free load entries.
void takeOverFrom()
Takes over execution from another CPU's thread.
DynInstPtr getMemDepViolator(ThreadID tid)
Gets the instruction that caused the memory ordering violation.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets the pointer to the list of active threads.
void insertStore(const DynInstPtr &store_inst)
Inserts a store into the LSQ.
void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
Commits loads up until the given sequence number for a specific thread.
uint64_t getLatestHtmUid(ThreadID tid) const
bool willWB()
Returns if the LSQ will write back to memory this cycle.
void drainSanityCheck() const
Perform sanity checks after a drain.
int numHtmStops(ThreadID tid) const
void writebackStores()
Attempts to write back stores until all cache ports are used or the interface becomes blocked.
bool lqFull()
Returns if any of the LQs are full.
int getCount()
Returns the number of instructions in all of the queues.
Fault executeStore(const DynInstPtr &inst)
Executes a store.
void tick()
Ticks the LSQ.
void insertLoad(const DynInstPtr &load_inst)
Inserts a load into the LSQ.
Fault executeLoad(const DynInstPtr &inst)
Executes a load.
bool violation()
Returns whether or not there was a memory ordering violation.
unsigned numFreeStoreEntries()
Returns the number of free store entries.
bool sqFull()
Returns if any of the SQs are full.
Implements a simple scoreboard to track which registers are ready.
void setReg(PhysRegIdPtr phys_reg)
Sets the register as ready.
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Derived & init(size_type size)
Set this vector to have the given size.
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
#define panic(...)
This implements a cprintf based panic() function.
#define fatal(...)
This implements a cprintf based fatal() function.
ProbeManager * getProbeManager()
Get the probe manager for this object.
static constexpr int MaxThreads
static constexpr int MaxWidth
const FlagsType total
Print the total.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
int16_t ThreadID
Thread index/ID type.
Tick curTick()
The universal simulation clock.
constexpr decltype(nullptr) NoFault
statistics::Scalar numCycles
statistics::Formula numStoreInsts
Number of executed store instructions.
statistics::Vector numLoadInsts
Stat for total number of executed load instructions.
statistics::Vector numSwp
Number of executed software prefetches.
statistics::Vector numBranches
Number of executed branches.
statistics::Scalar numInsts
Stat for total number of executed instructions.
statistics::Vector numRefs
Number of executed meomory references.
statistics::Scalar numSquashedInsts
Stat for total number of squashed instructions skipped at execute.
statistics::Vector numNop
Number of executed nops.
statistics::Formula numRate
Number of instructions executed per cycle.
ExecutedInstStats(CPU *cpu)
statistics::Scalar dispatchedInsts
Stat for total number of instructions dispatched.
statistics::Formula wbFanout
Average number of woken instructions per writeback.
statistics::Scalar squashCycles
Stat for total number of squashing cycles.
statistics::Vector consumerInst
Number of instructions that wake up from producers.
statistics::Scalar predictedNotTakenIncorrect
Stat for total number of incorrect predicted not taken branches.
statistics::Scalar dispLoadInsts
Stat for total number of dispatched load instructions.
statistics::Scalar dispNonSpecInsts
Stat for total number of dispatched non speculative insts.
statistics::Vector instsToCommit
Number of instructions sent to commit.
gem5::o3::IEW::IEWStats::ExecutedInstStats executedInstStats
statistics::Formula wbRate
Number of instructions per cycle written back.
statistics::Scalar dispSquashedInsts
Stat for total number of squashed instructions dispatch skips.
statistics::Scalar predictedTakenIncorrect
Stat for total number of incorrect predicted taken branches.
statistics::Scalar blockCycles
Stat for total number of blocking cycles.
statistics::Vector writebackCount
Number of instructions that writeback.
statistics::Scalar memOrderViolationEvents
Stat for total number of memory ordering violation events.
statistics::Vector producerInst
Number of instructions that wake consumers.
statistics::Scalar iqFullEvents
Stat for number of times the IQ becomes full.
statistics::Scalar unblockCycles
Stat for total number of unblocking cycles.
statistics::Scalar lsqFullEvents
Stat for number of times the LSQ becomes full.
statistics::Scalar dispStoreInsts
Stat for total number of dispatched store instructions.
statistics::Scalar intInstQueueReads