gem5  v21.1.0.2
inst_queue.cc
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41 
42 #include "cpu/o3/inst_queue.hh"
43 
44 #include <limits>
45 #include <vector>
46 
47 #include "base/logging.hh"
48 #include "cpu/o3/dyn_inst.hh"
49 #include "cpu/o3/fu_pool.hh"
50 #include "cpu/o3/limits.hh"
51 #include "debug/IQ.hh"
52 #include "enums/OpClass.hh"
53 #include "params/O3CPU.hh"
54 #include "sim/core.hh"
55 
56 // clang complains about std::set being overloaded with Packet::set if
57 // we open up the entire namespace std
58 using std::list;
59 
60 namespace gem5
61 {
62 
63 namespace o3
64 {
65 
67  int fu_idx, InstructionQueue *iq_ptr)
68  : Event(Stat_Event_Pri, AutoDelete),
69  inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
70 {
71 }
72 
73 void
75 {
76  iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
77  inst = NULL;
78 }
79 
80 
81 const char *
83 {
84  return "Functional unit completion";
85 }
86 
88  const O3CPUParams &params)
89  : cpu(cpu_ptr),
90  iewStage(iew_ptr),
91  fuPool(params.fuPool),
92  iqPolicy(params.smtIQPolicy),
93  numThreads(params.numThreads),
94  numEntries(params.numIQEntries),
95  totalWidth(params.issueWidth),
98  iqIOStats(cpu)
99 {
100  assert(fuPool);
101 
102  // Set the number of total physical registers
103  // As the vector registers have two addressing modes, they are added twice
104  numPhysRegs = params.numPhysIntRegs + params.numPhysFloatRegs +
105  params.numPhysVecRegs +
106  params.numPhysVecRegs * TheISA::NumVecElemPerVecReg +
107  params.numPhysVecPredRegs +
108  params.numPhysCCRegs;
109 
110  //Create an entry for each physical register within the
111  //dependency graph.
112  dependGraph.resize(numPhysRegs);
113 
114  // Resize the register scoreboard.
115  regScoreboard.resize(numPhysRegs);
116 
117  //Initialize Mem Dependence Units
118  for (ThreadID tid = 0; tid < MaxThreads; tid++) {
119  memDepUnit[tid].init(params, tid, cpu_ptr);
120  memDepUnit[tid].setIQ(this);
121  }
122 
123  resetState();
124 
125  //Figure out resource sharing policy
126  if (iqPolicy == SMTQueuePolicy::Dynamic) {
127  //Set Max Entries to Total ROB Capacity
128  for (ThreadID tid = 0; tid < numThreads; tid++) {
129  maxEntries[tid] = numEntries;
130  }
131 
132  } else if (iqPolicy == SMTQueuePolicy::Partitioned) {
133  //@todo:make work if part_amt doesnt divide evenly.
134  int part_amt = numEntries / numThreads;
135 
136  //Divide ROB up evenly
137  for (ThreadID tid = 0; tid < numThreads; tid++) {
138  maxEntries[tid] = part_amt;
139  }
140 
141  DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
142  "%i entries per thread.\n",part_amt);
143  } else if (iqPolicy == SMTQueuePolicy::Threshold) {
144  double threshold = (double)params.smtIQThreshold / 100;
145 
146  int thresholdIQ = (int)((double)threshold * numEntries);
147 
148  //Divide up by threshold amount
149  for (ThreadID tid = 0; tid < numThreads; tid++) {
150  maxEntries[tid] = thresholdIQ;
151  }
152 
153  DPRINTF(IQ, "IQ sharing policy set to Threshold:"
154  "%i entries per thread.\n",thresholdIQ);
155  }
156  for (ThreadID tid = numThreads; tid < MaxThreads; tid++) {
157  maxEntries[tid] = 0;
158  }
159 }
160 
162 {
163  dependGraph.reset();
164 #ifdef DEBUG
165  cprintf("Nodes traversed: %i, removed: %i\n",
166  dependGraph.nodesTraversed, dependGraph.nodesRemoved);
167 #endif
168 }
169 
170 std::string
172 {
173  return cpu->name() + ".iq";
174 }
175 
176 InstructionQueue::IQStats::IQStats(CPU *cpu, const unsigned &total_width)
177  : statistics::Group(cpu),
178  ADD_STAT(instsAdded, statistics::units::Count::get(),
179  "Number of instructions added to the IQ (excludes non-spec)"),
180  ADD_STAT(nonSpecInstsAdded, statistics::units::Count::get(),
181  "Number of non-speculative instructions added to the IQ"),
182  ADD_STAT(instsIssued, statistics::units::Count::get(),
183  "Number of instructions issued"),
184  ADD_STAT(intInstsIssued, statistics::units::Count::get(),
185  "Number of integer instructions issued"),
186  ADD_STAT(floatInstsIssued, statistics::units::Count::get(),
187  "Number of float instructions issued"),
188  ADD_STAT(branchInstsIssued, statistics::units::Count::get(),
189  "Number of branch instructions issued"),
190  ADD_STAT(memInstsIssued, statistics::units::Count::get(),
191  "Number of memory instructions issued"),
192  ADD_STAT(miscInstsIssued, statistics::units::Count::get(),
193  "Number of miscellaneous instructions issued"),
194  ADD_STAT(squashedInstsIssued, statistics::units::Count::get(),
195  "Number of squashed instructions issued"),
196  ADD_STAT(squashedInstsExamined, statistics::units::Count::get(),
197  "Number of squashed instructions iterated over during squash; "
198  "mainly for profiling"),
199  ADD_STAT(squashedOperandsExamined, statistics::units::Count::get(),
200  "Number of squashed operands that are examined and possibly "
201  "removed from graph"),
202  ADD_STAT(squashedNonSpecRemoved, statistics::units::Count::get(),
203  "Number of squashed non-spec instructions that were removed"),
204  ADD_STAT(numIssuedDist, statistics::units::Count::get(),
205  "Number of insts issued each cycle"),
206  ADD_STAT(statFuBusy, statistics::units::Count::get(),
207  "attempts to use FU when none available"),
208  ADD_STAT(statIssuedInstType, statistics::units::Count::get(),
209  "Number of instructions issued per FU type, per thread"),
210  ADD_STAT(issueRate, statistics::units::Rate<
211  statistics::units::Count, statistics::units::Cycle>::get(),
212  "Inst issue rate", instsIssued / cpu->baseStats.numCycles),
213  ADD_STAT(fuBusy, statistics::units::Count::get(), "FU busy when requested"),
214  ADD_STAT(fuBusyRate, statistics::units::Rate<
215  statistics::units::Count, statistics::units::Count>::get(),
216  "FU busy rate (busy events/executed inst)")
217 {
218  instsAdded
219  .prereq(instsAdded);
220 
223 
226 
229 
232 
235 
238 
241 
244 
247 
250 
253 /*
254  queueResDist
255  .init(Num_OpClasses, 0, 99, 2)
256  .name(name() + ".IQ:residence:")
257  .desc("cycles from dispatch to issue")
258  .flags(total | pdf | cdf )
259  ;
260  for (int i = 0; i < Num_OpClasses; ++i) {
261  queueResDist.subname(i, opClassStrings[i]);
262  }
263 */
265  .init(0,total_width,1)
267  ;
268 /*
269  dist_unissued
270  .init(Num_OpClasses+2)
271  .name(name() + ".unissued_cause")
272  .desc("Reason ready instruction not issued")
273  .flags(pdf | dist)
274  ;
275  for (int i=0; i < (Num_OpClasses + 2); ++i) {
276  dist_unissued.subname(i, unissued_names[i]);
277  }
278 */
280  .init(cpu->numThreads,enums::Num_OpClass)
282  ;
283  statIssuedInstType.ysubnames(enums::OpClassStrings);
284 
285  //
286  // How long did instructions for a particular FU type wait prior to issue
287  //
288 /*
289  issueDelayDist
290  .init(Num_OpClasses,0,99,2)
291  .name(name() + ".")
292  .desc("cycles from operands ready to issue")
293  .flags(pdf | cdf)
294  ;
295  for (int i=0; i<Num_OpClasses; ++i) {
296  std::stringstream subname;
297  subname << opClassStrings[i] << "_delay";
298  issueDelayDist.subname(i, subname.str());
299  }
300 */
301  issueRate
303  ;
304 
305  statFuBusy
308  ;
309  for (int i=0; i < Num_OpClasses; ++i) {
310  statFuBusy.subname(i, enums::OpClassStrings[i]);
311  }
312 
313  fuBusy
314  .init(cpu->numThreads)
316  ;
317 
318  fuBusyRate
320  ;
322 }
323 
325  : statistics::Group(parent),
326  ADD_STAT(intInstQueueReads, statistics::units::Count::get(),
327  "Number of integer instruction queue reads"),
328  ADD_STAT(intInstQueueWrites, statistics::units::Count::get(),
329  "Number of integer instruction queue writes"),
330  ADD_STAT(intInstQueueWakeupAccesses, statistics::units::Count::get(),
331  "Number of integer instruction queue wakeup accesses"),
332  ADD_STAT(fpInstQueueReads, statistics::units::Count::get(),
333  "Number of floating instruction queue reads"),
334  ADD_STAT(fpInstQueueWrites, statistics::units::Count::get(),
335  "Number of floating instruction queue writes"),
336  ADD_STAT(fpInstQueueWakeupAccesses, statistics::units::Count::get(),
337  "Number of floating instruction queue wakeup accesses"),
338  ADD_STAT(vecInstQueueReads, statistics::units::Count::get(),
339  "Number of vector instruction queue reads"),
340  ADD_STAT(vecInstQueueWrites, statistics::units::Count::get(),
341  "Number of vector instruction queue writes"),
342  ADD_STAT(vecInstQueueWakeupAccesses, statistics::units::Count::get(),
343  "Number of vector instruction queue wakeup accesses"),
344  ADD_STAT(intAluAccesses, statistics::units::Count::get(),
345  "Number of integer alu accesses"),
346  ADD_STAT(fpAluAccesses, statistics::units::Count::get(),
347  "Number of floating point alu accesses"),
348  ADD_STAT(vecAluAccesses, statistics::units::Count::get(),
349  "Number of vector alu accesses")
350 {
351  using namespace statistics;
353  .flags(total);
354 
356  .flags(total);
357 
359  .flags(total);
360 
362  .flags(total);
363 
365  .flags(total);
366 
368  .flags(total);
369 
371  .flags(total);
372 
374  .flags(total);
375 
377  .flags(total);
378 
380  .flags(total);
381 
383  .flags(total);
384 
386  .flags(total);
387 }
388 
389 void
391 {
392  //Initialize thread IQ counts
393  for (ThreadID tid = 0; tid < MaxThreads; tid++) {
394  count[tid] = 0;
395  instList[tid].clear();
396  }
397 
398  // Initialize the number of free IQ entries.
400 
401  // Note that in actuality, the registers corresponding to the logical
402  // registers start off as ready. However this doesn't matter for the
403  // IQ as the instruction should have been correctly told if those
404  // registers are ready in rename. Thus it can all be initialized as
405  // unready.
406  for (int i = 0; i < numPhysRegs; ++i) {
407  regScoreboard[i] = false;
408  }
409 
410  for (ThreadID tid = 0; tid < MaxThreads; ++tid) {
411  squashedSeqNum[tid] = 0;
412  }
413 
414  for (int i = 0; i < Num_OpClasses; ++i) {
415  while (!readyInsts[i].empty())
416  readyInsts[i].pop();
417  queueOnList[i] = false;
418  readyIt[i] = listOrder.end();
419  }
420  nonSpecInsts.clear();
421  listOrder.clear();
422  deferredMemInsts.clear();
423  blockedMemInsts.clear();
424  retryMemInsts.clear();
425  wbOutstanding = 0;
426 }
427 
428 void
430 {
431  activeThreads = at_ptr;
432 }
433 
434 void
436 {
437  issueToExecuteQueue = i2e_ptr;
438 }
439 
440 void
442 {
443  timeBuffer = tb_ptr;
444 
446 }
447 
448 bool
450 {
451  bool drained = dependGraph.empty() &&
452  instsToExecute.empty() &&
453  wbOutstanding == 0;
454  for (ThreadID tid = 0; tid < numThreads; ++tid)
455  drained = drained && memDepUnit[tid].isDrained();
456 
457  return drained;
458 }
459 
460 void
462 {
463  assert(dependGraph.empty());
464  assert(instsToExecute.empty());
465  for (ThreadID tid = 0; tid < numThreads; ++tid)
467 }
468 
469 void
471 {
472  resetState();
473 }
474 
475 int
477 {
478  if (iqPolicy == SMTQueuePolicy::Partitioned) {
479  return numEntries / num_threads;
480  } else {
481  return 0;
482  }
483 }
484 
485 
486 void
488 {
489  if (iqPolicy != SMTQueuePolicy::Dynamic || numThreads > 1) {
490  int active_threads = activeThreads->size();
491 
492  list<ThreadID>::iterator threads = activeThreads->begin();
494 
495  while (threads != end) {
496  ThreadID tid = *threads++;
497 
498  if (iqPolicy == SMTQueuePolicy::Partitioned) {
499  maxEntries[tid] = numEntries / active_threads;
500  } else if (iqPolicy == SMTQueuePolicy::Threshold &&
501  active_threads == 1) {
502  maxEntries[tid] = numEntries;
503  }
504  }
505  }
506 }
507 
508 unsigned
510 {
511  return freeEntries;
512 }
513 
514 unsigned
516 {
517  return maxEntries[tid] - count[tid];
518 }
519 
520 // Might want to do something more complex if it knows how many instructions
521 // will be issued this cycle.
522 bool
524 {
525  if (freeEntries == 0) {
526  return(true);
527  } else {
528  return(false);
529  }
530 }
531 
532 bool
534 {
535  if (numFreeEntries(tid) == 0) {
536  return(true);
537  } else {
538  return(false);
539  }
540 }
541 
542 bool
544 {
545  if (!listOrder.empty()) {
546  return true;
547  }
548 
549  for (int i = 0; i < Num_OpClasses; ++i) {
550  if (!readyInsts[i].empty()) {
551  return true;
552  }
553  }
554 
555  return false;
556 }
557 
558 void
560 {
561  if (new_inst->isFloating()) {
563  } else if (new_inst->isVector()) {
565  } else {
567  }
568  // Make sure the instruction is valid
569  assert(new_inst);
570 
571  DPRINTF(IQ, "Adding instruction [sn:%llu] PC %s to the IQ.\n",
572  new_inst->seqNum, new_inst->pcState());
573 
574  assert(freeEntries != 0);
575 
576  instList[new_inst->threadNumber].push_back(new_inst);
577 
578  --freeEntries;
579 
580  new_inst->setInIQ();
581 
582  // Look through its source registers (physical regs), and mark any
583  // dependencies.
584  addToDependents(new_inst);
585 
586  // Have this instruction set itself as the producer of its destination
587  // register(s).
588  addToProducers(new_inst);
589 
590  if (new_inst->isMemRef()) {
591  memDepUnit[new_inst->threadNumber].insert(new_inst);
592  } else {
593  addIfReady(new_inst);
594  }
595 
597 
598  count[new_inst->threadNumber]++;
599 
600  assert(freeEntries == (numEntries - countInsts()));
601 }
602 
603 void
605 {
606  // @todo: Clean up this code; can do it by setting inst as unable
607  // to issue, then calling normal insert on the inst.
608  if (new_inst->isFloating()) {
610  } else if (new_inst->isVector()) {
612  } else {
614  }
615 
616  assert(new_inst);
617 
618  nonSpecInsts[new_inst->seqNum] = new_inst;
619 
620  DPRINTF(IQ, "Adding non-speculative instruction [sn:%llu] PC %s "
621  "to the IQ.\n",
622  new_inst->seqNum, new_inst->pcState());
623 
624  assert(freeEntries != 0);
625 
626  instList[new_inst->threadNumber].push_back(new_inst);
627 
628  --freeEntries;
629 
630  new_inst->setInIQ();
631 
632  // Have this instruction set itself as the producer of its destination
633  // register(s).
634  addToProducers(new_inst);
635 
636  // If it's a memory instruction, add it to the memory dependency
637  // unit.
638  if (new_inst->isMemRef()) {
639  memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
640  }
641 
643 
644  count[new_inst->threadNumber]++;
645 
646  assert(freeEntries == (numEntries - countInsts()));
647 }
648 
649 void
651 {
652  memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
653 
654  insertNonSpec(barr_inst);
655 }
656 
659 {
660  assert(!instsToExecute.empty());
661  DynInstPtr inst = std::move(instsToExecute.front());
662  instsToExecute.pop_front();
663  if (inst->isFloating()) {
665  } else if (inst->isVector()) {
667  } else {
669  }
670  return inst;
671 }
672 
673 void
675 {
676  assert(!readyInsts[op_class].empty());
677 
678  ListOrderEntry queue_entry;
679 
680  queue_entry.queueType = op_class;
681 
682  queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
683 
684  ListOrderIt list_it = listOrder.begin();
685  ListOrderIt list_end_it = listOrder.end();
686 
687  while (list_it != list_end_it) {
688  if ((*list_it).oldestInst > queue_entry.oldestInst) {
689  break;
690  }
691 
692  list_it++;
693  }
694 
695  readyIt[op_class] = listOrder.insert(list_it, queue_entry);
696  queueOnList[op_class] = true;
697 }
698 
699 void
701 {
702  // Get iterator of next item on the list
703  // Delete the original iterator
704  // Determine if the next item is either the end of the list or younger
705  // than the new instruction. If so, then add in a new iterator right here.
706  // If not, then move along.
707  ListOrderEntry queue_entry;
708  OpClass op_class = (*list_order_it).queueType;
709  ListOrderIt next_it = list_order_it;
710 
711  ++next_it;
712 
713  queue_entry.queueType = op_class;
714  queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
715 
716  while (next_it != listOrder.end() &&
717  (*next_it).oldestInst < queue_entry.oldestInst) {
718  ++next_it;
719  }
720 
721  readyIt[op_class] = listOrder.insert(next_it, queue_entry);
722 }
723 
724 void
726 {
727  DPRINTF(IQ, "Processing FU completion [sn:%llu]\n", inst->seqNum);
728  assert(!cpu->switchedOut());
729  // The CPU could have been sleeping until this op completed (*extremely*
730  // long latency op). Wake it if it was. This may be overkill.
731  --wbOutstanding;
732  iewStage->wakeCPU();
733 
734  if (fu_idx > -1)
735  fuPool->freeUnitNextCycle(fu_idx);
736 
737  // @todo: Ensure that these FU Completions happen at the beginning
738  // of a cycle, otherwise they could add too many instructions to
739  // the queue.
740  issueToExecuteQueue->access(-1)->size++;
741  instsToExecute.push_back(inst);
742 }
743 
744 // @todo: Figure out a better way to remove the squashed items from the
745 // lists. Checking the top item of each list to see if it's squashed
746 // wastes time and forces jumps.
747 void
749 {
750  DPRINTF(IQ, "Attempting to schedule ready instructions from "
751  "the IQ.\n");
752 
753  IssueStruct *i2e_info = issueToExecuteQueue->access(0);
754 
755  DynInstPtr mem_inst;
756  while ((mem_inst = getDeferredMemInstToExecute())) {
757  addReadyMemInst(mem_inst);
758  }
759 
760  // See if any cache blocked instructions are able to be executed
761  while ((mem_inst = getBlockedMemInstToExecute())) {
762  addReadyMemInst(mem_inst);
763  }
764 
765  // Have iterator to head of the list
766  // While I haven't exceeded bandwidth or reached the end of the list,
767  // Try to get a FU that can do what this op needs.
768  // If successful, change the oldestInst to the new top of the list, put
769  // the queue in the proper place in the list.
770  // Increment the iterator.
771  // This will avoid trying to schedule a certain op class if there are no
772  // FUs that handle it.
773  int total_issued = 0;
774  ListOrderIt order_it = listOrder.begin();
775  ListOrderIt order_end_it = listOrder.end();
776 
777  while (total_issued < totalWidth && order_it != order_end_it) {
778  OpClass op_class = (*order_it).queueType;
779 
780  assert(!readyInsts[op_class].empty());
781 
782  DynInstPtr issuing_inst = readyInsts[op_class].top();
783 
784  if (issuing_inst->isFloating()) {
786  } else if (issuing_inst->isVector()) {
788  } else {
790  }
791 
792  assert(issuing_inst->seqNum == (*order_it).oldestInst);
793 
794  if (issuing_inst->isSquashed()) {
795  readyInsts[op_class].pop();
796 
797  if (!readyInsts[op_class].empty()) {
798  moveToYoungerInst(order_it);
799  } else {
800  readyIt[op_class] = listOrder.end();
801  queueOnList[op_class] = false;
802  }
803 
804  listOrder.erase(order_it++);
805 
807 
808  continue;
809  }
810 
811  int idx = FUPool::NoCapableFU;
812  Cycles op_latency = Cycles(1);
813  ThreadID tid = issuing_inst->threadNumber;
814 
815  if (op_class != No_OpClass) {
816  idx = fuPool->getUnit(op_class);
817  if (issuing_inst->isFloating()) {
819  } else if (issuing_inst->isVector()) {
821  } else {
823  }
824  if (idx > FUPool::NoFreeFU) {
825  op_latency = fuPool->getOpLatency(op_class);
826  }
827  }
828 
829  // If we have an instruction that doesn't require a FU, or a
830  // valid FU, then schedule for execution.
831  if (idx != FUPool::NoFreeFU) {
832  if (op_latency == Cycles(1)) {
833  i2e_info->size++;
834  instsToExecute.push_back(issuing_inst);
835 
836  // Add the FU onto the list of FU's to be freed next
837  // cycle if we used one.
838  if (idx >= 0)
840  } else {
841  bool pipelined = fuPool->isPipelined(op_class);
842  // Generate completion event for the FU
843  ++wbOutstanding;
844  FUCompletion *execution = new FUCompletion(issuing_inst,
845  idx, this);
846 
847  cpu->schedule(execution,
848  cpu->clockEdge(Cycles(op_latency - 1)));
849 
850  if (!pipelined) {
851  // If FU isn't pipelined, then it must be freed
852  // upon the execution completing.
853  execution->setFreeFU();
854  } else {
855  // Add the FU onto the list of FU's to be freed next cycle.
857  }
858  }
859 
860  DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
861  "[sn:%llu]\n",
862  tid, issuing_inst->pcState(),
863  issuing_inst->seqNum);
864 
865  readyInsts[op_class].pop();
866 
867  if (!readyInsts[op_class].empty()) {
868  moveToYoungerInst(order_it);
869  } else {
870  readyIt[op_class] = listOrder.end();
871  queueOnList[op_class] = false;
872  }
873 
874  issuing_inst->setIssued();
875  ++total_issued;
876 
877 #if TRACING_ON
878  issuing_inst->issueTick = curTick() - issuing_inst->fetchTick;
879 #endif
880 
881  if (issuing_inst->firstIssue == -1)
882  issuing_inst->firstIssue = curTick();
883 
884  if (!issuing_inst->isMemRef()) {
885  // Memory instructions can not be freed from the IQ until they
886  // complete.
887  ++freeEntries;
888  count[tid]--;
889  issuing_inst->clearInIQ();
890  } else {
891  memDepUnit[tid].issue(issuing_inst);
892  }
893 
894  listOrder.erase(order_it++);
895  iqStats.statIssuedInstType[tid][op_class]++;
896  } else {
897  iqStats.statFuBusy[op_class]++;
898  iqStats.fuBusy[tid]++;
899  ++order_it;
900  }
901  }
902 
903  iqStats.numIssuedDist.sample(total_issued);
904  iqStats.instsIssued+= total_issued;
905 
906  // If we issued any instructions, tell the CPU we had activity.
907  // @todo If the way deferred memory instructions are handeled due to
908  // translation changes then the deferredMemInsts condition should be
909  // removed from the code below.
910  if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) {
912  } else {
913  DPRINTF(IQ, "Not able to schedule any instructions.\n");
914  }
915 }
916 
917 void
919 {
920  DPRINTF(IQ, "Marking nonspeculative instruction [sn:%llu] as ready "
921  "to execute.\n", inst);
922 
923  NonSpecMapIt inst_it = nonSpecInsts.find(inst);
924 
925  assert(inst_it != nonSpecInsts.end());
926 
927  ThreadID tid = (*inst_it).second->threadNumber;
928 
929  (*inst_it).second->setAtCommit();
930 
931  (*inst_it).second->setCanIssue();
932 
933  if (!(*inst_it).second->isMemRef()) {
934  addIfReady((*inst_it).second);
935  } else {
936  memDepUnit[tid].nonSpecInstReady((*inst_it).second);
937  }
938 
939  (*inst_it).second = NULL;
940 
941  nonSpecInsts.erase(inst_it);
942 }
943 
944 void
946 {
947  DPRINTF(IQ, "[tid:%i] Committing instructions older than [sn:%llu]\n",
948  tid,inst);
949 
950  ListIt iq_it = instList[tid].begin();
951 
952  while (iq_it != instList[tid].end() &&
953  (*iq_it)->seqNum <= inst) {
954  ++iq_it;
955  instList[tid].pop_front();
956  }
957 
958  assert(freeEntries == (numEntries - countInsts()));
959 }
960 
961 int
963 {
964  int dependents = 0;
965 
966  // The instruction queue here takes care of both floating and int ops
967  if (completed_inst->isFloating()) {
969  } else if (completed_inst->isVector()) {
971  } else {
973  }
974 
975  completed_inst->lastWakeDependents = curTick();
976 
977  DPRINTF(IQ, "Waking dependents of completed instruction.\n");
978 
979  assert(!completed_inst->isSquashed());
980 
981  // Tell the memory dependence unit to wake any dependents on this
982  // instruction if it is a memory instruction. Also complete the memory
983  // instruction at this point since we know it executed without issues.
984  ThreadID tid = completed_inst->threadNumber;
985  if (completed_inst->isMemRef()) {
986  memDepUnit[tid].completeInst(completed_inst);
987 
988  DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%llu]\n",
989  completed_inst->pcState(), completed_inst->seqNum);
990 
991  ++freeEntries;
992  completed_inst->memOpDone(true);
993  count[tid]--;
994  } else if (completed_inst->isReadBarrier() ||
995  completed_inst->isWriteBarrier()) {
996  // Completes a non mem ref barrier
997  memDepUnit[tid].completeInst(completed_inst);
998  }
999 
1000  for (int dest_reg_idx = 0;
1001  dest_reg_idx < completed_inst->numDestRegs();
1002  dest_reg_idx++)
1003  {
1004  PhysRegIdPtr dest_reg =
1005  completed_inst->regs.renamedDestIdx(dest_reg_idx);
1006 
1007  // Special case of uniq or control registers. They are not
1008  // handled by the IQ and thus have no dependency graph entry.
1009  if (dest_reg->isFixedMapping()) {
1010  DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n",
1011  dest_reg->index(), dest_reg->className());
1012  continue;
1013  }
1014 
1015  // Avoid waking up dependents if the register is pinned
1016  dest_reg->decrNumPinnedWritesToComplete();
1017  if (dest_reg->isPinned())
1018  completed_inst->setPinnedRegsWritten();
1019 
1020  if (dest_reg->getNumPinnedWritesToComplete() != 0) {
1021  DPRINTF(IQ, "Reg %d [%s] is pinned, skipping\n",
1022  dest_reg->index(), dest_reg->className());
1023  continue;
1024  }
1025 
1026  DPRINTF(IQ, "Waking any dependents on register %i (%s).\n",
1027  dest_reg->index(),
1028  dest_reg->className());
1029 
1030  //Go through the dependency chain, marking the registers as
1031  //ready within the waiting instructions.
1032  DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex());
1033 
1034  while (dep_inst) {
1035  DPRINTF(IQ, "Waking up a dependent instruction, [sn:%llu] "
1036  "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1037 
1038  // Might want to give more information to the instruction
1039  // so that it knows which of its source registers is
1040  // ready. However that would mean that the dependency
1041  // graph entries would need to hold the src_reg_idx.
1042  dep_inst->markSrcRegReady();
1043 
1044  addIfReady(dep_inst);
1045 
1046  dep_inst = dependGraph.pop(dest_reg->flatIndex());
1047 
1048  ++dependents;
1049  }
1050 
1051  // Reset the head node now that all of its dependents have
1052  // been woken up.
1053  assert(dependGraph.empty(dest_reg->flatIndex()));
1054  dependGraph.clearInst(dest_reg->flatIndex());
1055 
1056  // Mark the scoreboard as having that register ready.
1057  regScoreboard[dest_reg->flatIndex()] = true;
1058  }
1059  return dependents;
1060 }
1061 
1062 void
1064 {
1065  OpClass op_class = ready_inst->opClass();
1066 
1067  readyInsts[op_class].push(ready_inst);
1068 
1069  // Will need to reorder the list if either a queue is not on the list,
1070  // or it has an older instruction than last time.
1071  if (!queueOnList[op_class]) {
1072  addToOrderList(op_class);
1073  } else if (readyInsts[op_class].top()->seqNum <
1074  (*readyIt[op_class]).oldestInst) {
1075  listOrder.erase(readyIt[op_class]);
1076  addToOrderList(op_class);
1077  }
1078 
1079  DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1080  "the ready list, PC %s opclass:%i [sn:%llu].\n",
1081  ready_inst->pcState(), op_class, ready_inst->seqNum);
1082 }
1083 
1084 void
1086 {
1087  DPRINTF(IQ, "Rescheduling mem inst [sn:%llu]\n", resched_inst->seqNum);
1088 
1089  // Reset DTB translation state
1090  resched_inst->translationStarted(false);
1091  resched_inst->translationCompleted(false);
1092 
1093  resched_inst->clearCanIssue();
1094  memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1095 }
1096 
1097 void
1099 {
1100  memDepUnit[replay_inst->threadNumber].replay();
1101 }
1102 
1103 void
1105 {
1106  deferredMemInsts.push_back(deferred_inst);
1107 }
1108 
1109 void
1111 {
1112  blocked_inst->clearIssued();
1113  blocked_inst->clearCanIssue();
1114  blockedMemInsts.push_back(blocked_inst);
1115  DPRINTF(IQ, "Memory inst [sn:%llu] PC %s is blocked, will be "
1116  "reissued later\n", blocked_inst->seqNum,
1117  blocked_inst->pcState());
1118 }
1119 
1120 void
1122 {
1123  DPRINTF(IQ, "Cache is unblocked, rescheduling blocked memory "
1124  "instructions\n");
1126  // Get the CPU ticking again
1127  cpu->wakeCPU();
1128 }
1129 
1130 DynInstPtr
1132 {
1133  for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1134  ++it) {
1135  if ((*it)->translationCompleted() || (*it)->isSquashed()) {
1136  DynInstPtr mem_inst = std::move(*it);
1137  deferredMemInsts.erase(it);
1138  return mem_inst;
1139  }
1140  }
1141  return nullptr;
1142 }
1143 
1144 DynInstPtr
1146 {
1147  if (retryMemInsts.empty()) {
1148  return nullptr;
1149  } else {
1150  DynInstPtr mem_inst = std::move(retryMemInsts.front());
1151  retryMemInsts.pop_front();
1152  return mem_inst;
1153  }
1154 }
1155 
1156 void
1158  const DynInstPtr &faulting_load)
1159 {
1161  memDepUnit[store->threadNumber].violation(store, faulting_load);
1162 }
1163 
1164 void
1166 {
1167  DPRINTF(IQ, "[tid:%i] Starting to squash instructions in "
1168  "the IQ.\n", tid);
1169 
1170  // Read instruction sequence number of last instruction out of the
1171  // time buffer.
1172  squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1173 
1174  doSquash(tid);
1175 
1176  // Also tell the memory dependence unit to squash.
1177  memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1178 }
1179 
1180 void
1182 {
1183  // Start at the tail.
1184  ListIt squash_it = instList[tid].end();
1185  --squash_it;
1186 
1187  DPRINTF(IQ, "[tid:%i] Squashing until sequence number %i!\n",
1188  tid, squashedSeqNum[tid]);
1189 
1190  // Squash any instructions younger than the squashed sequence number
1191  // given.
1192  while (squash_it != instList[tid].end() &&
1193  (*squash_it)->seqNum > squashedSeqNum[tid]) {
1194 
1195  DynInstPtr squashed_inst = (*squash_it);
1196  if (squashed_inst->isFloating()) {
1198  } else if (squashed_inst->isVector()) {
1200  } else {
1202  }
1203 
1204  // Only handle the instruction if it actually is in the IQ and
1205  // hasn't already been squashed in the IQ.
1206  if (squashed_inst->threadNumber != tid ||
1207  squashed_inst->isSquashedInIQ()) {
1208  --squash_it;
1209  continue;
1210  }
1211 
1212  if (!squashed_inst->isIssued() ||
1213  (squashed_inst->isMemRef() &&
1214  !squashed_inst->memOpDone())) {
1215 
1216  DPRINTF(IQ, "[tid:%i] Instruction [sn:%llu] PC %s squashed.\n",
1217  tid, squashed_inst->seqNum, squashed_inst->pcState());
1218 
1219  bool is_acq_rel = squashed_inst->isFullMemBarrier() &&
1220  (squashed_inst->isLoad() ||
1221  (squashed_inst->isStore() &&
1222  !squashed_inst->isStoreConditional()));
1223 
1224  // Remove the instruction from the dependency list.
1225  if (is_acq_rel ||
1226  (!squashed_inst->isNonSpeculative() &&
1227  !squashed_inst->isStoreConditional() &&
1228  !squashed_inst->isAtomic() &&
1229  !squashed_inst->isReadBarrier() &&
1230  !squashed_inst->isWriteBarrier())) {
1231 
1232  for (int src_reg_idx = 0;
1233  src_reg_idx < squashed_inst->numSrcRegs();
1234  src_reg_idx++)
1235  {
1236  PhysRegIdPtr src_reg =
1237  squashed_inst->regs.renamedSrcIdx(src_reg_idx);
1238 
1239  // Only remove it from the dependency graph if it
1240  // was placed there in the first place.
1241 
1242  // Instead of doing a linked list traversal, we
1243  // can just remove these squashed instructions
1244  // either at issue time, or when the register is
1245  // overwritten. The only downside to this is it
1246  // leaves more room for error.
1247 
1248  if (!squashed_inst->regs.readySrcIdx(src_reg_idx) &&
1249  !src_reg->isFixedMapping()) {
1250  dependGraph.remove(src_reg->flatIndex(),
1251  squashed_inst);
1252  }
1253 
1255  }
1256 
1257  } else if (!squashed_inst->isStoreConditional() ||
1258  !squashed_inst->isCompleted()) {
1259  NonSpecMapIt ns_inst_it =
1260  nonSpecInsts.find(squashed_inst->seqNum);
1261 
1262  // we remove non-speculative instructions from
1263  // nonSpecInsts already when they are ready, and so we
1264  // cannot always expect to find them
1265  if (ns_inst_it == nonSpecInsts.end()) {
1266  // loads that became ready but stalled on a
1267  // blocked cache are alreayd removed from
1268  // nonSpecInsts, and have not faulted
1269  assert(squashed_inst->getFault() != NoFault ||
1270  squashed_inst->isMemRef());
1271  } else {
1272 
1273  (*ns_inst_it).second = NULL;
1274 
1275  nonSpecInsts.erase(ns_inst_it);
1276 
1278  }
1279  }
1280 
1281  // Might want to also clear out the head of the dependency graph.
1282 
1283  // Mark it as squashed within the IQ.
1284  squashed_inst->setSquashedInIQ();
1285 
1286  // @todo: Remove this hack where several statuses are set so the
1287  // inst will flow through the rest of the pipeline.
1288  squashed_inst->setIssued();
1289  squashed_inst->setCanCommit();
1290  squashed_inst->clearInIQ();
1291 
1292  //Update Thread IQ Count
1293  count[squashed_inst->threadNumber]--;
1294 
1295  ++freeEntries;
1296  }
1297 
1298  // IQ clears out the heads of the dependency graph only when
1299  // instructions reach writeback stage. If an instruction is squashed
1300  // before writeback stage, its head of dependency graph would not be
1301  // cleared out; it holds the instruction's DynInstPtr. This
1302  // prevents freeing the squashed instruction's DynInst.
1303  // Thus, we need to manually clear out the squashed instructions'
1304  // heads of dependency graph.
1305  for (int dest_reg_idx = 0;
1306  dest_reg_idx < squashed_inst->numDestRegs();
1307  dest_reg_idx++)
1308  {
1309  PhysRegIdPtr dest_reg =
1310  squashed_inst->regs.renamedDestIdx(dest_reg_idx);
1311  if (dest_reg->isFixedMapping()){
1312  continue;
1313  }
1314  assert(dependGraph.empty(dest_reg->flatIndex()));
1315  dependGraph.clearInst(dest_reg->flatIndex());
1316  }
1317  instList[tid].erase(squash_it--);
1319  }
1320 }
1321 
1322 bool
1324  const DynInstPtr &lhs, const DynInstPtr &rhs) const
1325 {
1326  return lhs->seqNum > rhs->seqNum;
1327 }
1328 
1329 bool
1331 {
1332  // Loop through the instruction's source registers, adding
1333  // them to the dependency list if they are not ready.
1334  int8_t total_src_regs = new_inst->numSrcRegs();
1335  bool return_val = false;
1336 
1337  for (int src_reg_idx = 0;
1338  src_reg_idx < total_src_regs;
1339  src_reg_idx++)
1340  {
1341  // Only add it to the dependency graph if it's not ready.
1342  if (!new_inst->regs.readySrcIdx(src_reg_idx)) {
1343  PhysRegIdPtr src_reg = new_inst->regs.renamedSrcIdx(src_reg_idx);
1344 
1345  // Check the IQ's scoreboard to make sure the register
1346  // hasn't become ready while the instruction was in flight
1347  // between stages. Only if it really isn't ready should
1348  // it be added to the dependency graph.
1349  if (src_reg->isFixedMapping()) {
1350  continue;
1351  } else if (!regScoreboard[src_reg->flatIndex()]) {
1352  DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1353  "is being added to the dependency chain.\n",
1354  new_inst->pcState(), src_reg->index(),
1355  src_reg->className());
1356 
1357  dependGraph.insert(src_reg->flatIndex(), new_inst);
1358 
1359  // Change the return value to indicate that something
1360  // was added to the dependency graph.
1361  return_val = true;
1362  } else {
1363  DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1364  "became ready before it reached the IQ.\n",
1365  new_inst->pcState(), src_reg->index(),
1366  src_reg->className());
1367  // Mark a register ready within the instruction.
1368  new_inst->markSrcRegReady(src_reg_idx);
1369  }
1370  }
1371  }
1372 
1373  return return_val;
1374 }
1375 
1376 void
1378 {
1379  // Nothing really needs to be marked when an instruction becomes
1380  // the producer of a register's value, but for convenience a ptr
1381  // to the producing instruction will be placed in the head node of
1382  // the dependency links.
1383  int8_t total_dest_regs = new_inst->numDestRegs();
1384 
1385  for (int dest_reg_idx = 0;
1386  dest_reg_idx < total_dest_regs;
1387  dest_reg_idx++)
1388  {
1389  PhysRegIdPtr dest_reg = new_inst->regs.renamedDestIdx(dest_reg_idx);
1390 
1391  // Some registers have fixed mapping, and there is no need to track
1392  // dependencies as these instructions must be executed at commit.
1393  if (dest_reg->isFixedMapping()) {
1394  continue;
1395  }
1396 
1397  if (!dependGraph.empty(dest_reg->flatIndex())) {
1398  dependGraph.dump();
1399  panic("Dependency graph %i (%s) (flat: %i) not empty!",
1400  dest_reg->index(), dest_reg->className(),
1401  dest_reg->flatIndex());
1402  }
1403 
1404  dependGraph.setInst(dest_reg->flatIndex(), new_inst);
1405 
1406  // Mark the scoreboard to say it's not yet ready.
1407  regScoreboard[dest_reg->flatIndex()] = false;
1408  }
1409 }
1410 
1411 void
1413 {
1414  // If the instruction now has all of its source registers
1415  // available, then add it to the list of ready instructions.
1416  if (inst->readyToIssue()) {
1417 
1418  //Add the instruction to the proper ready list.
1419  if (inst->isMemRef()) {
1420 
1421  DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1422 
1423  // Message to the mem dependence unit that this instruction has
1424  // its registers ready.
1425  memDepUnit[inst->threadNumber].regsReady(inst);
1426 
1427  return;
1428  }
1429 
1430  OpClass op_class = inst->opClass();
1431 
1432  DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1433  "the ready list, PC %s opclass:%i [sn:%llu].\n",
1434  inst->pcState(), op_class, inst->seqNum);
1435 
1436  readyInsts[op_class].push(inst);
1437 
1438  // Will need to reorder the list if either a queue is not on the list,
1439  // or it has an older instruction than last time.
1440  if (!queueOnList[op_class]) {
1441  addToOrderList(op_class);
1442  } else if (readyInsts[op_class].top()->seqNum <
1443  (*readyIt[op_class]).oldestInst) {
1444  listOrder.erase(readyIt[op_class]);
1445  addToOrderList(op_class);
1446  }
1447  }
1448 }
1449 
1450 int
1452 {
1453  return numEntries - freeEntries;
1454 }
1455 
1456 void
1458 {
1459  for (int i = 0; i < Num_OpClasses; ++i) {
1460  cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1461 
1462  cprintf("\n");
1463  }
1464 
1465  cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1466 
1467  NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1468  NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1469 
1470  cprintf("Non speculative list: ");
1471 
1472  while (non_spec_it != non_spec_end_it) {
1473  cprintf("%s [sn:%llu]", (*non_spec_it).second->pcState(),
1474  (*non_spec_it).second->seqNum);
1475  ++non_spec_it;
1476  }
1477 
1478  cprintf("\n");
1479 
1480  ListOrderIt list_order_it = listOrder.begin();
1481  ListOrderIt list_order_end_it = listOrder.end();
1482  int i = 1;
1483 
1484  cprintf("List order: ");
1485 
1486  while (list_order_it != list_order_end_it) {
1487  cprintf("%i OpClass:%i [sn:%llu] ", i, (*list_order_it).queueType,
1488  (*list_order_it).oldestInst);
1489 
1490  ++list_order_it;
1491  ++i;
1492  }
1493 
1494  cprintf("\n");
1495 }
1496 
1497 
1498 void
1500 {
1501  for (ThreadID tid = 0; tid < numThreads; ++tid) {
1502  int num = 0;
1503  int valid_num = 0;
1504  ListIt inst_list_it = instList[tid].begin();
1505 
1506  while (inst_list_it != instList[tid].end()) {
1507  cprintf("Instruction:%i\n", num);
1508  if (!(*inst_list_it)->isSquashed()) {
1509  if (!(*inst_list_it)->isIssued()) {
1510  ++valid_num;
1511  cprintf("Count:%i\n", valid_num);
1512  } else if ((*inst_list_it)->isMemRef() &&
1513  !(*inst_list_it)->memOpDone()) {
1514  // Loads that have not been marked as executed
1515  // still count towards the total instructions.
1516  ++valid_num;
1517  cprintf("Count:%i\n", valid_num);
1518  }
1519  }
1520 
1521  cprintf("PC: %s\n[sn:%llu]\n[tid:%i]\n"
1522  "Issued:%i\nSquashed:%i\n",
1523  (*inst_list_it)->pcState(),
1524  (*inst_list_it)->seqNum,
1525  (*inst_list_it)->threadNumber,
1526  (*inst_list_it)->isIssued(),
1527  (*inst_list_it)->isSquashed());
1528 
1529  if ((*inst_list_it)->isMemRef()) {
1530  cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1531  }
1532 
1533  cprintf("\n");
1534 
1535  inst_list_it++;
1536  ++num;
1537  }
1538  }
1539 
1540  cprintf("Insts to Execute list:\n");
1541 
1542  int num = 0;
1543  int valid_num = 0;
1544  ListIt inst_list_it = instsToExecute.begin();
1545 
1546  while (inst_list_it != instsToExecute.end())
1547  {
1548  cprintf("Instruction:%i\n",
1549  num);
1550  if (!(*inst_list_it)->isSquashed()) {
1551  if (!(*inst_list_it)->isIssued()) {
1552  ++valid_num;
1553  cprintf("Count:%i\n", valid_num);
1554  } else if ((*inst_list_it)->isMemRef() &&
1555  !(*inst_list_it)->memOpDone()) {
1556  // Loads that have not been marked as executed
1557  // still count towards the total instructions.
1558  ++valid_num;
1559  cprintf("Count:%i\n", valid_num);
1560  }
1561  }
1562 
1563  cprintf("PC: %s\n[sn:%llu]\n[tid:%i]\n"
1564  "Issued:%i\nSquashed:%i\n",
1565  (*inst_list_it)->pcState(),
1566  (*inst_list_it)->seqNum,
1567  (*inst_list_it)->threadNumber,
1568  (*inst_list_it)->isIssued(),
1569  (*inst_list_it)->isSquashed());
1570 
1571  if ((*inst_list_it)->isMemRef()) {
1572  cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1573  }
1574 
1575  cprintf("\n");
1576 
1577  inst_list_it++;
1578  ++num;
1579  }
1580 }
1581 
1582 } // namespace o3
1583 } // namespace gem5
gem5::o3::InstructionQueue::IQStats::miscInstsIssued
statistics::Scalar miscInstsIssued
Stat for number of miscellaneous instructions issued.
Definition: inst_queue.hh:500
gem5::o3::InstructionQueue::readyIt
ListOrderIt readyIt[Num_OpClasses]
Iterators of each ready queue.
Definition: inst_queue.hh:393
gem5::o3::InstructionQueue::rescheduleMemInst
void rescheduleMemInst(const DynInstPtr &resched_inst)
Reschedules a memory instruction.
Definition: inst_queue.cc:1085
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::o3::InstructionQueue::addToOrderList
void addToOrderList(OpClass op_class)
Add an op class to the age order list.
Definition: inst_queue.cc:674
gem5::o3::InstructionQueue::maxEntries
unsigned maxEntries[MaxThreads]
Max IQ Entries Per Thread.
Definition: inst_queue.hh:423
gem5::o3::InstructionQueue::resetEntries
void resetEntries()
Resets max entries for all threads.
Definition: inst_queue.cc:487
gem5::o3::InstructionQueue::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: inst_queue.cc:461
gem5::o3::InstructionQueue::issueToExecuteQueue
TimeBuffer< IssueStruct > * issueToExecuteQueue
The queue to the execute stage.
Definition: inst_queue.hh:304
gem5::PhysRegId::isPinned
bool isPinned() const
Definition: reg_class.hh:290
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::o3::InstructionQueue::IQStats::statIssuedInstType
statistics::Vector2d statIssuedInstType
Stat for total number issued for each instruction type.
Definition: inst_queue.hh:534
gem5::BaseCPU::switchedOut
bool switchedOut() const
Determine if the CPU is switched out.
Definition: base.hh:357
gem5::o3::InstructionQueue::IQIOStats::fpAluAccesses
statistics::Scalar fpAluAccesses
Definition: inst_queue.hh:560
gem5::o3::InstructionQueue::IQStats::squashedInstsIssued
statistics::Scalar squashedInstsIssued
Stat for number of squashed instructions that were ready to issue.
Definition: inst_queue.hh:503
gem5::o3::InstructionQueue::countInsts
int countInsts()
Debugging function to count how many entries are in the IQ.
Definition: inst_queue.cc:1451
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::o3::InstructionQueue::instsToExecute
std::list< DynInstPtr > instsToExecute
List of instructions that are ready to be executed.
Definition: inst_queue.hh:323
gem5::o3::InstructionQueue::IQStats::instsIssued
statistics::Scalar instsIssued
Definition: inst_queue.hh:490
gem5::o3::InstructionQueue::getDeferredMemInstToExecute
DynInstPtr getDeferredMemInstToExecute()
Gets a memory instruction that was referred due to a delayed DTB translation if it is now ready to ex...
Definition: inst_queue.cc:1131
gem5::o3::FUPool::NoCapableFU
static constexpr auto NoCapableFU
Definition: fu_pool.hh:142
gem5::o3::InstructionQueue::IQIOStats::IQIOStats
IQIOStats(statistics::Group *parent)
Definition: inst_queue.cc:324
gem5::o3::InstructionQueue::regScoreboard
std::vector< bool > regScoreboard
A cache of the recently woken registers.
Definition: inst_queue.hh:454
gem5::o3::MemDepUnit::insertBarrier
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a barrier instruction.
Definition: mem_dep_unit.cc:323
gem5::o3::InstructionQueue::isFull
bool isFull()
Returns whether or not the IQ is full.
Definition: inst_queue.cc:523
gem5::o3::InstructionQueue::queueOnList
bool queueOnList[Num_OpClasses]
Tracks if each ready queue is on the age order list.
Definition: inst_queue.hh:388
gem5::o3::InstructionQueue::nonSpecInsts
std::map< InstSeqNum, DynInstPtr > nonSpecInsts
List of non-speculative instructions that will be scheduled once the IQ gets a signal from commit.
Definition: inst_queue.hh:365
gem5::o3::InstructionQueue
A standard instruction queue class.
Definition: inst_queue.hh:98
gem5::o3::InstructionQueue::getBlockedMemInstToExecute
DynInstPtr getBlockedMemInstToExecute()
Gets a memory instruction that was blocked on the cache.
Definition: inst_queue.cc:1145
gem5::statistics::Vector2dBase::init
Derived & init(size_type _x, size_type _y)
Definition: statistics.hh:1171
gem5::o3::MemDepUnit::completeInst
void completeInst(const DynInstPtr &inst)
Notifies completion of an instruction.
Definition: mem_dep_unit.cc:428
gem5::o3::InstructionQueue::IQStats::issueRate
statistics::Formula issueRate
Number of instructions issued per cycle.
Definition: inst_queue.hh:537
gem5::o3::FUPool::getOpLatency
Cycles getOpLatency(OpClass capability)
Returns the operation execution latency of the given capability.
Definition: fu_pool.hh:169
gem5::o3::InstructionQueue::IQIOStats::vecInstQueueWrites
statistics::Scalar vecInstQueueWrites
Definition: inst_queue.hh:556
gem5::o3::InstructionQueue::cpu
CPU * cpu
Pointer to the CPU.
Definition: inst_queue.hh:288
gem5::o3::MemDepUnit::squash
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squashes all instructions up until a given sequence number for a specific thread.
Definition: mem_dep_unit.cc:521
gem5::o3::InstructionQueue::commit
void commit(const InstSeqNum &inst, ThreadID tid=0)
Commits all instructions up to and including the given sequence number, for a specific thread.
Definition: inst_queue.cc:945
gem5::o3::InstructionQueue::IQIOStats::vecInstQueueWakeupAccesses
statistics::Scalar vecInstQueueWakeupAccesses
Definition: inst_queue.hh:557
gem5::o3::InstructionQueue::IQStats::squashedInstsExamined
statistics::Scalar squashedInstsExamined
Stat for number of squashed instructions examined when squashing.
Definition: inst_queue.hh:506
gem5::statistics::DataWrapVec::subname
Derived & subname(off_type index, const std::string &name)
Set the subfield name for the given index, and marks this stat to print at the end of simulation.
Definition: statistics.hh:399
sc_dt::list
static scfx_rep_node * list
Definition: scfx_rep.cc:368
top
Definition: test.h:61
gem5::o3::InstructionQueue::IQStats::instsAdded
statistics::Scalar instsAdded
Stat for number of instructions added.
Definition: inst_queue.hh:486
gem5::o3::InstructionQueue::PqCompare::operator()
bool operator()(const DynInstPtr &lhs, const DynInstPtr &rhs) const
Definition: inst_queue.cc:1323
gem5::o3::InstructionQueue::IQIOStats::intInstQueueReads
statistics::Scalar intInstQueueReads
Definition: inst_queue.hh:549
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::o3::InstructionQueue::IQIOStats::vecInstQueueReads
statistics::Scalar vecInstQueueReads
Definition: inst_queue.hh:555
dyn_inst.hh
gem5::o3::InstructionQueue::numEntries
unsigned numEntries
The number of entries in the instruction queue.
Definition: inst_queue.hh:429
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::o3::InstructionQueue::addToDependents
bool addToDependents(const DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a consumer.
Definition: inst_queue.cc:1330
gem5::o3::InstructionQueue::cacheUnblocked
void cacheUnblocked()
Notify instruction queue that a previous blockage has resolved.
Definition: inst_queue.cc:1121
gem5::o3::InstructionQueue::takeOverFrom
void takeOverFrom()
Takes over execution from another CPU's thread.
Definition: inst_queue.cc:470
gem5::o3::InstructionQueue::IQIOStats::intInstQueueWakeupAccesses
statistics::Scalar intInstQueueWakeupAccesses
Definition: inst_queue.hh:551
gem5::o3::InstructionQueue::numPhysRegs
unsigned numPhysRegs
The number of physical registers in the CPU.
Definition: inst_queue.hh:435
gem5::o3::InstructionQueue::resetState
void resetState()
Resets all instruction queue state.
Definition: inst_queue.cc:390
gem5::o3::InstructionQueue::setIssueToExecuteQueue
void setIssueToExecuteQueue(TimeBuffer< IssueStruct > *i2eQueue)
Sets the timer buffer between issue and execute.
Definition: inst_queue.cc:435
gem5::statistics::DistBase::sample
void sample(const U &v, int n=1)
Add a value to the distribtion n times.
Definition: statistics.hh:1325
gem5::PhysRegId::decrNumPinnedWritesToComplete
void decrNumPinnedWritesToComplete()
Definition: reg_class.hh:304
gem5::statistics::dist
const FlagsType dist
Print the distribution.
Definition: info.hh:66
gem5::o3::IEW::wakeCPU
void wakeCPU()
Tells the CPU to wakeup if it has descheduled itself due to no activity.
Definition: iew.cc:805
gem5::o3::InstructionQueue::ListOrderEntry::queueType
OpClass queueType
Definition: inst_queue.hh:372
gem5::o3::InstructionQueue::dependGraph
DependencyGraph< DynInstPtr > dependGraph
Definition: inst_queue.hh:404
gem5::o3::InstructionQueue::freeEntries
unsigned freeEntries
Number of free IQ entries left.
Definition: inst_queue.hh:426
gem5::RefCountingPtr< DynInst >
gem5::TimeBuffer
Definition: timebuf.hh:40
gem5::o3::MemDepUnit::issue
void issue(const DynInstPtr &inst)
Issues the given instruction.
Definition: mem_dep_unit.cc:582
gem5::o3::InstructionQueue::ListOrderIt
std::list< ListOrderEntry >::iterator ListOrderIt
Definition: inst_queue.hh:385
gem5::o3::InstructionQueue::wakeDependents
int wakeDependents(const DynInstPtr &completed_inst)
Wakes all dependents of a completed instruction.
Definition: inst_queue.cc:962
gem5::o3::InstructionQueue::IQIOStats::vecAluAccesses
statistics::Scalar vecAluAccesses
Definition: inst_queue.hh:561
gem5::o3::InstructionQueue::iewStage
IEW * iewStage
Pointer to IEW stage.
Definition: inst_queue.hh:294
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::InstructionQueue::memDepUnit
MemDepUnit memDepUnit[MaxThreads]
The memory dependence unit, which tracks/predicts memory dependences between instructions.
Definition: inst_queue.hh:299
gem5::o3::InstructionQueue::deferredMemInsts
std::list< DynInstPtr > deferredMemInsts
List of instructions waiting for their DTB translation to complete (hw page table walk in progress).
Definition: inst_queue.hh:328
gem5::o3::InstructionQueue::iqIOStats
gem5::o3::InstructionQueue::IQIOStats iqIOStats
gem5::statistics::pdf
const FlagsType pdf
Print the percent of the total that this entry represents.
Definition: info.hh:62
gem5::o3::FUPool::freeUnitNextCycle
void freeUnitNextCycle(int fu_idx)
Frees a FU at the end of this cycle.
Definition: fu_pool.cc:190
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
gem5::o3::InstructionQueue::IQIOStats::fpInstQueueReads
statistics::Scalar fpInstQueueReads
Definition: inst_queue.hh:552
gem5::o3::InstructionQueue::InstructionQueue
InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params)
Constructs an IQ.
Definition: inst_queue.cc:87
gem5::o3::InstructionQueue::addIfReady
void addIfReady(const DynInstPtr &inst)
Moves an instruction to the ready queue if it is ready.
Definition: inst_queue.cc:1412
gem5::PhysRegId::flatIndex
const RegIndex & flatIndex() const
Flat index accessor.
Definition: reg_class.hh:263
gem5::o3::InstructionQueue::FUCompletion::setFreeFU
void setFreeFU()
Definition: inst_queue.hh:129
gem5::o3::MemDepUnit::replay
void replay()
Replays all instructions that have been rescheduled by moving them to the ready list.
Definition: mem_dep_unit.cc:385
gem5::o3::InstructionQueue::IQIOStats::intAluAccesses
statistics::Scalar intAluAccesses
Definition: inst_queue.hh:559
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::InstructionQueue::IQStats::squashedOperandsExamined
statistics::Scalar squashedOperandsExamined
Stat for number of squashed instruction operands examined when squashing.
Definition: inst_queue.hh:510
gem5::o3::MemDepUnit::setIQ
void setIQ(InstructionQueue *iq_ptr)
Sets the pointer to the IQ.
Definition: mem_dep_unit.cc:152
gem5::o3::InstructionQueue::name
std::string name() const
Returns the name of the IQ.
Definition: inst_queue.cc:171
gem5::o3::InstructionQueue::FUCompletion
FU completion event class.
Definition: inst_queue.hh:105
gem5::statistics::Distribution::init
Distribution & init(Counter min, Counter max, Counter bkt)
Set the parameters of this distribution.
Definition: statistics.hh:2110
gem5::o3::InstructionQueue::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the global time buffer.
Definition: inst_queue.cc:441
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Event
Definition: eventq.hh:251
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::o3::InstructionQueue::doSquash
void doSquash(ThreadID tid)
Does the actual squashing.
Definition: inst_queue.cc:1181
gem5::o3::InstructionQueue::IQStats::branchInstsIssued
statistics::Scalar branchInstsIssued
Stat for number of branch instructions issued.
Definition: inst_queue.hh:496
gem5::o3::IssueStruct::size
int size
Definition: comm.hh:106
gem5::o3::InstructionQueue::activeThreads
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Definition: inst_queue.hh:417
gem5::o3::IssueStruct
Definition: comm.hh:104
gem5::o3::InstructionQueue::IQStats::squashedNonSpecRemoved
statistics::Scalar squashedNonSpecRemoved
Stat for number of non-speculative instructions removed due to a squash.
Definition: inst_queue.hh:514
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::o3::InstructionQueue::deferMemInst
void deferMemInst(const DynInstPtr &deferred_inst)
Defers a memory instruction when its DTB translation incurs a hw page table walk.
Definition: inst_queue.cc:1104
gem5::o3::MemDepUnit::nonSpecInstReady
void nonSpecInstReady(const DynInstPtr &inst)
Indicate that a non-speculative instruction is ready.
Definition: mem_dep_unit.cc:367
gem5::o3::InstructionQueue::retryMemInsts
std::list< DynInstPtr > retryMemInsts
List of instructions that were cache blocked, but a retry has been seen since, so they can now be ret...
Definition: inst_queue.hh:336
gem5::o3::InstructionQueue::commitToIEWDelay
Cycles commitToIEWDelay
Delay between commit stage and the IQ.
Definition: inst_queue.hh:443
gem5::o3::InstructionQueue::totalWidth
unsigned totalWidth
The total number of instructions that can be issued in one cycle.
Definition: inst_queue.hh:432
gem5::o3::InstructionQueue::numFreeEntries
unsigned numFreeEntries()
Returns total number of free entries.
Definition: inst_queue.cc:509
gem5::o3::InstructionQueue::IQStats::nonSpecInstsAdded
statistics::Scalar nonSpecInstsAdded
Stat for number of non-speculative instructions added.
Definition: inst_queue.hh:488
gem5::o3::InstructionQueue::addToProducers
void addToProducers(const DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a producer.
Definition: inst_queue.cc:1377
gem5::o3::CPU::wakeCPU
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
Definition: cpu.cc:1594
gem5::o3::MemDepUnit::violation
void violation(const DynInstPtr &store_inst, const DynInstPtr &violating_load)
Indicates an ordering violation between a store and a younger load.
Definition: mem_dep_unit.cc:571
gem5::o3::InstructionQueue::IQStats::fuBusyRate
statistics::Formula fuBusyRate
Number of times the FU was busy per instruction issued.
Definition: inst_queue.hh:542
gem5::o3::InstructionQueue::fromCommit
TimeBuffer< TimeStruct >::wire fromCommit
Wire to read information from timebuffer.
Definition: inst_queue.hh:310
gem5::o3::InstructionQueue::fuPool
FUPool * fuPool
Function unit pool.
Definition: inst_queue.hh:313
gem5::o3::InstructionQueue::dumpInsts
void dumpInsts()
Debugging function to dump out all instructions that are in the IQ.
Definition: inst_queue.cc:1499
fu_pool.hh
gem5::o3::InstructionQueue::IQStats::memInstsIssued
statistics::Scalar memInstsIssued
Stat for number of memory instructions issued.
Definition: inst_queue.hh:498
gem5::PhysRegId::getNumPinnedWritesToComplete
int getNumPinnedWritesToComplete() const
Definition: reg_class.hh:293
gem5::o3::InstructionQueue::scheduleNonSpec
void scheduleNonSpec(const InstSeqNum &inst)
Schedules a single specific non-speculative instruction.
Definition: inst_queue.cc:918
core.hh
gem5::o3::InstructionQueue::processFUCompletion
void processFUCompletion(const DynInstPtr &inst, int fu_idx)
Process FU completion event.
Definition: inst_queue.cc:725
gem5::o3::InstructionQueue::getInstToExecute
DynInstPtr getInstToExecute()
Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to exe...
Definition: inst_queue.cc:658
gem5::o3::FUPool::isPipelined
bool isPipelined(OpClass capability)
Returns the issue latency of the given capability.
Definition: fu_pool.hh:174
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::o3::InstructionQueue::IQStats::intInstsIssued
statistics::Scalar intInstsIssued
Stat for number of integer instructions issued.
Definition: inst_queue.hh:492
gem5::o3::InstructionQueue::iqStats
gem5::o3::InstructionQueue::IQStats iqStats
gem5::o3::InstructionQueue::IQIOStats::intInstQueueWrites
statistics::Scalar intInstQueueWrites
Definition: inst_queue.hh:550
gem5::o3::InstructionQueue::insertBarrier
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly.
Definition: inst_queue.cc:650
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::InstructionQueue::FUCompletion::process
virtual void process()
Definition: inst_queue.cc:74
gem5::o3::InstructionQueue::IQStats::floatInstsIssued
statistics::Scalar floatInstsIssued
Stat for number of floating point instructions issued.
Definition: inst_queue.hh:494
gem5::o3::InstructionQueue::iqPolicy
SMTQueuePolicy iqPolicy
IQ sharing policy for SMT.
Definition: inst_queue.hh:411
gem5::o3::MemDepUnit::regsReady
void regsReady(const DynInstPtr &inst)
Indicate that an instruction has its registers ready.
Definition: mem_dep_unit.cc:345
gem5::o3::CPU::activityThisCycle
void activityThisCycle()
Records that there was time buffer activity this cycle.
Definition: cpu.hh:569
gem5::o3::InstructionQueue::squash
void squash(ThreadID tid)
Squashes instructions for a thread.
Definition: inst_queue.cc:1165
gem5::o3::InstructionQueue::IQIOStats::fpInstQueueWrites
statistics::Scalar fpInstQueueWrites
Definition: inst_queue.hh:553
gem5::o3::InstructionQueue::~InstructionQueue
~InstructionQueue()
Destructs the IQ.
Definition: inst_queue.cc:161
gem5::statistics::DataWrap::prereq
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Definition: statistics.hh:369
gem5::PhysRegId::className
const char * className() const
Return a const char* with the register class name.
Definition: reg_class.hh:182
gem5::o3::InstructionQueue::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: inst_queue.hh:102
gem5::o3::InstructionQueue::isDrained
bool isDrained() const
Determine if we are drained.
Definition: inst_queue.cc:449
gem5::o3::InstructionQueue::FUCompletion::description
virtual const char * description() const
Return a C string describing the event.
Definition: inst_queue.cc:82
gem5::o3::InstructionQueue::moveToYoungerInst
void moveToYoungerInst(ListOrderIt age_order_it)
Called when the oldest instruction has been removed from a ready queue; this places that ready queue ...
Definition: inst_queue.cc:700
gem5::o3::InstructionQueue::insertNonSpec
void insertNonSpec(const DynInstPtr &new_inst)
Inserts a new, non-speculative instruction into the IQ.
Definition: inst_queue.cc:604
gem5::o3::InstructionQueue::blockedMemInsts
std::list< DynInstPtr > blockedMemInsts
List of instructions that have been cache blocked.
Definition: inst_queue.hh:331
gem5::o3::InstructionQueue::addReadyMemInst
void addReadyMemInst(const DynInstPtr &ready_inst)
Adds a ready memory instruction to the ready list.
Definition: inst_queue.cc:1063
gem5::o3::InstructionQueue::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets active threads list.
Definition: inst_queue.cc:429
gem5::o3::InstructionQueue::count
unsigned count[MaxThreads]
Per Thread IQ count.
Definition: inst_queue.hh:420
gem5::o3::InstructionQueue::blockMemInst
void blockMemInst(const DynInstPtr &blocked_inst)
Defers a memory instruction when it is cache blocked.
Definition: inst_queue.cc:1110
gem5::o3::InstructionQueue::IQStats::IQStats
IQStats(CPU *cpu, const unsigned &total_width)
Definition: inst_queue.cc:176
gem5::o3::MemDepUnit::insertNonSpec
void insertNonSpec(const DynInstPtr &inst)
Inserts a non-speculative memory instruction.
Definition: mem_dep_unit.cc:301
logging.hh
gem5::o3::InstructionQueue::insert
void insert(const DynInstPtr &new_inst)
Inserts a new instruction into the IQ.
Definition: inst_queue.cc:559
gem5::o3::InstructionQueue::IQStats::statFuBusy
statistics::Vector statFuBusy
Distribution of the cycles it takes to issue an instruction.
Definition: inst_queue.hh:531
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::statistics::DataWrapVec2d::ysubnames
Derived & ysubnames(const char **names)
Definition: statistics.hh:475
gem5::o3::InstructionQueue::entryAmount
int entryAmount(ThreadID num_threads)
Number of entries needed for given amount of threads.
Definition: inst_queue.cc:476
gem5::o3::InstructionQueue::IQStats::fuBusy
statistics::Vector fuBusy
Number of times the FU was busy.
Definition: inst_queue.hh:540
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:198
gem5::o3::InstructionQueue::replayMemInst
void replayMemInst(const DynInstPtr &replay_inst)
Replays a memory instruction.
Definition: inst_queue.cc:1098
gem5::o3::InstructionQueue::IQStats::numIssuedDist
statistics::Distribution numIssuedDist
Distribution of number of instructions in the queue.
Definition: inst_queue.hh:522
gem5::o3::InstructionQueue::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
The backwards time buffer.
Definition: inst_queue.hh:307
inst_queue.hh
gem5::Num_OpClasses
static const OpClass Num_OpClasses
Definition: op_class.hh:108
gem5::o3::InstructionQueue::numThreads
ThreadID numThreads
Number of Total Threads.
Definition: inst_queue.hh:414
gem5::PhysRegId::isFixedMapping
bool isFixedMapping() const
Returns true if this register is always associated to the same architectural register.
Definition: reg_class.hh:260
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:355
gem5::o3::FUPool::NoFreeFU
static constexpr auto NoFreeFU
Definition: fu_pool.hh:143
gem5::o3::InstructionQueue::scheduleReadyInsts
void scheduleReadyInsts()
Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute.
Definition: inst_queue.cc:748
gem5::o3::InstructionQueue::NonSpecMapIt
std::map< InstSeqNum, DynInstPtr >::iterator NonSpecMapIt
Definition: inst_queue.hh:367
std::list
STL list class.
Definition: stl.hh:51
gem5::o3::InstructionQueue::dumpLists
void dumpLists()
Debugging function to dump all the list sizes, as well as print out the list of nonspeculative instru...
Definition: inst_queue.cc:1457
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::InstructionQueue::wbOutstanding
int wbOutstanding
Number of instructions currently in flight to FUs.
Definition: inst_queue.hh:438
gem5::o3::InstructionQueue::IQIOStats::fpInstQueueWakeupAccesses
statistics::Scalar fpInstQueueWakeupAccesses
Definition: inst_queue.hh:554
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
limits.hh
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1037
gem5::o3::InstructionQueue::squashedSeqNum
InstSeqNum squashedSeqNum[MaxThreads]
The sequence number of the squashed instruction.
Definition: inst_queue.hh:446
gem5::o3::MemDepUnit::init
void init(const O3CPUParams &params, ThreadID tid, CPU *cpu)
Initializes the unit with parameters and a thread id.
Definition: mem_dep_unit.cc:92
gem5::o3::InstructionQueue::ListOrderEntry::oldestInst
InstSeqNum oldestInst
Definition: inst_queue.hh:373
gem5::o3::MemDepUnit::insert
void insert(const DynInstPtr &inst)
Inserts a memory instruction.
Definition: mem_dep_unit.cc:190
gem5::o3::FUPool::getUnit
int getUnit(OpClass capability)
Gets a FU providing the requested capability.
Definition: fu_pool.cc:162
gem5::PhysRegId::index
RegIndex index() const
Visible RegId methods.
Definition: reg_class.hh:154
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::InstructionQueue::listOrder
std::list< ListOrderEntry > listOrder
List that contains the age order of the oldest instruction of each ready queue.
Definition: inst_queue.hh:383
gem5::o3::InstructionQueue::instList
std::list< DynInstPtr > instList[MaxThreads]
List of all the instructions in the IQ (some of which may be issued).
Definition: inst_queue.hh:320
gem5::o3::InstructionQueue::readyInsts
ReadyInstQueue readyInsts[Num_OpClasses]
List of ready instructions, per op class.
Definition: inst_queue.hh:356
gem5::o3::InstructionQueue::violation
void violation(const DynInstPtr &store, const DynInstPtr &faulting_load)
Indicates an ordering violation between a store and a load.
Definition: inst_queue.cc:1157
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::o3::InstructionQueue::ListOrderEntry
Entry for the list age ordering by op class.
Definition: inst_queue.hh:370
gem5::o3::InstructionQueue::hasReadyInsts
bool hasReadyInsts()
Returns if there are any ready instructions in the IQ.
Definition: inst_queue.cc:543
gem5::o3::MemDepUnit::reschedule
void reschedule(const DynInstPtr &inst)
Reschedules an instruction to be re-executed.
Definition: mem_dep_unit.cc:379
gem5::o3::InstructionQueue::FUCompletion::FUCompletion
FUCompletion(const DynInstPtr &_inst, int fu_idx, InstructionQueue *iq_ptr)
Construct a FU completion event.
Definition: inst_queue.cc:66

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