gem5  v21.1.0.2
cpu.cc
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42 
43 #include "cpu/o3/cpu.hh"
44 
45 #include "config/the_isa.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/checker/cpu.hh"
49 #include "cpu/o3/dyn_inst.hh"
50 #include "cpu/o3/limits.hh"
51 #include "cpu/o3/thread_context.hh"
52 #include "cpu/simple_thread.hh"
53 #include "cpu/thread_context.hh"
54 #include "debug/Activity.hh"
55 #include "debug/Drain.hh"
56 #include "debug/O3CPU.hh"
57 #include "debug/Quiesce.hh"
58 #include "enums/MemoryMode.hh"
59 #include "sim/cur_tick.hh"
60 #include "sim/full_system.hh"
61 #include "sim/process.hh"
62 #include "sim/stat_control.hh"
63 #include "sim/system.hh"
64 
65 namespace gem5
66 {
67 
68 struct BaseCPUParams;
69 
70 namespace o3
71 {
72 
73 CPU::CPU(const O3CPUParams &params)
74  : BaseCPU(params),
75  mmu(params.mmu),
76  tickEvent([this]{ tick(); }, "O3CPU tick",
77  false, Event::CPU_Tick_Pri),
78  threadExitEvent([this]{ exitThreads(); }, "O3CPU exit threads",
79  false, Event::CPU_Exit_Pri),
80 #ifndef NDEBUG
81  instcount(0),
82 #endif
83  removeInstsThisCycle(false),
84  fetch(this, params),
85  decode(this, params),
86  rename(this, params),
87  iew(this, params),
88  commit(this, params),
89 
90  /* It is mandatory that all SMT threads use the same renaming mode as
91  * they are sharing registers and rename */
92  vecMode(params.isa[0]->initVecRegRenameMode()),
93  regFile(params.numPhysIntRegs,
94  params.numPhysFloatRegs,
95  params.numPhysVecRegs,
96  params.numPhysVecPredRegs,
97  params.numPhysCCRegs,
98  params.isa[0]->regClasses(),
99  vecMode),
100 
101  freeList(name() + ".freelist", &regFile),
102 
103  rob(this, params),
104 
105  scoreboard(name() + ".scoreboard", regFile.totalNumPhysRegs(),
106  params.isa[0]->regClasses().at(IntRegClass).zeroReg()),
107 
108  isa(numThreads, NULL),
109 
110  timeBuffer(params.backComSize, params.forwardComSize),
111  fetchQueue(params.backComSize, params.forwardComSize),
112  decodeQueue(params.backComSize, params.forwardComSize),
113  renameQueue(params.backComSize, params.forwardComSize),
114  iewQueue(params.backComSize, params.forwardComSize),
115  activityRec(name(), NumStages,
116  params.backComSize + params.forwardComSize,
117  params.activity),
118 
119  globalSeqNum(1),
120  system(params.system),
121  lastRunningCycle(curCycle()),
122  cpuStats(this)
123 {
124  fatal_if(FullSystem && params.numThreads > 1,
125  "SMT is not supported in O3 in full system mode currently.");
126 
127  fatal_if(!FullSystem && params.numThreads < params.workload.size(),
128  "More workload items (%d) than threads (%d) on CPU %s.",
129  params.workload.size(), params.numThreads, name());
130 
131  if (!params.switched_out) {
132  _status = Running;
133  } else {
134  _status = SwitchedOut;
135  }
136 
137  if (params.checker) {
138  BaseCPU *temp_checker = params.checker;
139  checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
140  checker->setIcachePort(&fetch.getInstPort());
141  checker->setSystem(params.system);
142  } else {
143  checker = NULL;
144  }
145 
146  if (!FullSystem) {
147  thread.resize(numThreads);
148  tids.resize(numThreads);
149  }
150 
151  // The stages also need their CPU pointer setup. However this
152  // must be done at the upper level CPU because they have pointers
153  // to the upper level CPU, and not this CPU.
154 
155  // Set up Pointers to the activeThreads list for each stage
156  fetch.setActiveThreads(&activeThreads);
157  decode.setActiveThreads(&activeThreads);
158  rename.setActiveThreads(&activeThreads);
159  iew.setActiveThreads(&activeThreads);
160  commit.setActiveThreads(&activeThreads);
161 
162  // Give each of the stages the time buffer they will use.
163  fetch.setTimeBuffer(&timeBuffer);
164  decode.setTimeBuffer(&timeBuffer);
165  rename.setTimeBuffer(&timeBuffer);
166  iew.setTimeBuffer(&timeBuffer);
167  commit.setTimeBuffer(&timeBuffer);
168 
169  // Also setup each of the stages' queues.
170  fetch.setFetchQueue(&fetchQueue);
171  decode.setFetchQueue(&fetchQueue);
172  commit.setFetchQueue(&fetchQueue);
173  decode.setDecodeQueue(&decodeQueue);
174  rename.setDecodeQueue(&decodeQueue);
175  rename.setRenameQueue(&renameQueue);
176  iew.setRenameQueue(&renameQueue);
177  iew.setIEWQueue(&iewQueue);
178  commit.setIEWQueue(&iewQueue);
179  commit.setRenameQueue(&renameQueue);
180 
181  commit.setIEWStage(&iew);
182  rename.setIEWStage(&iew);
183  rename.setCommitStage(&commit);
184 
185  ThreadID active_threads;
186  if (FullSystem) {
187  active_threads = 1;
188  } else {
189  active_threads = params.workload.size();
190 
191  if (active_threads > MaxThreads) {
192  panic("Workload Size too large. Increase the 'MaxThreads' "
193  "constant in cpu/o3/limits.hh or edit your workload size.");
194  }
195  }
196 
197  // Make Sure That this a Valid Architeture
198  assert(numThreads);
199  const auto &regClasses = params.isa[0]->regClasses();
200 
201  assert(params.numPhysIntRegs >=
202  numThreads * regClasses.at(IntRegClass).size());
203  assert(params.numPhysFloatRegs >=
204  numThreads * regClasses.at(FloatRegClass).size());
205  assert(params.numPhysVecRegs >=
206  numThreads * regClasses.at(VecRegClass).size());
207  assert(params.numPhysVecPredRegs >=
208  numThreads * regClasses.at(VecPredRegClass).size());
209  assert(params.numPhysCCRegs >=
210  numThreads * regClasses.at(CCRegClass).size());
211 
212  // Just make this a warning and go ahead anyway, to keep from having to
213  // add checks everywhere.
214  warn_if(regClasses.at(CCRegClass).size() == 0 && params.numPhysCCRegs != 0,
215  "Non-zero number of physical CC regs specified, even though\n"
216  " ISA does not use them.");
217 
218  rename.setScoreboard(&scoreboard);
219  iew.setScoreboard(&scoreboard);
220 
221  // Setup the rename map for whichever stages need it.
222  for (ThreadID tid = 0; tid < numThreads; tid++) {
223  isa[tid] = dynamic_cast<TheISA::ISA *>(params.isa[tid]);
224  assert(isa[tid]);
225  assert(isa[tid]->initVecRegRenameMode() ==
226  isa[0]->initVecRegRenameMode());
227 
228  commitRenameMap[tid].init(regClasses, &regFile, &freeList, vecMode);
229  renameMap[tid].init(regClasses, &regFile, &freeList, vecMode);
230  }
231 
232  // Initialize rename map to assign physical registers to the
233  // architectural registers for active threads only.
234  for (ThreadID tid = 0; tid < active_threads; tid++) {
235  for (RegIndex ridx = 0; ridx < regClasses.at(IntRegClass).size();
236  ++ridx) {
237  // Note that we can't use the rename() method because we don't
238  // want special treatment for the zero register at this point
239  PhysRegIdPtr phys_reg = freeList.getIntReg();
240  renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
241  commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
242  }
243 
244  for (RegIndex ridx = 0; ridx < regClasses.at(FloatRegClass).size();
245  ++ridx) {
246  PhysRegIdPtr phys_reg = freeList.getFloatReg();
247  renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
248  commitRenameMap[tid].setEntry(
249  RegId(FloatRegClass, ridx), phys_reg);
250  }
251 
252  /* Here we need two 'interfaces' the 'whole register' and the
253  * 'register element'. At any point only one of them will be
254  * active. */
255  const size_t numVecs = regClasses.at(VecRegClass).size();
256  if (vecMode == enums::Full) {
257  /* Initialize the full-vector interface */
258  for (RegIndex ridx = 0; ridx < numVecs; ++ridx) {
259  RegId rid = RegId(VecRegClass, ridx);
260  PhysRegIdPtr phys_reg = freeList.getVecReg();
261  renameMap[tid].setEntry(rid, phys_reg);
262  commitRenameMap[tid].setEntry(rid, phys_reg);
263  }
264  } else {
265  /* Initialize the vector-element interface */
266  const size_t numElems = regClasses.at(VecElemClass).size();
267  const size_t elemsPerVec = numElems / numVecs;
268  for (RegIndex ridx = 0; ridx < numVecs; ++ridx) {
269  for (ElemIndex ldx = 0; ldx < elemsPerVec; ++ldx) {
270  RegId lrid = RegId(VecElemClass, ridx, ldx);
271  PhysRegIdPtr phys_elem = freeList.getVecElem();
272  renameMap[tid].setEntry(lrid, phys_elem);
273  commitRenameMap[tid].setEntry(lrid, phys_elem);
274  }
275  }
276  }
277 
278  for (RegIndex ridx = 0; ridx < regClasses.at(VecPredRegClass).size();
279  ++ridx) {
280  PhysRegIdPtr phys_reg = freeList.getVecPredReg();
281  renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg);
282  commitRenameMap[tid].setEntry(
283  RegId(VecPredRegClass, ridx), phys_reg);
284  }
285 
286  for (RegIndex ridx = 0; ridx < regClasses.at(CCRegClass).size();
287  ++ridx) {
288  PhysRegIdPtr phys_reg = freeList.getCCReg();
289  renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
290  commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
291  }
292  }
293 
294  rename.setRenameMap(renameMap);
295  commit.setRenameMap(commitRenameMap);
296  rename.setFreeList(&freeList);
297 
298  // Setup the ROB for whichever stages need it.
299  commit.setROB(&rob);
300 
301  lastActivatedCycle = 0;
302 
303  DPRINTF(O3CPU, "Creating O3CPU object.\n");
304 
305  // Setup any thread state.
306  thread.resize(numThreads);
307 
308  for (ThreadID tid = 0; tid < numThreads; ++tid) {
309  if (FullSystem) {
310  // SMT is not supported in FS mode yet.
311  assert(numThreads == 1);
312  thread[tid] = new ThreadState(this, 0, NULL);
313  } else {
314  if (tid < params.workload.size()) {
315  DPRINTF(O3CPU, "Workload[%i] process is %#x", tid,
316  thread[tid]);
317  thread[tid] = new ThreadState(this, tid, params.workload[tid]);
318  } else {
319  //Allocate Empty thread so M5 can use later
320  //when scheduling threads to CPU
321  Process* dummy_proc = NULL;
322 
323  thread[tid] = new ThreadState(this, tid, dummy_proc);
324  }
325  }
326 
328 
329  // Setup the TC that will serve as the interface to the threads/CPU.
330  auto *o3_tc = new ThreadContext;
331 
332  tc = o3_tc;
333 
334  // If we're using a checker, then the TC should be the
335  // CheckerThreadContext.
336  if (params.checker) {
337  tc = new CheckerThreadContext<ThreadContext>(o3_tc, checker);
338  }
339 
340  o3_tc->cpu = this;
341  o3_tc->thread = thread[tid];
342 
343  // Give the thread the TC.
344  thread[tid]->tc = tc;
345 
346  // Add the TC to the CPU's list of TC's.
347  threadContexts.push_back(tc);
348  }
349 
350  // O3CPU always requires an interrupt controller.
351  if (!params.switched_out && interrupts.empty()) {
352  fatal("O3CPU %s has no interrupt controller.\n"
353  "Ensure createInterruptController() is called.\n", name());
354  }
355 }
356 
357 void
359 {
361 
363  getProbeManager(), "InstAccessComplete");
366  getProbeManager(), "DataAccessComplete");
367 
372 }
373 
375  : statistics::Group(cpu),
376  ADD_STAT(timesIdled, statistics::units::Count::get(),
377  "Number of times that the entire CPU went into an idle state "
378  "and unscheduled itself"),
379  ADD_STAT(idleCycles, statistics::units::Cycle::get(),
380  "Total number of cycles that the CPU has spent unscheduled due "
381  "to idling"),
382  ADD_STAT(quiesceCycles, statistics::units::Cycle::get(),
383  "Total number of cycles that CPU has spent quiesced or waiting "
384  "for an interrupt"),
385  ADD_STAT(committedInsts, statistics::units::Count::get(),
386  "Number of Instructions Simulated"),
387  ADD_STAT(committedOps, statistics::units::Count::get(),
388  "Number of Ops (including micro ops) Simulated"),
389  ADD_STAT(cpi, statistics::units::Rate<
390  statistics::units::Cycle, statistics::units::Count>::get(),
391  "CPI: Cycles Per Instruction"),
392  ADD_STAT(totalCpi, statistics::units::Rate<
393  statistics::units::Cycle, statistics::units::Count>::get(),
394  "CPI: Total CPI of All Threads"),
395  ADD_STAT(ipc, statistics::units::Rate<
396  statistics::units::Count, statistics::units::Cycle>::get(),
397  "IPC: Instructions Per Cycle"),
398  ADD_STAT(totalIpc, statistics::units::Rate<
399  statistics::units::Count, statistics::units::Cycle>::get(),
400  "IPC: Total IPC of All Threads"),
401  ADD_STAT(intRegfileReads, statistics::units::Count::get(),
402  "Number of integer regfile reads"),
403  ADD_STAT(intRegfileWrites, statistics::units::Count::get(),
404  "Number of integer regfile writes"),
405  ADD_STAT(fpRegfileReads, statistics::units::Count::get(),
406  "Number of floating regfile reads"),
407  ADD_STAT(fpRegfileWrites, statistics::units::Count::get(),
408  "Number of floating regfile writes"),
409  ADD_STAT(vecRegfileReads, statistics::units::Count::get(),
410  "number of vector regfile reads"),
411  ADD_STAT(vecRegfileWrites, statistics::units::Count::get(),
412  "number of vector regfile writes"),
413  ADD_STAT(vecPredRegfileReads, statistics::units::Count::get(),
414  "number of predicate regfile reads"),
415  ADD_STAT(vecPredRegfileWrites, statistics::units::Count::get(),
416  "number of predicate regfile writes"),
417  ADD_STAT(ccRegfileReads, statistics::units::Count::get(),
418  "number of cc regfile reads"),
419  ADD_STAT(ccRegfileWrites, statistics::units::Count::get(),
420  "number of cc regfile writes"),
421  ADD_STAT(miscRegfileReads, statistics::units::Count::get(),
422  "number of misc regfile reads"),
423  ADD_STAT(miscRegfileWrites, statistics::units::Count::get(),
424  "number of misc regfile writes")
425 {
426  // Register any of the O3CPU's stats here.
427  timesIdled
428  .prereq(timesIdled);
429 
430  idleCycles
431  .prereq(idleCycles);
432 
435 
436  // Number of Instructions simulated
437  // --------------------------------
438  // Should probably be in Base CPU but need templated
439  // MaxThreads so put in here instead
441  .init(cpu->numThreads)
443 
445  .init(cpu->numThreads)
447 
448  cpi
449  .precision(6);
451 
452  totalCpi
453  .precision(6);
455 
456  ipc
457  .precision(6);
459 
460  totalIpc
461  .precision(6);
463 
466 
469 
472 
475 
478 
481 
484 
487 
490 
493 
496 
499 }
500 
501 void
503 {
504  DPRINTF(O3CPU, "\n\nO3CPU: Ticking main, O3CPU.\n");
505  assert(!switchedOut());
506  assert(drainState() != DrainState::Drained);
507 
510 
511 // activity = false;
512 
513  //Tick each of the stages
514  fetch.tick();
515 
516  decode.tick();
517 
518  rename.tick();
519 
520  iew.tick();
521 
522  commit.tick();
523 
524  // Now advance the time buffers
525  timeBuffer.advance();
526 
527  fetchQueue.advance();
528  decodeQueue.advance();
529  renameQueue.advance();
530  iewQueue.advance();
531 
533 
534  if (removeInstsThisCycle) {
536  }
537 
538  if (!tickEvent.scheduled()) {
539  if (_status == SwitchedOut) {
540  DPRINTF(O3CPU, "Switched out!\n");
541  // increment stat
543  } else if (!activityRec.active() || _status == Idle) {
544  DPRINTF(O3CPU, "Idle!\n");
547  } else {
549  DPRINTF(O3CPU, "Scheduling next tick!\n");
550  }
551  }
552 
553  if (!FullSystem)
555 
556  tryDrain();
557 }
558 
559 void
561 {
562  BaseCPU::init();
563 
564  for (ThreadID tid = 0; tid < numThreads; ++tid) {
565  // Set noSquashFromTC so that the CPU doesn't squash when initially
566  // setting up registers.
567  thread[tid]->noSquashFromTC = true;
568  // Initialise the ThreadContext's memory proxies
569  thread[tid]->initMemProxies(thread[tid]->getTC());
570  }
571 
572  // Clear noSquashFromTC.
573  for (int tid = 0; tid < numThreads; ++tid)
574  thread[tid]->noSquashFromTC = false;
575 
577 }
578 
579 void
581 {
583 
586  iew.startupStage();
589 }
590 
591 void
593 {
595  std::find(activeThreads.begin(), activeThreads.end(), tid);
596 
597  DPRINTF(O3CPU, "[tid:%i] Calling activate thread.\n", tid);
598  assert(!switchedOut());
599 
600  if (isActive == activeThreads.end()) {
601  DPRINTF(O3CPU, "[tid:%i] Adding to active threads list\n", tid);
602 
603  activeThreads.push_back(tid);
604  }
605 }
606 
607 void
609 {
610  // hardware transactional memory
611  // shouldn't deactivate thread in the middle of a transaction
612  assert(!commit.executingHtmTransaction(tid));
613 
614  //Remove From Active List, if Active
616  std::find(activeThreads.begin(), activeThreads.end(), tid);
617 
618  DPRINTF(O3CPU, "[tid:%i] Calling deactivate thread.\n", tid);
619  assert(!switchedOut());
620 
621  if (thread_it != activeThreads.end()) {
622  DPRINTF(O3CPU,"[tid:%i] Removing from active threads list\n",
623  tid);
624  activeThreads.erase(thread_it);
625  }
626 
627  fetch.deactivateThread(tid);
629 }
630 
631 Counter
633 {
634  Counter total(0);
635 
636  ThreadID size = thread.size();
637  for (ThreadID i = 0; i < size; i++)
638  total += thread[i]->numInst;
639 
640  return total;
641 }
642 
643 Counter
645 {
646  Counter total(0);
647 
648  ThreadID size = thread.size();
649  for (ThreadID i = 0; i < size; i++)
650  total += thread[i]->numOp;
651 
652  return total;
653 }
654 
655 void
657 {
658  assert(!switchedOut());
659 
660  // Needs to set each stage to running as well.
661  activateThread(tid);
662 
663  // We don't want to wake the CPU if it is drained. In that case,
664  // we just want to flag the thread as active and schedule the tick
665  // event from drainResume() instead.
667  return;
668 
669  // If we are time 0 or if the last activation time is in the past,
670  // schedule the next tick and wake up the fetch unit
673 
674  // Be sure to signal that there's some activity so the CPU doesn't
675  // deschedule itself.
678 
679  Cycles cycles(curCycle() - lastRunningCycle);
680  // @todo: This is an oddity that is only here to match the stats
681  if (cycles != 0)
682  --cycles;
683  cpuStats.quiesceCycles += cycles;
684 
686 
687  _status = Running;
688 
690  }
691 }
692 
693 void
695 {
696  DPRINTF(O3CPU,"[tid:%i] Suspending Thread Context.\n", tid);
697  assert(!switchedOut());
698 
699  deactivateThread(tid);
700 
701  // If this was the last thread then unschedule the tick event.
702  if (activeThreads.size() == 0) {
705  _status = Idle;
706  }
707 
708  DPRINTF(Quiesce, "Suspending Context\n");
709 
711 }
712 
713 void
715 {
716  //For now, this is the same as deallocate
717  DPRINTF(O3CPU,"[tid:%i] Halt Context called. Deallocating\n", tid);
718  assert(!switchedOut());
719 
720  deactivateThread(tid);
721  removeThread(tid);
722 
723  // If this was the last thread then unschedule the tick event.
724  if (activeThreads.size() == 0) {
725  if (tickEvent.scheduled())
726  {
728  }
730  _status = Idle;
731  }
733 }
734 
735 void
737 {
738  DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
739  // Will change now that the PC and thread state is internal to the CPU
740  // and not in the ThreadContext.
741  gem5::ThreadContext *src_tc;
742  if (FullSystem)
743  src_tc = system->threads[tid];
744  else
745  src_tc = tcBase(tid);
746 
747  //Bind Int Regs to Rename Map
748  const auto &regClasses = isa[tid]->regClasses();
749 
750  for (RegIndex idx = 0; idx < regClasses.at(IntRegClass).size(); idx++) {
751  PhysRegIdPtr phys_reg = freeList.getIntReg();
752  renameMap[tid].setEntry(RegId(IntRegClass, idx), phys_reg);
753  scoreboard.setReg(phys_reg);
754  }
755 
756  //Bind Float Regs to Rename Map
757  for (RegIndex idx = 0; idx < regClasses.at(FloatRegClass).size(); idx++) {
758  PhysRegIdPtr phys_reg = freeList.getFloatReg();
759  renameMap[tid].setEntry(RegId(FloatRegClass, idx), phys_reg);
760  scoreboard.setReg(phys_reg);
761  }
762 
763  //Bind condition-code Regs to Rename Map
764  for (RegIndex idx = 0; idx < regClasses.at(CCRegClass).size(); idx++) {
765  PhysRegIdPtr phys_reg = freeList.getCCReg();
766  renameMap[tid].setEntry(RegId(CCRegClass, idx), phys_reg);
767  scoreboard.setReg(phys_reg);
768  }
769 
770  //Copy Thread Data Into RegFile
771  //copyFromTC(tid);
772 
773  //Set PC/NPC/NNPC
774  pcState(src_tc->pcState(), tid);
775 
777 
778  activateContext(tid);
779 
780  //Reset ROB/IQ/LSQ Entries
782 }
783 
784 void
786 {
787  DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
788 
789  // Copy Thread Data From RegFile
790  // If thread is suspended, it might be re-allocated
791  // copyToTC(tid);
792 
793 
794  // @todo: 2-27-2008: Fix how we free up rename mappings
795  // here to alleviate the case for double-freeing registers
796  // in SMT workloads.
797 
798  // clear all thread-specific states in each stage of the pipeline
799  // since this thread is going to be completely removed from the CPU
800  commit.clearStates(tid);
801  fetch.clearStates(tid);
802  decode.clearStates(tid);
803  rename.clearStates(tid);
804  iew.clearStates(tid);
805 
806  // Flush out any old data from the time buffers.
807  for (int i = 0; i < timeBuffer.getSize(); ++i) {
808  timeBuffer.advance();
809  fetchQueue.advance();
810  decodeQueue.advance();
811  renameQueue.advance();
812  iewQueue.advance();
813  }
814 
815  // at this step, all instructions in the pipeline should be already
816  // either committed successfully or squashed. All thread-specific
817  // queues in the pipeline must be empty.
818  assert(iew.instQueue.getCount(tid) == 0);
819  assert(iew.ldstQueue.getCount(tid) == 0);
820  assert(commit.rob->isEmpty(tid));
821 
822  // Reset ROB/IQ/LSQ Entries
823 
824  // Commented out for now. This should be possible to do by
825  // telling all the pipeline stages to drain first, and then
826  // checking until the drain completes. Once the pipeline is
827  // drained, call resetEntries(). - 10-09-06 ktlim
828 /*
829  if (activeThreads.size() >= 1) {
830  commit.rob->resetEntries();
831  iew.resetEntries();
832  }
833 */
834 }
835 
836 void
838 {
839  const auto &regClasses = isa[tid]->regClasses();
840 
841  const size_t numVecs = regClasses.at(VecRegClass).size();
842  if (vecMode == enums::Elem) {
843  const size_t numElems = regClasses.at(VecElemClass).size();
844  const size_t elemsPerVec = numElems / numVecs;
845  for (auto v = 0; v < numVecs; v++) {
846  for (auto e = 0; e < elemsPerVec; e++) {
847  scoreboard.setReg(commitRenameMap[tid].lookup(
848  RegId(VecElemClass, v, e)));
849  }
850  }
851  } else if (vecMode == enums::Full) {
852  for (auto v = 0; v < numVecs; v++) {
853  scoreboard.setReg(commitRenameMap[tid].lookup(
854  RegId(VecRegClass, v)));
855  }
856  }
857 }
858 
859 void
861 {
862  auto pc = pcState(tid);
863 
864  // new_mode is the new vector renaming mode
865  auto new_mode = isa[tid]->vecRegRenameMode(thread[tid]->getTC());
866 
867  // We update vecMode only if there has been a change
868  if (new_mode != vecMode) {
869  vecMode = new_mode;
870 
873  renameMap[tid].switchFreeList(freelist);
874  setVectorsAsReady(tid);
875  }
876 }
877 
878 Fault
880 {
881  // Check if there are any outstanding interrupts
882  return interrupts[0]->getInterrupt();
883 }
884 
885 void
886 CPU::processInterrupts(const Fault &interrupt)
887 {
888  // Check for interrupts here. For now can copy the code that
889  // exists within isa_fullsys_traits.hh. Also assume that thread 0
890  // is the one that handles the interrupts.
891  // @todo: Possibly consolidate the interrupt checking code.
892  // @todo: Allow other threads to handle interrupts.
893 
894  assert(interrupt != NoFault);
895  interrupts[0]->updateIntrInfo();
896 
897  DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
898  trap(interrupt, 0, nullptr);
899 }
900 
901 void
902 CPU::trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
903 {
904  // Pass the thread's TC into the invoke method.
905  fault->invoke(threadContexts[tid], inst);
906 }
907 
908 void
910 {
911  thread[tid]->serialize(cp);
912 }
913 
914 void
916 {
917  thread[tid]->unserialize(cp);
918 }
919 
922 {
923  // Deschedule any power gating event (if any)
925 
926  // If the CPU isn't doing anything, then return immediately.
927  if (switchedOut())
928  return DrainState::Drained;
929 
930  DPRINTF(Drain, "Draining...\n");
931 
932  // We only need to signal a drain to the commit stage as this
933  // initiates squashing controls the draining. Once the commit
934  // stage commits an instruction where it is safe to stop, it'll
935  // squash the rest of the instructions in the pipeline and force
936  // the fetch stage to stall. The pipeline will be drained once all
937  // in-flight instructions have retired.
938  commit.drain();
939 
940  // Wake the CPU and record activity so everything can drain out if
941  // the CPU was not able to immediately drain.
942  if (!isCpuDrained()) {
943  // If a thread is suspended, wake it up so it can be drained
944  for (auto t : threadContexts) {
945  if (t->status() == gem5::ThreadContext::Suspended){
946  DPRINTF(Drain, "Currently suspended so activate %i \n",
947  t->threadId());
948  t->activate();
949  // As the thread is now active, change the power state as well
950  activateContext(t->threadId());
951  }
952  }
953 
954  wakeCPU();
956 
957  DPRINTF(Drain, "CPU not drained\n");
958 
959  return DrainState::Draining;
960  } else {
961  DPRINTF(Drain, "CPU is already drained\n");
962  if (tickEvent.scheduled())
964 
965  // Flush out any old data from the time buffers. In
966  // particular, there might be some data in flight from the
967  // fetch stage that isn't visible in any of the CPU buffers we
968  // test in isCpuDrained().
969  for (int i = 0; i < timeBuffer.getSize(); ++i) {
970  timeBuffer.advance();
971  fetchQueue.advance();
972  decodeQueue.advance();
973  renameQueue.advance();
974  iewQueue.advance();
975  }
976 
978  return DrainState::Drained;
979  }
980 }
981 
982 bool
984 {
986  return false;
987 
988  if (tickEvent.scheduled())
990 
991  DPRINTF(Drain, "CPU done draining, processing drain event\n");
992  signalDrainDone();
993 
994  return true;
995 }
996 
997 void
999 {
1000  assert(isCpuDrained());
1006 }
1007 
1008 bool
1010 {
1011  bool drained(true);
1012 
1013  if (!instList.empty() || !removeList.empty()) {
1014  DPRINTF(Drain, "Main CPU structures not drained.\n");
1015  drained = false;
1016  }
1017 
1018  if (!fetch.isDrained()) {
1019  DPRINTF(Drain, "Fetch not drained.\n");
1020  drained = false;
1021  }
1022 
1023  if (!decode.isDrained()) {
1024  DPRINTF(Drain, "Decode not drained.\n");
1025  drained = false;
1026  }
1027 
1028  if (!rename.isDrained()) {
1029  DPRINTF(Drain, "Rename not drained.\n");
1030  drained = false;
1031  }
1032 
1033  if (!iew.isDrained()) {
1034  DPRINTF(Drain, "IEW not drained.\n");
1035  drained = false;
1036  }
1037 
1038  if (!commit.isDrained()) {
1039  DPRINTF(Drain, "Commit not drained.\n");
1040  drained = false;
1041  }
1042 
1043  return drained;
1044 }
1045 
1047 
1048 void
1050 {
1051  if (switchedOut())
1052  return;
1053 
1054  DPRINTF(Drain, "Resuming...\n");
1055  verifyMemoryMode();
1056 
1057  fetch.drainResume();
1058  commit.drainResume();
1059 
1060  _status = Idle;
1061  for (ThreadID i = 0; i < thread.size(); i++) {
1063  DPRINTF(Drain, "Activating thread: %i\n", i);
1064  activateThread(i);
1065  _status = Running;
1066  }
1067  }
1068 
1069  assert(!tickEvent.scheduled());
1070  if (_status == Running)
1072 
1073  // Reschedule any power gating event (if any)
1075 }
1076 
1077 void
1079 {
1080  DPRINTF(O3CPU, "Switching out\n");
1082 
1083  activityRec.reset();
1084 
1085  _status = SwitchedOut;
1086 
1087  if (checker)
1088  checker->switchOut();
1089 }
1090 
1091 void
1093 {
1094  BaseCPU::takeOverFrom(oldCPU);
1095 
1096  fetch.takeOverFrom();
1097  decode.takeOverFrom();
1098  rename.takeOverFrom();
1099  iew.takeOverFrom();
1100  commit.takeOverFrom();
1101 
1102  assert(!tickEvent.scheduled());
1103 
1104  auto *oldO3CPU = dynamic_cast<CPU *>(oldCPU);
1105  if (oldO3CPU)
1106  globalSeqNum = oldO3CPU->globalSeqNum;
1107 
1109  _status = Idle;
1110 }
1111 
1112 void
1114 {
1115  if (!system->isTimingMode()) {
1116  fatal("The O3 CPU requires the memory system to be in "
1117  "'timing' mode.\n");
1118  }
1119 }
1120 
1121 RegVal
1122 CPU::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1123 {
1124  return isa[tid]->readMiscRegNoEffect(misc_reg);
1125 }
1126 
1127 RegVal
1128 CPU::readMiscReg(int misc_reg, ThreadID tid)
1129 {
1131  return isa[tid]->readMiscReg(misc_reg);
1132 }
1133 
1134 void
1136 {
1137  isa[tid]->setMiscRegNoEffect(misc_reg, val);
1138 }
1139 
1140 void
1141 CPU::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
1142 {
1144  isa[tid]->setMiscReg(misc_reg, val);
1145 }
1146 
1147 RegVal
1149 {
1151  return regFile.readIntReg(phys_reg);
1152 }
1153 
1154 RegVal
1156 {
1158  return regFile.readFloatReg(phys_reg);
1159 }
1160 
1163 {
1165  return regFile.readVecReg(phys_reg);
1166 }
1167 
1170 {
1172  return regFile.getWritableVecReg(phys_reg);
1173 }
1174 
1175 const TheISA::VecElem&
1177 {
1179  return regFile.readVecElem(phys_reg);
1180 }
1181 
1184 {
1186  return regFile.readVecPredReg(phys_reg);
1187 }
1188 
1191 {
1193  return regFile.getWritableVecPredReg(phys_reg);
1194 }
1195 
1196 RegVal
1198 {
1200  return regFile.readCCReg(phys_reg);
1201 }
1202 
1203 void
1205 {
1207  regFile.setIntReg(phys_reg, val);
1208 }
1209 
1210 void
1212 {
1214  regFile.setFloatReg(phys_reg, val);
1215 }
1216 
1217 void
1219 {
1221  regFile.setVecReg(phys_reg, val);
1222 }
1223 
1224 void
1226 {
1228  regFile.setVecElem(phys_reg, val);
1229 }
1230 
1231 void
1234 {
1236  regFile.setVecPredReg(phys_reg, val);
1237 }
1238 
1239 void
1241 {
1243  regFile.setCCReg(phys_reg, val);
1244 }
1245 
1246 RegVal
1248 {
1250  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1251  RegId(IntRegClass, reg_idx));
1252 
1253  return regFile.readIntReg(phys_reg);
1254 }
1255 
1256 RegVal
1258 {
1260  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1261  RegId(FloatRegClass, reg_idx));
1262 
1263  return regFile.readFloatReg(phys_reg);
1264 }
1265 
1267 CPU::readArchVecReg(int reg_idx, ThreadID tid) const
1268 {
1269  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1270  RegId(VecRegClass, reg_idx));
1271  return readVecReg(phys_reg);
1272 }
1273 
1276 {
1277  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1278  RegId(VecRegClass, reg_idx));
1279  return getWritableVecReg(phys_reg);
1280 }
1281 
1282 const TheISA::VecElem&
1284  const RegIndex& reg_idx, const ElemIndex& ldx, ThreadID tid) const
1285 {
1286  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1287  RegId(VecElemClass, reg_idx, ldx));
1288  return readVecElem(phys_reg);
1289 }
1290 
1292 CPU::readArchVecPredReg(int reg_idx, ThreadID tid) const
1293 {
1294  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1295  RegId(VecPredRegClass, reg_idx));
1296  return readVecPredReg(phys_reg);
1297 }
1298 
1301 {
1302  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1303  RegId(VecPredRegClass, reg_idx));
1304  return getWritableVecPredReg(phys_reg);
1305 }
1306 
1307 RegVal
1308 CPU::readArchCCReg(int reg_idx, ThreadID tid)
1309 {
1311  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1312  RegId(CCRegClass, reg_idx));
1313 
1314  return regFile.readCCReg(phys_reg);
1315 }
1316 
1317 void
1319 {
1321  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1322  RegId(IntRegClass, reg_idx));
1323 
1324  regFile.setIntReg(phys_reg, val);
1325 }
1326 
1327 void
1329 {
1331  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1332  RegId(FloatRegClass, reg_idx));
1333 
1334  regFile.setFloatReg(phys_reg, val);
1335 }
1336 
1337 void
1339  ThreadID tid)
1340 {
1341  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1342  RegId(VecRegClass, reg_idx));
1343  setVecReg(phys_reg, val);
1344 }
1345 
1346 void
1347 CPU::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1348  const TheISA::VecElem& val, ThreadID tid)
1349 {
1350  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1351  RegId(VecElemClass, reg_idx, ldx));
1352  setVecElem(phys_reg, val);
1353 }
1354 
1355 void
1358 {
1359  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1360  RegId(VecPredRegClass, reg_idx));
1361  setVecPredReg(phys_reg, val);
1362 }
1363 
1364 void
1366 {
1368  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1369  RegId(CCRegClass, reg_idx));
1370 
1371  regFile.setCCReg(phys_reg, val);
1372 }
1373 
1376 {
1377  return commit.pcState(tid);
1378 }
1379 
1380 void
1382 {
1383  commit.pcState(val, tid);
1384 }
1385 
1386 Addr
1388 {
1389  return commit.instAddr(tid);
1390 }
1391 
1392 Addr
1394 {
1395  return commit.nextInstAddr(tid);
1396 }
1397 
1398 MicroPC
1400 {
1401  return commit.microPC(tid);
1402 }
1403 
1404 void
1406 {
1407  thread[tid]->noSquashFromTC = true;
1408  commit.generateTCEvent(tid);
1409 }
1410 
1413 {
1414  instList.push_back(inst);
1415 
1416  return --(instList.end());
1417 }
1418 
1419 void
1421 {
1422  // Keep an instruction count.
1423  if (!inst->isMicroop() || inst->isLastMicroop()) {
1424  thread[tid]->numInst++;
1425  thread[tid]->threadStats.numInsts++;
1426  cpuStats.committedInsts[tid]++;
1427 
1428  // Check for instruction-count-based events.
1429  thread[tid]->comInstEventQueue.serviceEvents(thread[tid]->numInst);
1430  }
1431  thread[tid]->numOp++;
1432  thread[tid]->threadStats.numOps++;
1433  cpuStats.committedOps[tid]++;
1434 
1435  probeInstCommit(inst->staticInst, inst->instAddr());
1436 }
1437 
1438 void
1440 {
1441  DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1442  "[sn:%lli]\n",
1443  inst->threadNumber, inst->pcState(), inst->seqNum);
1444 
1445  removeInstsThisCycle = true;
1446 
1447  // Remove the front instruction.
1448  removeList.push(inst->getInstListIt());
1449 }
1450 
1451 void
1453 {
1454  DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1455  " list.\n", tid);
1456 
1457  ListIt end_it;
1458 
1459  bool rob_empty = false;
1460 
1461  if (instList.empty()) {
1462  return;
1463  } else if (rob.isEmpty(tid)) {
1464  DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1465  end_it = instList.begin();
1466  rob_empty = true;
1467  } else {
1468  end_it = (rob.readTailInst(tid))->getInstListIt();
1469  DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1470  }
1471 
1472  removeInstsThisCycle = true;
1473 
1474  ListIt inst_it = instList.end();
1475 
1476  inst_it--;
1477 
1478  // Walk through the instruction list, removing any instructions
1479  // that were inserted after the given instruction iterator, end_it.
1480  while (inst_it != end_it) {
1481  assert(!instList.empty());
1482 
1483  squashInstIt(inst_it, tid);
1484 
1485  inst_it--;
1486  }
1487 
1488  // If the ROB was empty, then we actually need to remove the first
1489  // instruction as well.
1490  if (rob_empty) {
1491  squashInstIt(inst_it, tid);
1492  }
1493 }
1494 
1495 void
1497 {
1498  assert(!instList.empty());
1499 
1500  removeInstsThisCycle = true;
1501 
1502  ListIt inst_iter = instList.end();
1503 
1504  inst_iter--;
1505 
1506  DPRINTF(O3CPU, "Deleting instructions from instruction "
1507  "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1508  tid, seq_num, (*inst_iter)->seqNum);
1509 
1510  while ((*inst_iter)->seqNum > seq_num) {
1511 
1512  bool break_loop = (inst_iter == instList.begin());
1513 
1514  squashInstIt(inst_iter, tid);
1515 
1516  inst_iter--;
1517 
1518  if (break_loop)
1519  break;
1520  }
1521 }
1522 
1523 void
1524 CPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1525 {
1526  if ((*instIt)->threadNumber == tid) {
1527  DPRINTF(O3CPU, "Squashing instruction, "
1528  "[tid:%i] [sn:%lli] PC %s\n",
1529  (*instIt)->threadNumber,
1530  (*instIt)->seqNum,
1531  (*instIt)->pcState());
1532 
1533  // Mark it as squashed.
1534  (*instIt)->setSquashed();
1535 
1536  // @todo: Formulate a consistent method for deleting
1537  // instructions from the instruction list
1538  // Remove the instruction from the list.
1539  removeList.push(instIt);
1540  }
1541 }
1542 
1543 void
1545 {
1546  while (!removeList.empty()) {
1547  DPRINTF(O3CPU, "Removing instruction, "
1548  "[tid:%i] [sn:%lli] PC %s\n",
1549  (*removeList.front())->threadNumber,
1550  (*removeList.front())->seqNum,
1551  (*removeList.front())->pcState());
1552 
1553  instList.erase(removeList.front());
1554 
1555  removeList.pop();
1556  }
1557 
1558  removeInstsThisCycle = false;
1559 }
1560 /*
1561 void
1562 CPU::removeAllInsts()
1563 {
1564  instList.clear();
1565 }
1566 */
1567 void
1569 {
1570  int num = 0;
1571 
1572  ListIt inst_list_it = instList.begin();
1573 
1574  cprintf("Dumping Instruction List\n");
1575 
1576  while (inst_list_it != instList.end()) {
1577  cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1578  "Squashed:%i\n\n",
1579  num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1580  (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1581  (*inst_list_it)->isSquashed());
1582  inst_list_it++;
1583  ++num;
1584  }
1585 }
1586 /*
1587 void
1588 CPU::wakeDependents(const DynInstPtr &inst)
1589 {
1590  iew.wakeDependents(inst);
1591 }
1592 */
1593 void
1595 {
1596  if (activityRec.active() || tickEvent.scheduled()) {
1597  DPRINTF(Activity, "CPU already running.\n");
1598  return;
1599  }
1600 
1601  DPRINTF(Activity, "Waking up CPU\n");
1602 
1603  Cycles cycles(curCycle() - lastRunningCycle);
1604  // @todo: This is an oddity that is only here to match the stats
1605  if (cycles > 1) {
1606  --cycles;
1607  cpuStats.idleCycles += cycles;
1608  baseStats.numCycles += cycles;
1609  }
1610 
1612 }
1613 
1614 void
1616 {
1618  return;
1619 
1620  wakeCPU();
1621 
1622  DPRINTF(Quiesce, "Suspended Processor woken\n");
1623  threadContexts[tid]->activate();
1624 }
1625 
1626 ThreadID
1628 {
1629  for (ThreadID tid = 0; tid < numThreads; tid++) {
1630  if (!tids[tid]) {
1631  tids[tid] = true;
1632  return tid;
1633  }
1634  }
1635 
1636  return InvalidThreadID;
1637 }
1638 
1639 void
1641 {
1642  if (activeThreads.size() > 1) {
1643  //DEFAULT TO ROUND ROBIN SCHEME
1644  //e.g. Move highest priority to end of thread list
1645  std::list<ThreadID>::iterator list_begin = activeThreads.begin();
1646 
1647  unsigned high_thread = *list_begin;
1648 
1649  activeThreads.erase(list_begin);
1650 
1651  activeThreads.push_back(high_thread);
1652  }
1653 }
1654 
1655 void
1657 {
1658  DPRINTF(O3CPU, "Thread %d is inserted to exitingThreads list\n", tid);
1659 
1660  // the thread trying to exit can't be already halted
1661  assert(tcBase(tid)->status() != gem5::ThreadContext::Halted);
1662 
1663  // make sure the thread has not been added to the list yet
1664  assert(exitingThreads.count(tid) == 0);
1665 
1666  // add the thread to exitingThreads list to mark that this thread is
1667  // trying to exit. The boolean value in the pair denotes if a thread is
1668  // ready to exit. The thread is not ready to exit until the corresponding
1669  // exit trap event is processed in the future. Until then, it'll be still
1670  // an active thread that is trying to exit.
1671  exitingThreads.emplace(std::make_pair(tid, false));
1672 }
1673 
1674 bool
1676 {
1677  return exitingThreads.count(tid) == 1;
1678 }
1679 
1680 void
1682 {
1683  assert(exitingThreads.count(tid) == 1);
1684 
1685  // exit trap event has been processed. Now, the thread is ready to exit
1686  // and be removed from the CPU.
1687  exitingThreads[tid] = true;
1688 
1689  // we schedule a threadExitEvent in the next cycle to properly clean
1690  // up the thread's states in the pipeline. threadExitEvent has lower
1691  // priority than tickEvent, so the cleanup will happen at the very end
1692  // of the next cycle after all pipeline stages complete their operations.
1693  // We want all stages to complete squashing instructions before doing
1694  // the cleanup.
1695  if (!threadExitEvent.scheduled()) {
1697  }
1698 }
1699 
1700 void
1702 {
1703  // there must be at least one thread trying to exit
1704  assert(exitingThreads.size() > 0);
1705 
1706  // terminate all threads that are ready to exit
1707  auto it = exitingThreads.begin();
1708  while (it != exitingThreads.end()) {
1709  ThreadID thread_id = it->first;
1710  bool readyToExit = it->second;
1711 
1712  if (readyToExit) {
1713  DPRINTF(O3CPU, "Exiting thread %d\n", thread_id);
1714  haltContext(thread_id);
1716  it = exitingThreads.erase(it);
1717  } else {
1718  it++;
1719  }
1720  }
1721 }
1722 
1723 void
1724 CPU::htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
1725  HtmFailureFaultCause cause)
1726 {
1727  const Addr addr = 0x0ul;
1728  const int size = 8;
1729  const Request::Flags flags =
1731 
1732  // O3-specific actions
1735 
1736  // notify l1 d-cache (ruby) that core has aborted transaction
1737  RequestPtr req =
1738  std::make_shared<Request>(addr, size, flags, _dataRequestorId);
1739 
1740  req->taskId(taskId());
1741  req->setContext(thread[tid]->contextId());
1742  req->setHtmAbortCause(cause);
1743 
1744  assert(req->isHTMAbort());
1745 
1746  PacketPtr abort_pkt = Packet::createRead(req);
1747  uint8_t *memData = new uint8_t[8];
1748  assert(memData);
1749  abort_pkt->dataStatic(memData);
1750  abort_pkt->setHtmTransactional(htm_uid);
1751 
1752  // TODO include correct error handling here
1753  if (!iew.ldstQueue.getDataPort().sendTimingReq(abort_pkt)) {
1754  panic("HTM abort signal was not sent to the memory subsystem.");
1755  }
1756 }
1757 
1758 } // namespace o3
1759 } // namespace gem5
gem5::o3::Rename::isDrained
bool isDrained() const
Has the stage drained?
Definition: rename.cc:305
gem5::o3::CPU::vecMode
enums::VecRegRenameMode vecMode
The rename mode of the vector registers.
Definition: cpu.hh:498
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::o3::CPU::setArchIntReg
void setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
Architectural register accessors.
Definition: cpu.cc:1318
gem5::o3::UnifiedRenameMap::switchMode
void switchMode(VecMode newVecMode)
Set vector mode to Full or Elem.
Definition: rename_map.cc:166
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::o3::PhysRegFile::setCCReg
void setCCReg(PhysRegIdPtr phys_reg, RegVal val)
Sets a condition-code register to the given value.
Definition: regfile.hh:340
gem5::o3::CPU::addThreadToExitingList
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
Definition: cpu.cc:1656
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::o3::PhysRegFile::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(PhysRegIdPtr phys_reg)
Reads a vector register for modification.
Definition: regfile.hh:222
gem5::o3::Commit::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: commit.cc:400
gem5::o3::CPU::dumpInsts
void dumpInsts()
Debug function to print all instructions on the list.
Definition: cpu.cc:1568
gem5::o3::CPU::ppDataAccessComplete
ProbePointArg< std::pair< DynInstPtr, PacketPtr > > * ppDataAccessComplete
Definition: cpu.hh:174
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::o3::CPU::readVecElem
const TheISA::VecElem & readVecElem(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1176
gem5::o3::CPU::isCpuDrained
bool isCpuDrained() const
Check if a system is in a drained state.
Definition: cpu.cc:1009
gem5::o3::CPU::tids
std::vector< ThreadID > tids
Available thread ids in the cpu.
Definition: cpu.hh:623
gem5::o3::CPU::setArchVecElem
void setArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, const TheISA::VecElem &val, ThreadID tid)
Definition: cpu.cc:1347
gem5::o3::CPU::CPUStats::miscRegfileWrites
statistics::Scalar miscRegfileWrites
Definition: cpu.hh:705
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:108
gem5::BaseCPU::switchedOut
bool switchedOut() const
Determine if the CPU is switched out.
Definition: base.hh:357
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::o3::CPU::removeList
std::queue< ListIt > removeList
List of all the instructions that will be removed at the end of this cycle.
Definition: cpu.hh:467
gem5::o3::Rename::tick
void tick()
Ticks rename, which processes all input signals and attempts to rename as many instructions as possib...
Definition: rename.cc:389
gem5::o3::CPU::setVecElem
void setVecElem(PhysRegIdPtr reg_idx, const TheISA::VecElem &val)
Definition: cpu.cc:1225
gem5::BaseCPU::interrupts
std::vector< BaseInterrupts * > interrupts
Definition: base.hh:225
gem5::o3::Commit::regProbePoints
void regProbePoints()
Registers probes.
Definition: commit.cc:139
gem5::o3::Rename::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: rename.cc:325
gem5::o3::CPU::CPUStats::fpRegfileWrites
statistics::Scalar fpRegfileWrites
Definition: cpu.hh:693
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::CPU::readCCReg
RegVal readCCReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1197
gem5::o3::CPU::removeInstsThisCycle
bool removeInstsThisCycle
Records if instructions need to be removed this cycle due to being retired or squashed.
Definition: cpu.hh:479
gem5::o3::PhysRegFile::readVecReg
const TheISA::VecRegContainer & readVecReg(PhysRegIdPtr phys_reg) const
Reads a vector register.
Definition: regfile.hh:209
gem5::o3::CPU::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: cpu.hh:98
gem5::o3::CPU::cpuStats
gem5::o3::CPU::CPUStats cpuStats
gem5::Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:135
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::o3::CPU::globalSeqNum
InstSeqNum globalSeqNum
The global sequence number counter.
Definition: cpu.hh:596
gem5::o3::CPU::removeInstsUntil
void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
Remove all instructions younger than the given sequence number.
Definition: cpu.cc:1496
gem5::o3::ROB::readTailInst
DynInstPtr readTailInst(ThreadID tid)
Returns pointer to the tail instruction within the ROB.
Definition: rob.cc:516
system.hh
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::o3::CPU::CPU
CPU(const O3CPUParams &params)
Constructs a CPU with the given parameters.
Definition: cpu.cc:73
gem5::o3::Commit::drain
void drain()
Initializes the draining of commit.
Definition: commit.cc:348
gem5::o3::PhysRegFile::readVecElem
const TheISA::VecElem & readVecElem(PhysRegIdPtr phys_reg) const
Reads a vector element.
Definition: regfile.hh:230
gem5::Clocked::curCycle
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Definition: clocked_object.hh:195
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:121
gem5::BaseCPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: base.cc:315
gem5::o3::PhysRegFile::setVecPredReg
void setVecPredReg(PhysRegIdPtr phys_reg, const TheISA::VecPredRegContainer &val)
Sets a predicate register to the given value.
Definition: regfile.hh:327
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::o3::CPU::regFile
PhysRegFile regFile
The register file.
Definition: cpu.hh:501
gem5::Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:324
gem5::o3::PhysRegFile::readFloatReg
RegVal readFloatReg(PhysRegIdPtr phys_reg) const
Definition: regfile.hh:195
gem5::o3::LSQ::getCount
int getCount()
Returns the number of instructions in all of the queues.
Definition: lsq.cc:464
gem5::o3::CPU::decode
Decode decode
The decode stage.
Definition: cpu.hh:486
gem5::o3::CPU::CPUStats::ccRegfileWrites
statistics::Scalar ccRegfileWrites
Definition: cpu.hh:702
gem5::o3::CPU::activeThreads
std::list< ThreadID > activeThreads
Active Threads List.
Definition: cpu.hh:516
gem5::o3::Commit::setThreads
void setThreads(std::vector< ThreadState * > &threads)
Sets the list of threads.
Definition: commit.cc:248
gem5::Request::HTM_ABORT
@ HTM_ABORT
The request aborts a HTM transaction.
Definition: request.hh:214
gem5::o3::CPU::freeList
UnifiedFreeList freeList
The free list.
Definition: cpu.hh:504
gem5::o3::PhysRegFile::readIntReg
RegVal readIntReg(PhysRegIdPtr phys_reg) const
Reads an integer register.
Definition: regfile.hh:185
gem5::o3::CPU::processInterrupts
void processInterrupts(const Fault &interrupt)
Processes any an interrupt fault.
Definition: cpu.cc:886
gem5::o3::Decode::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: decode.cc:98
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::o3::Fetch::drainStall
void drainStall(ThreadID tid)
Stall the fetch stage after reaching a safe drain point.
Definition: fetch.cc:459
gem5::o3::CPU::readArchFloatReg
RegVal readArchFloatReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1257
gem5::o3::CPU::CPUStats::quiesceCycles
statistics::Scalar quiesceCycles
Stat for total number of cycles the CPU spends descheduled due to a quiesce operation or waiting for ...
Definition: cpu.hh:673
gem5::o3::CPU::getInterrupts
Fault getInterrupts()
Returns the Fault for any valid interrupt.
Definition: cpu.cc:879
gem5::o3::CPU::squashInstIt
void squashInstIt(const ListIt &instIt, ThreadID tid)
Removes the instruction pointed to by the iterator.
Definition: cpu.cc:1524
gem5::BaseCPU::updateCycleCounters
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
Definition: base.hh:523
gem5::o3::Fetch::wakeFromQuiesce
void wakeFromQuiesce()
Tells fetch to wake up from a quiesce instruction.
Definition: fetch.cc:468
cur_tick.hh
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::o3::IEW::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: iew.cc:392
gem5::o3::CPU::readArchCCReg
RegVal readArchCCReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1308
gem5::o3::CPU::CPUStats::miscRegfileReads
statistics::Scalar miscRegfileReads
Definition: cpu.hh:704
gem5::o3::Commit::startupStage
void startupStage()
Initializes stage by sending back the number of free entries.
Definition: commit.cc:314
gem5::BaseCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:272
gem5::o3::CPU::CPUStats::intRegfileReads
statistics::Scalar intRegfileReads
Definition: cpu.hh:689
gem5::o3::IEW::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: iew.cc:293
gem5::o3::CPU::_status
Status _status
Overall CPU status.
Definition: cpu.hh:116
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::Packet::setHtmTransactional
void setHtmTransactional(uint64_t val)
Stipulates that this packet/request originates in the CPU executing in transactional mode,...
Definition: packet.cc:521
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::o3::CPU::timeBuffer
TimeBuffer< TimeStruct > timeBuffer
The main time buffer to do backwards communication.
Definition: cpu.hh:546
gem5::ThreadContext::setStatus
virtual void setStatus(Status new_status)=0
gem5::ActivityRecorder::advance
void advance()
Advances the activity buffer, decrementing the activityCount if active communication just left the ti...
Definition: activity.cc:71
gem5::o3::CPU::removeThread
void removeThread(ThreadID tid)
Remove all of a thread's context from CPU.
Definition: cpu.cc:785
gem5::Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:117
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:122
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::o3::CPU::htmSendAbortSignal
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)
Definition: cpu.cc:1724
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::o3::CPU::setVecReg
void setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer &val)
Definition: cpu.cc:1218
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::o3::CPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1141
dyn_inst.hh
gem5::o3::CPU::CPUStats::totalIpc
statistics::Formula totalIpc
Stat for the total IPC.
Definition: cpu.hh:686
gem5::o3::CPU::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(PhysRegIdPtr reg_idx)
Definition: cpu.cc:1190
gem5::o3::CPU::renameMap
UnifiedRenameMap renameMap[MaxThreads]
The rename map.
Definition: cpu.hh:507
gem5::o3::Fetch::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: fetch.cc:299
gem5::o3::CPU::instList
std::list< DynInstPtr > instList
List of all the instructions in flight.
Definition: cpu.hh:462
gem5::o3::PhysRegFile::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(PhysRegIdPtr phys_reg)
Definition: regfile.hh:256
gem5::o3::Fetch::isDrained
bool isDrained() const
Has the stage drained?
Definition: fetch.cc:421
gem5::o3::CPU::verifyMemoryMode
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
Definition: cpu.cc:1113
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::o3::CPU::deactivateThread
void deactivateThread(ThreadID tid)
Remove Thread from Active Threads List.
Definition: cpu.cc:608
gem5::o3::CPU::CPUStats::intRegfileWrites
statistics::Scalar intRegfileWrites
Definition: cpu.hh:690
gem5::o3::CPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition: cpu.cc:915
gem5::EventBase::CPU_Exit_Pri
static const Priority CPU_Exit_Pri
If we want to exit a thread in a CPU, it comes after CPU_Tick_Pri.
Definition: eventq.hh:211
gem5::BaseCPU::schedulePowerGatingEvent
void schedulePowerGatingEvent()
Definition: base.cc:460
gem5::o3::CPU::readFloatReg
RegVal readFloatReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1155
gem5::o3::CPU::CPUStats::cpi
statistics::Formula cpi
Stat for the CPI per thread.
Definition: cpu.hh:680
gem5::o3::CPU::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: cpu.cc:998
gem5::o3::CPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: cpu.cc:909
gem5::o3::CPU::cleanUpRemovedInsts
void cleanUpRemovedInsts()
Cleans up all instructions on the remove list.
Definition: cpu.cc:1544
gem5::o3::Commit::deactivateThread
void deactivateThread(ThreadID tid)
Deschedules a thread from scheduling.
Definition: commit.cc:415
gem5::o3::ROB::resetEntries
void resetEntries()
Re-adjust ROB partitioning.
Definition: rob.cc:148
gem5::o3::CPU::iewQueue
TimeBuffer< IEWStruct > iewQueue
The IEW stage's instruction queue.
Definition: cpu.hh:558
gem5::o3::CPU::ppInstAccessComplete
ProbePointArg< PacketPtr > * ppInstAccessComplete
Definition: cpu.hh:173
gem5::o3::IEW::startupStage
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
Definition: iew.cc:270
gem5::o3::PhysRegFile::setVecElem
void setVecElem(PhysRegIdPtr phys_reg, const TheISA::VecElem val)
Sets a vector register to the given value.
Definition: regfile.hh:314
gem5::RefCountingPtr< StaticInst >
gem5::o3::LSQ::resetHtmStartsStops
void resetHtmStartsStops(ThreadID tid)
Definition: lsq.cc:369
gem5::o3::CPU::checker
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
Definition: cpu.hh:602
gem5::o3::CPU::unscheduleTickEvent
void unscheduleTickEvent()
Unschedule tick event, regardless of its current state.
Definition: cpu.hh:136
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::CPU::totalInsts
Counter totalInsts() const override
Count the Total Instructions Committed in the CPU.
Definition: cpu.cc:632
gem5::o3::Fetch::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: fetch.cc:404
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
gem5::PhysRegIdPtr
PhysRegId * PhysRegIdPtr
Definition: reg_class.hh:308
gem5::o3::CPU::CPUStats::committedInsts
statistics::Vector committedInsts
Stat for the number of committed instructions per thread.
Definition: cpu.hh:675
gem5::o3::CPU::CPUStats::idleCycles
statistics::Scalar idleCycles
Stat for total number of cycles the CPU spends descheduled.
Definition: cpu.hh:670
gem5::o3::CPU::setArchFloatReg
void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
Definition: cpu.cc:1328
gem5::o3::IEW::instQueue
InstructionQueue instQueue
Instruction queue.
Definition: iew.hh:355
gem5::o3::CPU::decodeQueue
TimeBuffer< DecodeStruct > decodeQueue
The decode stage's instruction queue.
Definition: cpu.hh:552
gem5::Packet::dataStatic
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
Definition: packet.hh:1134
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::o3::Fetch::drainResume
void drainResume()
Resume after a drain.
Definition: fetch.cc:395
gem5::o3::CPU::CPUStats::totalCpi
statistics::Formula totalCpi
Stat for the total CPI.
Definition: cpu.hh:682
gem5::o3::CPU::setArchCCReg
void setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
Definition: cpu.cc:1365
gem5::BaseCPU::deschedulePowerGatingEvent
void deschedulePowerGatingEvent()
Definition: base.cc:452
gem5::o3::Rename::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: rename.cc:227
gem5::Flags< FlagsType >
gem5::o3::CPU::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(PhysRegIdPtr reg_idx)
Read physical vector register for modification.
Definition: cpu.cc:1169
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::o3::Commit::generateTCEvent
void generateTCEvent(ThreadID tid)
Records that commit needs to initiate a squash due to an external state update through the TC.
Definition: commit.cc:524
gem5::o3::CPU::setArchVecReg
void setArchVecReg(int reg_idx, const TheISA::VecRegContainer &val, ThreadID tid)
Definition: cpu.cc:1338
gem5::BaseCPU::suspendContext
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
Definition: base.cc:502
gem5::BaseCPU::baseStats
gem5::BaseCPU::BaseCPUStats baseStats
gem5::o3::Decode::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: decode.hh:132
gem5::o3::Decode::tick
void tick()
Ticks decode, processing all input signals and decoding as many instructions as possible.
Definition: decode.cc:544
gem5::o3::CPU::readArchVecPredReg
const TheISA::VecPredRegContainer & readArchVecPredReg(int reg_idx, ThreadID tid) const
Definition: cpu.cc:1292
gem5::BaseCPU::taskId
uint32_t taskId() const
Get cpu task id.
Definition: base.hh:212
gem5::BaseCPU::_dataRequestorId
RequestorID _dataRequestorId
data side request id that must be placed in all requests
Definition: base.hh:132
gem5::o3::CPU::tryDrain
bool tryDrain()
Check if the pipeline has drained and signal drain done.
Definition: cpu.cc:983
gem5::o3::CPU::wakeup
virtual void wakeup(ThreadID tid) override
Definition: cpu.cc:1615
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::CPU::insertThread
void insertThread(ThreadID tid)
Setup CPU to insert a thread's context.
Definition: cpu.cc:736
gem5::o3::IEW::isDrained
bool isDrained() const
Has the stage drained?
Definition: iew.cc:355
gem5::o3::CPU::setCCReg
void setCCReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1240
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::o3::CPU::CPUStats::vecPredRegfileReads
statistics::Scalar vecPredRegfileReads
Definition: cpu.hh:698
gem5::o3::CPU::setIntReg
void setIntReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1204
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::CPU::scheduleTickEvent
void scheduleTickEvent(Cycles delay)
Schedule tick event, regardless of its current state.
Definition: cpu.hh:127
gem5::o3::CPU::totalOps
Counter totalOps() const override
Count the Total Ops (including micro ops) committed in the CPU.
Definition: cpu.cc:644
gem5::o3::CPU::suspendContext
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
Definition: cpu.cc:694
gem5::o3::Commit::isDrained
bool isDrained() const
Has the stage drained?
Definition: commit.cc:373
gem5::o3::CPU::readArchVecElem
const TheISA::VecElem & readArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const
Definition: cpu.cc:1283
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:112
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::CPU::setVectorsAsReady
void setVectorsAsReady(ThreadID tid)
Mark vector fields in scoreboard as ready right after switching vector mode, since software may read ...
Definition: cpu.cc:837
gem5::o3::Commit::rob
ROB * rob
ROB interface.
Definition: commit.hh:352
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::o3::Scoreboard::setReg
void setReg(PhysRegIdPtr phys_reg)
Sets the register as ready.
Definition: scoreboard.hh:105
gem5::o3::CPU::fetch
Fetch fetch
The fetch stage.
Definition: cpu.hh:483
gem5::o3::Commit::microPC
Addr microPC(ThreadID tid)
Reads the micro PC of a specific thread.
Definition: commit.hh:322
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::BaseCPU::BaseCPUStats::numCycles
statistics::Scalar numCycles
Definition: base.hh:597
gem5::o3::CPU::scheduleThreadExitEvent
void scheduleThreadExitEvent(ThreadID tid)
If a thread is trying to exit and its corresponding trap event has been completed,...
Definition: cpu.cc:1681
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::o3::UnifiedRenameMap::switchFreeList
void switchFreeList(UnifiedFreeList *freeList)
Switch freeList of registers from Full to Elem or vicevers depending on vecMode (vector renaming mode...
Definition: rename_map.cc:129
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
cpu.hh
gem5::o3::Decode::isDrained
bool isDrained() const
Has the stage drained?
Definition: decode.cc:207
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::o3::CPU::squashFromTC
void squashFromTC(ThreadID tid)
Initiates a squash of all in-flight instructions for a given thread.
Definition: cpu.cc:1405
gem5::o3::CPU::CPUStats::vecPredRegfileWrites
statistics::Scalar vecPredRegfileWrites
Definition: cpu.hh:699
gem5::o3::CPU::readIntReg
RegVal readIntReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1148
process.hh
gem5::o3::CPU::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const
Register accessors.
Definition: cpu.cc:1122
gem5::o3::Commit::resetHtmStartsStops
void resetHtmStartsStops(ThreadID)
Definition: commit.cc:435
gem5::o3::CPU::tcBase
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
Definition: cpu.hh:590
gem5::o3::CPU::activateThread
void activateThread(ThreadID tid)
Add Thread to Active Threads List.
Definition: cpu.cc:592
gem5::BaseCPU::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: base.cc:340
activity.hh
gem5::o3::CPU::thread
std::vector< ThreadState * > thread
Pointers to all of the threads in the CPU.
Definition: cpu.hh:608
gem5::BaseCPU::CPU_STATE_ON
@ CPU_STATE_ON
Definition: base.hh:514
gem5::o3::Fetch::deactivateThread
void deactivateThread(ThreadID tid)
For priority-based fetch policies, need to keep update priorityList.
Definition: fetch.cc:501
gem5::o3::CPU::setArchVecPredReg
void setArchVecPredReg(int reg_idx, const TheISA::VecPredRegContainer &val, ThreadID tid)
Definition: cpu.cc:1356
gem5::o3::Commit::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: commit.cc:334
gem5::o3::CPU::CPUStats::ccRegfileReads
statistics::Scalar ccRegfileReads
Definition: cpu.hh:701
gem5::o3::CPU::CPUStats::timesIdled
statistics::Scalar timesIdled
Stat for total number of times the CPU is descheduled.
Definition: cpu.hh:668
gem5::InvalidThreadID
const ThreadID InvalidThreadID
Definition: types.hh:243
gem5::o3::CPU::drain
DrainState drain() override
Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses.
Definition: cpu.cc:921
gem5::o3::CPU::wakeCPU
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
Definition: cpu.cc:1594
gem5::BaseCPU
Definition: base.hh:107
gem5::o3::CPU::readVecReg
const TheISA::VecRegContainer & readVecReg(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1162
gem5::o3::CPU::tickEvent
EventFunctionWrapper tickEvent
The tick event used for scheduling CPU ticks.
Definition: cpu.hh:121
gem5::o3::CPU::switchOut
void switchOut() override
Switches out this CPU.
Definition: cpu.cc:1078
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::o3::CPU::Idle
@ Idle
Definition: cpu.hh:106
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:276
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::o3::CPU::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
Definition: cpu.cc:1135
gem5::o3::CPU::renameQueue
TimeBuffer< RenameStruct > renameQueue
The rename stage's instruction queue.
Definition: cpu.hh:555
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
std::pair
STL pair class.
Definition: stl.hh:58
gem5::o3::CPU::rob
ROB rob
The re-order buffer.
Definition: cpu.hh:513
gem5::statistics::DataWrap::precision
Derived & precision(int _precision)
Set the precision and marks this stat to print at the end of simulation.
Definition: statistics.hh:343
gem5::o3::IEW::tick
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle.
Definition: iew.cc:1433
gem5::o3::Fetch::tick
void tick()
Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible.
Definition: fetch.cc:840
gem5::o3::CPU::Running
@ Running
Definition: cpu.hh:105
gem5::BaseCPU::probeInstCommit
virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc)
Helper method to trigger PMU probes for a committed instruction.
Definition: base.cc:356
gem5::o3::CPU::CPUStats::vecRegfileWrites
statistics::Scalar vecRegfileWrites
Definition: cpu.hh:696
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::CPU::CPUStats::vecRegfileReads
statistics::Scalar vecRegfileReads
Definition: cpu.hh:695
gem5::o3::Commit::instAddr
Addr instAddr(ThreadID tid)
Returns the PC of a specific thread.
Definition: commit.hh:316
gem5::o3::CPU::CPUStats::committedOps
statistics::Vector committedOps
Stat for the number of committed ops (including micro ops) per thread.
Definition: cpu.hh:678
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
name
const std::string & name()
Definition: trace.cc:49
gem5::o3::CPU::instAddr
Addr instAddr(ThreadID tid)
Reads the commit PC of a specific thread.
Definition: cpu.cc:1387
gem5::o3::UnifiedFreeList::getCCReg
PhysRegIdPtr getCCReg()
Gets a free cc register.
Definition: free_list.hh:197
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::EventManager::deschedule
void deschedule(Event &event)
Definition: eventq.hh:1028
full_system.hh
gem5::o3::CPU::getWritableArchVecReg
TheISA::VecRegContainer & getWritableArchVecReg(int reg_idx, ThreadID tid)
Read architectural vector register for modification.
Definition: cpu.cc:1275
gem5::ActivityRecorder::activity
void activity()
Records that there is activity this cycle.
Definition: activity.cc:55
gem5::o3::CPU::setFloatReg
void setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1211
gem5::o3::CPU::setVecPredReg
void setVecPredReg(PhysRegIdPtr reg_idx, const TheISA::VecPredRegContainer &val)
Definition: cpu.cc:1232
gem5::o3::Fetch::startupStage
void startupStage()
Initialize stage.
Definition: fetch.cc:288
gem5::BaseCPU::CPU_STATE_SLEEP
@ CPU_STATE_SLEEP
Definition: base.hh:515
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::o3::CPU::regProbePoints
void regProbePoints() override
Register probe points.
Definition: cpu.cc:358
gem5::o3::CPU::system
System * system
Pointer to the system.
Definition: cpu.hh:605
gem5::Drainable::signalDrainDone
void signalDrainDone() const
Signal that an object is drained.
Definition: drain.hh:305
gem5::Clocked::nextCycle
Tick nextCycle() const
Based on the clock of the object, determine the start tick of the first cycle that is at least one cy...
Definition: clocked_object.hh:213
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::ActivityRecorder::reset
void reset()
Clears the time buffer and the activity count.
Definition: activity.cc:125
gem5::SimObject::getProbeManager
ProbeManager * getProbeManager()
Get the probe manager for this object.
Definition: sim_object.cc:120
gem5::o3::CPU::lastRunningCycle
Cycles lastRunningCycle
The cycle that the CPU was last running, used for statistics.
Definition: cpu.hh:614
gem5::o3::CPU::updateThreadPriority
void updateThreadPriority()
Update The Order In Which We Process Threads.
Definition: cpu.cc:1640
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::CPU::getWritableArchVecPredReg
TheISA::VecPredRegContainer & getWritableArchVecPredReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1300
stat_control.hh
warn_if
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:272
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::o3::CPU::CPUStats::ipc
statistics::Formula ipc
Stat for the IPC per thread.
Definition: cpu.hh:684
gem5::o3::CPU::rename
Rename rename
The dispatch stage.
Definition: cpu.hh:489
gem5::o3::CPU::fetchQueue
TimeBuffer< FetchStruct > fetchQueue
The fetch stage's instruction queue.
Definition: cpu.hh:549
simple_thread.hh
gem5::o3::CPU::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU) override
Takes over from another CPU.
Definition: cpu.cc:1092
gem5::BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:262
gem5::o3::UnifiedFreeList::getFloatReg
PhysRegIdPtr getFloatReg()
Gets a free fp register.
Definition: free_list.hh:185
gem5::o3::CPU::iew
IEW iew
The issue/execute/writeback stages.
Definition: cpu.hh:492
gem5::o3::CPU::removeInstsNotInROB
void removeInstsNotInROB(ThreadID tid)
Remove all instructions that are not currently in the ROB.
Definition: cpu.cc:1452
gem5::o3::IEW::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: iew.cc:383
gem5::o3::CPU::exitThreads
void exitThreads()
Terminate all threads that are ready to exit.
Definition: cpu.cc:1701
gem5::o3::CPU::lastActivatedCycle
Tick lastActivatedCycle
The cycle that the CPU was last activated by a new thread.
Definition: cpu.hh:617
gem5::o3::Commit::drainResume
void drainResume()
Resumes execution after draining.
Definition: commit.cc:351
gem5::BaseCPU::takeOverFrom
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: base.cc:554
gem5::BaseCPU::activateContext
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Definition: base.cc:488
gem5::o3::Commit::executingHtmTransaction
bool executingHtmTransaction(ThreadID) const
Is the CPU currently processing a HTM transaction?
Definition: commit.cc:426
gem5::statistics::DataWrap::prereq
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Definition: statistics.hh:369
gem5::o3::CPU::commitDrained
void commitDrained(ThreadID tid)
Commit has reached a safe point to drain a thread.
Definition: cpu.cc:1046
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::pseudo_inst::quiesceCycles
void quiesceCycles(ThreadContext *tc, uint64_t cycles)
Definition: pseudo_inst.cc:136
gem5::o3::CPU::switchRenameMode
void switchRenameMode(ThreadID tid, UnifiedFreeList *freelist)
Check if a change in renaming is needed for vector registers.
Definition: cpu.cc:860
gem5::o3::Fetch::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: fetch.cc:451
gem5::o3::CPU::microPC
MicroPC microPC(ThreadID tid)
Reads the commit micro PC of a specific thread.
Definition: cpu.cc:1399
gem5::o3::PhysRegFile::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(PhysRegIdPtr phys_reg) const
Reads a predicate register.
Definition: regfile.hh:244
gem5::o3::CPU::commitRenameMap
UnifiedRenameMap commitRenameMap[MaxThreads]
The commit rename map.
Definition: cpu.hh:510
gem5::o3::CPU::trap
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
Definition: cpu.cc:902
gem5::o3::CPU::drainResume
void drainResume() override
Resumes execution after a drain.
Definition: cpu.cc:1049
gem5::o3::CPU::getFreeTid
ThreadID getFreeTid()
Gets a free thread id.
Definition: cpu.cc:1627
gem5::o3::CPU::addInst
ListIt addInst(const DynInstPtr &inst)
Function to add instruction onto the head of the list of the instructions.
Definition: cpu.cc:1412
gem5::o3::ROB::isEmpty
bool isEmpty() const
Returns if the ROB is empty.
Definition: rob.hh:195
gem5::o3::CPU::isThreadExiting
bool isThreadExiting(ThreadID tid) const
Is the thread trying to exit?
Definition: cpu.cc:1675
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::o3::Decode::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: decode.cc:198
gem5::o3::CPU::threadExitEvent
EventFunctionWrapper threadExitEvent
The exit event used for terminating all ready-to-exit threads.
Definition: cpu.hh:124
gem5::o3::UnifiedRenameMap::lookup
PhysRegIdPtr lookup(const RegId &arch_reg) const
Look up the physical register mapped to an architectural register.
Definition: rename_map.hh:266
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::BaseCPU::switchOut
virtual void switchOut()
Prepare for another CPU to take over execution.
Definition: base.cc:540
gem5::o3::Commit::pcState
TheISA::PCState pcState(ThreadID tid)
Reads the PC of a specific thread.
Definition: commit.hh:309
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::CPU::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
Definition: cpu.cc:1128
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:198
gem5::o3::PhysRegFile::setFloatReg
void setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: regfile.hh:290
gem5::o3::Rename::startupStage
void startupStage()
Initializes variables for the stage.
Definition: rename.cc:221
thread_context.hh
gem5::o3::PhysRegFile::setIntReg
void setIntReg(PhysRegIdPtr phys_reg, RegVal val)
Sets an integer register to the given value.
Definition: regfile.hh:278
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::o3::CPU::SwitchedOut
@ SwitchedOut
Definition: cpu.hh:109
gem5::o3::CPU::exitingThreads
std::unordered_map< ThreadID, bool > exitingThreads
This is a list of threads that are trying to exit.
Definition: cpu.hh:523
gem5::o3::CPU::CPUStats::fpRegfileReads
statistics::Scalar fpRegfileReads
Definition: cpu.hh:692
gem5::o3::CPU::readArchIntReg
RegVal readArchIntReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1247
gem5::o3::Fetch::regProbePoints
void regProbePoints()
Registers probes.
Definition: fetch.cc:153
gem5::RiscvISA::sum
Bitfield< 18 > sum
Definition: misc.hh:545
gem5::o3::LSQ::getDataPort
RequestPort & getDataPort()
Definition: lsq.hh:1010
gem5::ActivityRecorder::active
bool active()
Returns if the CPU should be active.
Definition: activity.hh:91
gem5::o3::Commit::tick
void tick()
Ticks the commit stage, which tries to commit instructions.
Definition: commit.cc:629
gem5::o3::Rename::regProbePoints
void regProbePoints()
Registers probes.
Definition: rename.cc:179
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:355
gem5::o3::CPU::scoreboard
Scoreboard scoreboard
Integer Register Scoreboard.
Definition: cpu.hh:526
gem5::DrainState::Running
@ Running
Running normally.
gem5::o3::IEW::ldstQueue
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:358
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::o3::CPU::commit
Commit commit
The commit stage.
Definition: cpu.hh:495
cpu.hh
std::list
STL list class.
Definition: stl.hh:51
gem5::o3::CPU::haltContext
void haltContext(ThreadID tid) override
Remove Thread from Active Threads List && Remove Thread Context from CPU.
Definition: cpu.cc:714
gem5::EventBase::CPU_Tick_Pri
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:204
gem5::o3::PhysRegFile::setVecReg
void setVecReg(PhysRegIdPtr phys_reg, const TheISA::VecRegContainer &val)
Sets a vector register to the given value.
Definition: regfile.hh:302
gem5::o3::CPU::activityRec
ActivityRecorder activityRec
The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and...
Definition: cpu.hh:565
gem5::o3::CPU::pcState
void pcState(const TheISA::PCState &newPCState, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1381
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::Decode::startupStage
void startupStage()
Definition: decode.cc:92
gem5::o3::CPU::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1183
gem5::Packet::createRead
static PacketPtr createRead(const RequestPtr &req)
Constructor-like methods that return Packets based on Request objects.
Definition: packet.hh:1007
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
thread_context.hh
limits.hh
gem5::o3::CPU::activateContext
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
Definition: cpu.cc:656
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1037
gem5::o3::Rename::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: rename.cc:319
gem5::o3::UnifiedFreeList::getIntReg
PhysRegIdPtr getIntReg()
Gets a free integer register.
Definition: free_list.hh:182
gem5::o3::CPU::nextInstAddr
Addr nextInstAddr(ThreadID tid)
Reads the next PC of a specific thread.
Definition: cpu.cc:1393
gem5::o3::CPU::tick
void tick()
Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should d...
Definition: cpu.cc:502
gem5::o3::PhysRegFile::readCCReg
RegVal readCCReg(PhysRegIdPtr phys_reg)
Reads a condition-code register.
Definition: regfile.hh:265
gem5::o3::CPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: cpu.cc:580
gem5::o3::CPU::CPUStats::CPUStats
CPUStats(CPU *cpu)
Definition: cpu.cc:374
thread_context.hh
gem5::o3::CPU::isa
std::vector< TheISA::ISA * > isa
Definition: cpu.hh:528
gem5::o3::Commit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: commit.cc:358
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::o3::CPU::instDone
void instDone(ThreadID tid, const DynInstPtr &inst)
Function to tell the CPU that an instruction has completed.
Definition: cpu.cc:1420
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::Commit::nextInstAddr
Addr nextInstAddr(ThreadID tid)
Returns the next PC of a specific thread.
Definition: commit.hh:319
gem5::o3::CPU::init
void init() override
Initialize the CPU.
Definition: cpu.cc:560
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::o3::UnifiedRenameMap::setEntry
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
Definition: rename_map.hh:309
gem5::o3::CPU::removeFrontInst
void removeFrontInst(const DynInstPtr &inst)
Remove an instruction from the front end of the list.
Definition: cpu.cc:1439
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:422
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::o3::CPU::readArchVecReg
const TheISA::VecRegContainer & readArchVecReg(int reg_idx, ThreadID tid) const
Definition: cpu.cc:1267
gem5::o3::IEW::regProbePoints
void regProbePoints()
Registers probes.
Definition: iew.cc:125
gem5::o3::InstructionQueue::getCount
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
Definition: inst_queue.hh:274

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