gem5  v21.2.1.1
cpu.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019-2020 ARM Limited
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Copyright (c) 2004-2006 The Regents of The University of Michigan
16  * Copyright (c) 2011 Regents of the University of California
17  * All rights reserved.
18  *
19  * Redistribution and use in source and binary forms, with or without
20  * modification, are permitted provided that the following conditions are
21  * met: redistributions of source code must retain the above copyright
22  * notice, this list of conditions and the following disclaimer;
23  * redistributions in binary form must reproduce the above copyright
24  * notice, this list of conditions and the following disclaimer in the
25  * documentation and/or other materials provided with the distribution;
26  * neither the name of the copyright holders nor the names of its
27  * contributors may be used to endorse or promote products derived from
28  * this software without specific prior written permission.
29  *
30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41  */
42 
43 #include "cpu/o3/cpu.hh"
44 
45 #include "config/the_isa.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/checker/cpu.hh"
49 #include "cpu/o3/dyn_inst.hh"
50 #include "cpu/o3/limits.hh"
51 #include "cpu/o3/thread_context.hh"
52 #include "cpu/simple_thread.hh"
53 #include "cpu/thread_context.hh"
54 #include "debug/Activity.hh"
55 #include "debug/Drain.hh"
56 #include "debug/O3CPU.hh"
57 #include "debug/Quiesce.hh"
58 #include "enums/MemoryMode.hh"
59 #include "sim/cur_tick.hh"
60 #include "sim/full_system.hh"
61 #include "sim/process.hh"
62 #include "sim/stat_control.hh"
63 #include "sim/system.hh"
64 
65 namespace gem5
66 {
67 
68 struct BaseCPUParams;
69 
70 namespace o3
71 {
72 
73 CPU::CPU(const O3CPUParams &params)
74  : BaseCPU(params),
75  mmu(params.mmu),
76  tickEvent([this]{ tick(); }, "O3CPU tick",
77  false, Event::CPU_Tick_Pri),
78  threadExitEvent([this]{ exitThreads(); }, "O3CPU exit threads",
79  false, Event::CPU_Exit_Pri),
80 #ifndef NDEBUG
81  instcount(0),
82 #endif
83  removeInstsThisCycle(false),
84  fetch(this, params),
85  decode(this, params),
86  rename(this, params),
87  iew(this, params),
88  commit(this, params),
89 
90  regFile(params.numPhysIntRegs,
91  params.numPhysFloatRegs,
92  params.numPhysVecRegs,
93  params.numPhysVecPredRegs,
94  params.numPhysCCRegs,
95  params.isa[0]->regClasses()),
96 
97  freeList(name() + ".freelist", &regFile),
98 
99  rob(this, params),
100 
101  scoreboard(name() + ".scoreboard", regFile.totalNumPhysRegs(),
102  params.isa[0]->regClasses().at(IntRegClass).zeroReg()),
103 
104  isa(numThreads, NULL),
105 
106  timeBuffer(params.backComSize, params.forwardComSize),
107  fetchQueue(params.backComSize, params.forwardComSize),
108  decodeQueue(params.backComSize, params.forwardComSize),
109  renameQueue(params.backComSize, params.forwardComSize),
110  iewQueue(params.backComSize, params.forwardComSize),
111  activityRec(name(), NumStages,
112  params.backComSize + params.forwardComSize,
113  params.activity),
114 
115  globalSeqNum(1),
116  system(params.system),
117  lastRunningCycle(curCycle()),
118  cpuStats(this)
119 {
120  fatal_if(FullSystem && params.numThreads > 1,
121  "SMT is not supported in O3 in full system mode currently.");
122 
123  fatal_if(!FullSystem && params.numThreads < params.workload.size(),
124  "More workload items (%d) than threads (%d) on CPU %s.",
125  params.workload.size(), params.numThreads, name());
126 
127  if (!params.switched_out) {
128  _status = Running;
129  } else {
130  _status = SwitchedOut;
131  }
132 
133  if (params.checker) {
134  BaseCPU *temp_checker = params.checker;
135  checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
136  checker->setIcachePort(&fetch.getInstPort());
137  checker->setSystem(params.system);
138  } else {
139  checker = NULL;
140  }
141 
142  if (!FullSystem) {
143  thread.resize(numThreads);
144  tids.resize(numThreads);
145  }
146 
147  // The stages also need their CPU pointer setup. However this
148  // must be done at the upper level CPU because they have pointers
149  // to the upper level CPU, and not this CPU.
150 
151  // Set up Pointers to the activeThreads list for each stage
152  fetch.setActiveThreads(&activeThreads);
153  decode.setActiveThreads(&activeThreads);
154  rename.setActiveThreads(&activeThreads);
155  iew.setActiveThreads(&activeThreads);
156  commit.setActiveThreads(&activeThreads);
157 
158  // Give each of the stages the time buffer they will use.
159  fetch.setTimeBuffer(&timeBuffer);
160  decode.setTimeBuffer(&timeBuffer);
161  rename.setTimeBuffer(&timeBuffer);
162  iew.setTimeBuffer(&timeBuffer);
163  commit.setTimeBuffer(&timeBuffer);
164 
165  // Also setup each of the stages' queues.
166  fetch.setFetchQueue(&fetchQueue);
167  decode.setFetchQueue(&fetchQueue);
168  commit.setFetchQueue(&fetchQueue);
169  decode.setDecodeQueue(&decodeQueue);
170  rename.setDecodeQueue(&decodeQueue);
171  rename.setRenameQueue(&renameQueue);
172  iew.setRenameQueue(&renameQueue);
173  iew.setIEWQueue(&iewQueue);
174  commit.setIEWQueue(&iewQueue);
175  commit.setRenameQueue(&renameQueue);
176 
177  commit.setIEWStage(&iew);
178  rename.setIEWStage(&iew);
179  rename.setCommitStage(&commit);
180 
181  ThreadID active_threads;
182  if (FullSystem) {
183  active_threads = 1;
184  } else {
185  active_threads = params.workload.size();
186 
187  if (active_threads > MaxThreads) {
188  panic("Workload Size too large. Increase the 'MaxThreads' "
189  "constant in cpu/o3/limits.hh or edit your workload size.");
190  }
191  }
192 
193  // Make Sure That this a Valid Architeture
194  assert(numThreads);
195  const auto &regClasses = params.isa[0]->regClasses();
196 
197  assert(params.numPhysIntRegs >=
198  numThreads * regClasses.at(IntRegClass).size());
199  assert(params.numPhysFloatRegs >=
200  numThreads * regClasses.at(FloatRegClass).size());
201  assert(params.numPhysVecRegs >=
202  numThreads * regClasses.at(VecRegClass).size());
203  assert(params.numPhysVecPredRegs >=
204  numThreads * regClasses.at(VecPredRegClass).size());
205  assert(params.numPhysCCRegs >=
206  numThreads * regClasses.at(CCRegClass).size());
207 
208  // Just make this a warning and go ahead anyway, to keep from having to
209  // add checks everywhere.
210  warn_if(regClasses.at(CCRegClass).size() == 0 && params.numPhysCCRegs != 0,
211  "Non-zero number of physical CC regs specified, even though\n"
212  " ISA does not use them.");
213 
214  rename.setScoreboard(&scoreboard);
215  iew.setScoreboard(&scoreboard);
216 
217  // Setup the rename map for whichever stages need it.
218  for (ThreadID tid = 0; tid < numThreads; tid++) {
219  isa[tid] = dynamic_cast<TheISA::ISA *>(params.isa[tid]);
220  commitRenameMap[tid].init(regClasses, &regFile, &freeList);
221  renameMap[tid].init(regClasses, &regFile, &freeList);
222  }
223 
224  // Initialize rename map to assign physical registers to the
225  // architectural registers for active threads only.
226  for (ThreadID tid = 0; tid < active_threads; tid++) {
227  for (RegIndex ridx = 0; ridx < regClasses.at(IntRegClass).size();
228  ++ridx) {
229  // Note that we can't use the rename() method because we don't
230  // want special treatment for the zero register at this point
231  PhysRegIdPtr phys_reg = freeList.getIntReg();
232  renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
233  commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
234  }
235 
236  for (RegIndex ridx = 0; ridx < regClasses.at(FloatRegClass).size();
237  ++ridx) {
238  PhysRegIdPtr phys_reg = freeList.getFloatReg();
239  renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
240  commitRenameMap[tid].setEntry(
241  RegId(FloatRegClass, ridx), phys_reg);
242  }
243 
244  const size_t numVecs = regClasses.at(VecRegClass).size();
245  /* Initialize the full-vector interface */
246  for (RegIndex ridx = 0; ridx < numVecs; ++ridx) {
247  RegId rid = RegId(VecRegClass, ridx);
248  PhysRegIdPtr phys_reg = freeList.getVecReg();
249  renameMap[tid].setEntry(rid, phys_reg);
250  commitRenameMap[tid].setEntry(rid, phys_reg);
251  }
252  /* Initialize the vector-element interface */
253  const size_t numElems = regClasses.at(VecElemClass).size();
254  const size_t elemsPerVec = numElems / numVecs;
255  for (RegIndex ridx = 0; ridx < numVecs; ++ridx) {
256  for (ElemIndex ldx = 0; ldx < elemsPerVec; ++ldx) {
257  RegId lrid = RegId(VecElemClass, ridx, ldx);
258  PhysRegIdPtr phys_elem = freeList.getVecElem();
259  renameMap[tid].setEntry(lrid, phys_elem);
260  commitRenameMap[tid].setEntry(lrid, phys_elem);
261  }
262  }
263 
264  for (RegIndex ridx = 0; ridx < regClasses.at(VecPredRegClass).size();
265  ++ridx) {
266  PhysRegIdPtr phys_reg = freeList.getVecPredReg();
267  renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg);
268  commitRenameMap[tid].setEntry(
269  RegId(VecPredRegClass, ridx), phys_reg);
270  }
271 
272  for (RegIndex ridx = 0; ridx < regClasses.at(CCRegClass).size();
273  ++ridx) {
274  PhysRegIdPtr phys_reg = freeList.getCCReg();
275  renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
276  commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
277  }
278  }
279 
280  rename.setRenameMap(renameMap);
281  commit.setRenameMap(commitRenameMap);
282  rename.setFreeList(&freeList);
283 
284  // Setup the ROB for whichever stages need it.
285  commit.setROB(&rob);
286 
287  lastActivatedCycle = 0;
288 
289  DPRINTF(O3CPU, "Creating O3CPU object.\n");
290 
291  // Setup any thread state.
292  thread.resize(numThreads);
293 
294  for (ThreadID tid = 0; tid < numThreads; ++tid) {
295  if (FullSystem) {
296  // SMT is not supported in FS mode yet.
297  assert(numThreads == 1);
298  thread[tid] = new ThreadState(this, 0, NULL);
299  } else {
300  if (tid < params.workload.size()) {
301  DPRINTF(O3CPU, "Workload[%i] process is %#x", tid,
302  thread[tid]);
303  thread[tid] = new ThreadState(this, tid, params.workload[tid]);
304  } else {
305  //Allocate Empty thread so M5 can use later
306  //when scheduling threads to CPU
307  Process* dummy_proc = NULL;
308 
309  thread[tid] = new ThreadState(this, tid, dummy_proc);
310  }
311  }
312 
314 
315  // Setup the TC that will serve as the interface to the threads/CPU.
316  auto *o3_tc = new ThreadContext;
317 
318  tc = o3_tc;
319 
320  // If we're using a checker, then the TC should be the
321  // CheckerThreadContext.
322  if (params.checker) {
323  tc = new CheckerThreadContext<ThreadContext>(o3_tc, checker);
324  }
325 
326  o3_tc->cpu = this;
327  o3_tc->thread = thread[tid];
328 
329  // Give the thread the TC.
330  thread[tid]->tc = tc;
331 
332  // Add the TC to the CPU's list of TC's.
333  threadContexts.push_back(tc);
334  }
335 
336  // O3CPU always requires an interrupt controller.
337  if (!params.switched_out && interrupts.empty()) {
338  fatal("O3CPU %s has no interrupt controller.\n"
339  "Ensure createInterruptController() is called.\n", name());
340  }
341 }
342 
343 void
345 {
346  BaseCPU::regProbePoints();
347 
349  getProbeManager(), "InstAccessComplete");
352  getProbeManager(), "DataAccessComplete");
353 
358 }
359 
361  : statistics::Group(cpu),
362  ADD_STAT(timesIdled, statistics::units::Count::get(),
363  "Number of times that the entire CPU went into an idle state "
364  "and unscheduled itself"),
365  ADD_STAT(idleCycles, statistics::units::Cycle::get(),
366  "Total number of cycles that the CPU has spent unscheduled due "
367  "to idling"),
368  ADD_STAT(quiesceCycles, statistics::units::Cycle::get(),
369  "Total number of cycles that CPU has spent quiesced or waiting "
370  "for an interrupt"),
371  ADD_STAT(committedInsts, statistics::units::Count::get(),
372  "Number of Instructions Simulated"),
373  ADD_STAT(committedOps, statistics::units::Count::get(),
374  "Number of Ops (including micro ops) Simulated"),
375  ADD_STAT(cpi, statistics::units::Rate<
376  statistics::units::Cycle, statistics::units::Count>::get(),
377  "CPI: Cycles Per Instruction"),
378  ADD_STAT(totalCpi, statistics::units::Rate<
379  statistics::units::Cycle, statistics::units::Count>::get(),
380  "CPI: Total CPI of All Threads"),
381  ADD_STAT(ipc, statistics::units::Rate<
382  statistics::units::Count, statistics::units::Cycle>::get(),
383  "IPC: Instructions Per Cycle"),
384  ADD_STAT(totalIpc, statistics::units::Rate<
385  statistics::units::Count, statistics::units::Cycle>::get(),
386  "IPC: Total IPC of All Threads"),
387  ADD_STAT(intRegfileReads, statistics::units::Count::get(),
388  "Number of integer regfile reads"),
389  ADD_STAT(intRegfileWrites, statistics::units::Count::get(),
390  "Number of integer regfile writes"),
391  ADD_STAT(fpRegfileReads, statistics::units::Count::get(),
392  "Number of floating regfile reads"),
393  ADD_STAT(fpRegfileWrites, statistics::units::Count::get(),
394  "Number of floating regfile writes"),
395  ADD_STAT(vecRegfileReads, statistics::units::Count::get(),
396  "number of vector regfile reads"),
397  ADD_STAT(vecRegfileWrites, statistics::units::Count::get(),
398  "number of vector regfile writes"),
399  ADD_STAT(vecPredRegfileReads, statistics::units::Count::get(),
400  "number of predicate regfile reads"),
401  ADD_STAT(vecPredRegfileWrites, statistics::units::Count::get(),
402  "number of predicate regfile writes"),
403  ADD_STAT(ccRegfileReads, statistics::units::Count::get(),
404  "number of cc regfile reads"),
405  ADD_STAT(ccRegfileWrites, statistics::units::Count::get(),
406  "number of cc regfile writes"),
407  ADD_STAT(miscRegfileReads, statistics::units::Count::get(),
408  "number of misc regfile reads"),
409  ADD_STAT(miscRegfileWrites, statistics::units::Count::get(),
410  "number of misc regfile writes")
411 {
412  // Register any of the O3CPU's stats here.
413  timesIdled
414  .prereq(timesIdled);
415 
416  idleCycles
417  .prereq(idleCycles);
418 
421 
422  // Number of Instructions simulated
423  // --------------------------------
424  // Should probably be in Base CPU but need templated
425  // MaxThreads so put in here instead
427  .init(cpu->numThreads)
429 
431  .init(cpu->numThreads)
433 
434  cpi
435  .precision(6);
436  cpi = cpu->baseStats.numCycles / committedInsts;
437 
438  totalCpi
439  .precision(6);
440  totalCpi = cpu->baseStats.numCycles / sum(committedInsts);
441 
442  ipc
443  .precision(6);
444  ipc = committedInsts / cpu->baseStats.numCycles;
445 
446  totalIpc
447  .precision(6);
448  totalIpc = sum(committedInsts) / cpu->baseStats.numCycles;
449 
452 
455 
458 
461 
464 
467 
470 
473 
476 
479 
482 
485 }
486 
487 void
489 {
490  DPRINTF(O3CPU, "\n\nO3CPU: Ticking main, O3CPU.\n");
491  assert(!switchedOut());
492  assert(drainState() != DrainState::Drained);
493 
494  ++baseStats.numCycles;
495  updateCycleCounters(BaseCPU::CPU_STATE_ON);
496 
497 // activity = false;
498 
499  //Tick each of the stages
500  fetch.tick();
501 
502  decode.tick();
503 
504  rename.tick();
505 
506  iew.tick();
507 
508  commit.tick();
509 
510  // Now advance the time buffers
511  timeBuffer.advance();
512 
513  fetchQueue.advance();
514  decodeQueue.advance();
515  renameQueue.advance();
516  iewQueue.advance();
517 
519 
520  if (removeInstsThisCycle) {
522  }
523 
524  if (!tickEvent.scheduled()) {
525  if (_status == SwitchedOut) {
526  DPRINTF(O3CPU, "Switched out!\n");
527  // increment stat
528  lastRunningCycle = curCycle();
529  } else if (!activityRec.active() || _status == Idle) {
530  DPRINTF(O3CPU, "Idle!\n");
531  lastRunningCycle = curCycle();
533  } else {
534  schedule(tickEvent, clockEdge(Cycles(1)));
535  DPRINTF(O3CPU, "Scheduling next tick!\n");
536  }
537  }
538 
539  if (!FullSystem)
541 
542  tryDrain();
543 }
544 
545 void
547 {
548  BaseCPU::init();
549 
550  for (ThreadID tid = 0; tid < numThreads; ++tid) {
551  // Set noSquashFromTC so that the CPU doesn't squash when initially
552  // setting up registers.
553  thread[tid]->noSquashFromTC = true;
554  }
555 
556  // Clear noSquashFromTC.
557  for (int tid = 0; tid < numThreads; ++tid)
558  thread[tid]->noSquashFromTC = false;
559 
561 }
562 
563 void
565 {
566  BaseCPU::startup();
567 
570  iew.startupStage();
573 }
574 
575 void
577 {
579  std::find(activeThreads.begin(), activeThreads.end(), tid);
580 
581  DPRINTF(O3CPU, "[tid:%i] Calling activate thread.\n", tid);
582  assert(!switchedOut());
583 
584  if (isActive == activeThreads.end()) {
585  DPRINTF(O3CPU, "[tid:%i] Adding to active threads list\n", tid);
586 
587  activeThreads.push_back(tid);
588  }
589 }
590 
591 void
593 {
594  // hardware transactional memory
595  // shouldn't deactivate thread in the middle of a transaction
596  assert(!commit.executingHtmTransaction(tid));
597 
598  //Remove From Active List, if Active
600  std::find(activeThreads.begin(), activeThreads.end(), tid);
601 
602  DPRINTF(O3CPU, "[tid:%i] Calling deactivate thread.\n", tid);
603  assert(!switchedOut());
604 
605  if (thread_it != activeThreads.end()) {
606  DPRINTF(O3CPU,"[tid:%i] Removing from active threads list\n",
607  tid);
608  activeThreads.erase(thread_it);
609  }
610 
611  fetch.deactivateThread(tid);
613 }
614 
615 Counter
617 {
618  Counter total(0);
619 
620  ThreadID size = thread.size();
621  for (ThreadID i = 0; i < size; i++)
622  total += thread[i]->numInst;
623 
624  return total;
625 }
626 
627 Counter
629 {
630  Counter total(0);
631 
632  ThreadID size = thread.size();
633  for (ThreadID i = 0; i < size; i++)
634  total += thread[i]->numOp;
635 
636  return total;
637 }
638 
639 void
641 {
642  assert(!switchedOut());
643 
644  // Needs to set each stage to running as well.
645  activateThread(tid);
646 
647  // We don't want to wake the CPU if it is drained. In that case,
648  // we just want to flag the thread as active and schedule the tick
649  // event from drainResume() instead.
650  if (drainState() == DrainState::Drained)
651  return;
652 
653  // If we are time 0 or if the last activation time is in the past,
654  // schedule the next tick and wake up the fetch unit
657 
658  // Be sure to signal that there's some activity so the CPU doesn't
659  // deschedule itself.
662 
663  Cycles cycles(curCycle() - lastRunningCycle);
664  // @todo: This is an oddity that is only here to match the stats
665  if (cycles != 0)
666  --cycles;
667  cpuStats.quiesceCycles += cycles;
668 
670 
671  _status = Running;
672 
673  BaseCPU::activateContext(tid);
674  }
675 }
676 
677 void
679 {
680  DPRINTF(O3CPU,"[tid:%i] Suspending Thread Context.\n", tid);
681  assert(!switchedOut());
682 
683  deactivateThread(tid);
684 
685  // If this was the last thread then unschedule the tick event.
686  if (activeThreads.size() == 0) {
688  lastRunningCycle = curCycle();
689  _status = Idle;
690  }
691 
692  DPRINTF(Quiesce, "Suspending Context\n");
693 
694  BaseCPU::suspendContext(tid);
695 }
696 
697 void
699 {
700  //For now, this is the same as deallocate
701  DPRINTF(O3CPU,"[tid:%i] Halt Context called. Deallocating\n", tid);
702  assert(!switchedOut());
703 
704  deactivateThread(tid);
705  removeThread(tid);
706 
707  // If this was the last thread then unschedule the tick event.
708  if (activeThreads.size() == 0) {
709  if (tickEvent.scheduled())
710  {
712  }
713  lastRunningCycle = curCycle();
714  _status = Idle;
715  }
716  updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
717 }
718 
719 void
721 {
722  DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
723  // Will change now that the PC and thread state is internal to the CPU
724  // and not in the ThreadContext.
725  gem5::ThreadContext *src_tc;
726  if (FullSystem)
727  src_tc = system->threads[tid];
728  else
729  src_tc = tcBase(tid);
730 
731  //Bind Int Regs to Rename Map
732  const auto &regClasses = isa[tid]->regClasses();
733 
734  for (RegIndex idx = 0; idx < regClasses.at(IntRegClass).size(); idx++) {
735  PhysRegIdPtr phys_reg = freeList.getIntReg();
736  renameMap[tid].setEntry(RegId(IntRegClass, idx), phys_reg);
737  scoreboard.setReg(phys_reg);
738  }
739 
740  //Bind Float Regs to Rename Map
741  for (RegIndex idx = 0; idx < regClasses.at(FloatRegClass).size(); idx++) {
742  PhysRegIdPtr phys_reg = freeList.getFloatReg();
743  renameMap[tid].setEntry(RegId(FloatRegClass, idx), phys_reg);
744  scoreboard.setReg(phys_reg);
745  }
746 
747  //Bind condition-code Regs to Rename Map
748  for (RegIndex idx = 0; idx < regClasses.at(CCRegClass).size(); idx++) {
749  PhysRegIdPtr phys_reg = freeList.getCCReg();
750  renameMap[tid].setEntry(RegId(CCRegClass, idx), phys_reg);
751  scoreboard.setReg(phys_reg);
752  }
753 
754  //Copy Thread Data Into RegFile
755  //copyFromTC(tid);
756 
757  //Set PC/NPC/NNPC
758  pcState(src_tc->pcState(), tid);
759 
761 
762  activateContext(tid);
763 
764  //Reset ROB/IQ/LSQ Entries
766 }
767 
768 void
770 {
771  DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
772 
773  // Copy Thread Data From RegFile
774  // If thread is suspended, it might be re-allocated
775  // copyToTC(tid);
776 
777 
778  // @todo: 2-27-2008: Fix how we free up rename mappings
779  // here to alleviate the case for double-freeing registers
780  // in SMT workloads.
781 
782  // clear all thread-specific states in each stage of the pipeline
783  // since this thread is going to be completely removed from the CPU
784  commit.clearStates(tid);
785  fetch.clearStates(tid);
786  decode.clearStates(tid);
787  rename.clearStates(tid);
788  iew.clearStates(tid);
789 
790  // Flush out any old data from the time buffers.
791  for (int i = 0; i < timeBuffer.getSize(); ++i) {
792  timeBuffer.advance();
793  fetchQueue.advance();
794  decodeQueue.advance();
795  renameQueue.advance();
796  iewQueue.advance();
797  }
798 
799  // at this step, all instructions in the pipeline should be already
800  // either committed successfully or squashed. All thread-specific
801  // queues in the pipeline must be empty.
802  assert(iew.instQueue.getCount(tid) == 0);
803  assert(iew.ldstQueue.getCount(tid) == 0);
804  assert(commit.rob->isEmpty(tid));
805 
806  // Reset ROB/IQ/LSQ Entries
807 
808  // Commented out for now. This should be possible to do by
809  // telling all the pipeline stages to drain first, and then
810  // checking until the drain completes. Once the pipeline is
811  // drained, call resetEntries(). - 10-09-06 ktlim
812 /*
813  if (activeThreads.size() >= 1) {
814  commit.rob->resetEntries();
815  iew.resetEntries();
816  }
817 */
818 }
819 
820 Fault
822 {
823  // Check if there are any outstanding interrupts
824  return interrupts[0]->getInterrupt();
825 }
826 
827 void
828 CPU::processInterrupts(const Fault &interrupt)
829 {
830  // Check for interrupts here. For now can copy the code that
831  // exists within isa_fullsys_traits.hh. Also assume that thread 0
832  // is the one that handles the interrupts.
833  // @todo: Possibly consolidate the interrupt checking code.
834  // @todo: Allow other threads to handle interrupts.
835 
836  assert(interrupt != NoFault);
837  interrupts[0]->updateIntrInfo();
838 
839  DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
840  trap(interrupt, 0, nullptr);
841 }
842 
843 void
844 CPU::trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
845 {
846  // Pass the thread's TC into the invoke method.
847  fault->invoke(threadContexts[tid], inst);
848 }
849 
850 void
852 {
853  thread[tid]->serialize(cp);
854 }
855 
856 void
858 {
859  thread[tid]->unserialize(cp);
860 }
861 
864 {
865  // Deschedule any power gating event (if any)
866  deschedulePowerGatingEvent();
867 
868  // If the CPU isn't doing anything, then return immediately.
869  if (switchedOut())
870  return DrainState::Drained;
871 
872  DPRINTF(Drain, "Draining...\n");
873 
874  // We only need to signal a drain to the commit stage as this
875  // initiates squashing controls the draining. Once the commit
876  // stage commits an instruction where it is safe to stop, it'll
877  // squash the rest of the instructions in the pipeline and force
878  // the fetch stage to stall. The pipeline will be drained once all
879  // in-flight instructions have retired.
880  commit.drain();
881 
882  // Wake the CPU and record activity so everything can drain out if
883  // the CPU was not able to immediately drain.
884  if (!isCpuDrained()) {
885  // If a thread is suspended, wake it up so it can be drained
886  for (auto t : threadContexts) {
887  if (t->status() == gem5::ThreadContext::Suspended){
888  DPRINTF(Drain, "Currently suspended so activate %i \n",
889  t->threadId());
890  t->activate();
891  // As the thread is now active, change the power state as well
892  activateContext(t->threadId());
893  }
894  }
895 
896  wakeCPU();
898 
899  DPRINTF(Drain, "CPU not drained\n");
900 
901  return DrainState::Draining;
902  } else {
903  DPRINTF(Drain, "CPU is already drained\n");
904  if (tickEvent.scheduled())
905  deschedule(tickEvent);
906 
907  // Flush out any old data from the time buffers. In
908  // particular, there might be some data in flight from the
909  // fetch stage that isn't visible in any of the CPU buffers we
910  // test in isCpuDrained().
911  for (int i = 0; i < timeBuffer.getSize(); ++i) {
912  timeBuffer.advance();
913  fetchQueue.advance();
914  decodeQueue.advance();
915  renameQueue.advance();
916  iewQueue.advance();
917  }
918 
920  return DrainState::Drained;
921  }
922 }
923 
924 bool
926 {
927  if (drainState() != DrainState::Draining || !isCpuDrained())
928  return false;
929 
930  if (tickEvent.scheduled())
931  deschedule(tickEvent);
932 
933  DPRINTF(Drain, "CPU done draining, processing drain event\n");
934  signalDrainDone();
935 
936  return true;
937 }
938 
939 void
941 {
942  assert(isCpuDrained());
948 }
949 
950 bool
952 {
953  bool drained(true);
954 
955  if (!instList.empty() || !removeList.empty()) {
956  DPRINTF(Drain, "Main CPU structures not drained.\n");
957  drained = false;
958  }
959 
960  if (!fetch.isDrained()) {
961  DPRINTF(Drain, "Fetch not drained.\n");
962  drained = false;
963  }
964 
965  if (!decode.isDrained()) {
966  DPRINTF(Drain, "Decode not drained.\n");
967  drained = false;
968  }
969 
970  if (!rename.isDrained()) {
971  DPRINTF(Drain, "Rename not drained.\n");
972  drained = false;
973  }
974 
975  if (!iew.isDrained()) {
976  DPRINTF(Drain, "IEW not drained.\n");
977  drained = false;
978  }
979 
980  if (!commit.isDrained()) {
981  DPRINTF(Drain, "Commit not drained.\n");
982  drained = false;
983  }
984 
985  return drained;
986 }
987 
989 
990 void
992 {
993  if (switchedOut())
994  return;
995 
996  DPRINTF(Drain, "Resuming...\n");
998 
999  fetch.drainResume();
1000  commit.drainResume();
1001 
1002  _status = Idle;
1003  for (ThreadID i = 0; i < thread.size(); i++) {
1005  DPRINTF(Drain, "Activating thread: %i\n", i);
1006  activateThread(i);
1007  _status = Running;
1008  }
1009  }
1010 
1011  assert(!tickEvent.scheduled());
1012  if (_status == Running)
1013  schedule(tickEvent, nextCycle());
1014 
1015  // Reschedule any power gating event (if any)
1016  schedulePowerGatingEvent();
1017 }
1018 
1019 void
1021 {
1022  DPRINTF(O3CPU, "Switching out\n");
1023  BaseCPU::switchOut();
1024 
1025  activityRec.reset();
1026 
1027  _status = SwitchedOut;
1028 
1029  if (checker)
1030  checker->switchOut();
1031 }
1032 
1033 void
1034 CPU::takeOverFrom(BaseCPU *oldCPU)
1035 {
1036  BaseCPU::takeOverFrom(oldCPU);
1037 
1038  fetch.takeOverFrom();
1039  decode.takeOverFrom();
1040  rename.takeOverFrom();
1041  iew.takeOverFrom();
1042  commit.takeOverFrom();
1043 
1044  assert(!tickEvent.scheduled());
1045 
1046  auto *oldO3CPU = dynamic_cast<CPU *>(oldCPU);
1047  if (oldO3CPU)
1048  globalSeqNum = oldO3CPU->globalSeqNum;
1049 
1050  lastRunningCycle = curCycle();
1051  _status = Idle;
1052 }
1053 
1054 void
1056 {
1057  if (!system->isTimingMode()) {
1058  fatal("The O3 CPU requires the memory system to be in "
1059  "'timing' mode.\n");
1060  }
1061 }
1062 
1063 RegVal
1064 CPU::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1065 {
1066  return isa[tid]->readMiscRegNoEffect(misc_reg);
1067 }
1068 
1069 RegVal
1070 CPU::readMiscReg(int misc_reg, ThreadID tid)
1071 {
1073  return isa[tid]->readMiscReg(misc_reg);
1074 }
1075 
1076 void
1078 {
1079  isa[tid]->setMiscRegNoEffect(misc_reg, val);
1080 }
1081 
1082 void
1083 CPU::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
1084 {
1086  isa[tid]->setMiscReg(misc_reg, val);
1087 }
1088 
1089 RegVal
1091 {
1093  return regFile.readIntReg(phys_reg);
1094 }
1095 
1096 RegVal
1098 {
1100  return regFile.readFloatReg(phys_reg);
1101 }
1102 
1105 {
1107  return regFile.readVecReg(phys_reg);
1108 }
1109 
1112 {
1114  return regFile.getWritableVecReg(phys_reg);
1115 }
1116 
1117 RegVal
1119 {
1121  return regFile.readVecElem(phys_reg);
1122 }
1123 
1126 {
1128  return regFile.readVecPredReg(phys_reg);
1129 }
1130 
1133 {
1135  return regFile.getWritableVecPredReg(phys_reg);
1136 }
1137 
1138 RegVal
1140 {
1142  return regFile.readCCReg(phys_reg);
1143 }
1144 
1145 void
1147 {
1149  regFile.setIntReg(phys_reg, val);
1150 }
1151 
1152 void
1154 {
1156  regFile.setFloatReg(phys_reg, val);
1157 }
1158 
1159 void
1161 {
1163  regFile.setVecReg(phys_reg, val);
1164 }
1165 
1166 void
1168 {
1170  regFile.setVecElem(phys_reg, val);
1171 }
1172 
1173 void
1176 {
1178  regFile.setVecPredReg(phys_reg, val);
1179 }
1180 
1181 void
1183 {
1185  regFile.setCCReg(phys_reg, val);
1186 }
1187 
1188 RegVal
1190 {
1191  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1192  RegId(IntRegClass, reg_idx));
1193 
1194  return regFile.readIntReg(phys_reg);
1195 }
1196 
1197 RegVal
1199 {
1200  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1201  RegId(FloatRegClass, reg_idx));
1202 
1203  return regFile.readFloatReg(phys_reg);
1204 }
1205 
1207 CPU::readArchVecReg(int reg_idx, ThreadID tid) const
1208 {
1209  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1210  RegId(VecRegClass, reg_idx));
1211  return regFile.readVecReg(phys_reg);
1212 }
1213 
1216 {
1217  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1218  RegId(VecRegClass, reg_idx));
1219  return regFile.getWritableVecReg(phys_reg);
1220 }
1221 
1222 RegVal
1224  const RegIndex& reg_idx, const ElemIndex& ldx, ThreadID tid) const
1225 {
1226  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1227  RegId(VecElemClass, reg_idx, ldx));
1228  return regFile.readVecElem(phys_reg);
1229 }
1230 
1232 CPU::readArchVecPredReg(int reg_idx, ThreadID tid) const
1233 {
1234  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1235  RegId(VecPredRegClass, reg_idx));
1236  return regFile.readVecPredReg(phys_reg);
1237 }
1238 
1241 {
1242  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1243  RegId(VecPredRegClass, reg_idx));
1244  return regFile.getWritableVecPredReg(phys_reg);
1245 }
1246 
1247 RegVal
1248 CPU::readArchCCReg(int reg_idx, ThreadID tid)
1249 {
1250  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1251  RegId(CCRegClass, reg_idx));
1252 
1253  return regFile.readCCReg(phys_reg);
1254 }
1255 
1256 void
1258 {
1259  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1260  RegId(IntRegClass, reg_idx));
1261 
1262  regFile.setIntReg(phys_reg, val);
1263 }
1264 
1265 void
1267 {
1268  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1269  RegId(FloatRegClass, reg_idx));
1270 
1271  regFile.setFloatReg(phys_reg, val);
1272 }
1273 
1274 void
1276  ThreadID tid)
1277 {
1278  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1279  RegId(VecRegClass, reg_idx));
1280  regFile.setVecReg(phys_reg, val);
1281 }
1282 
1283 void
1284 CPU::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1285  RegVal val, ThreadID tid)
1286 {
1287  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1288  RegId(VecElemClass, reg_idx, ldx));
1289  regFile.setVecElem(phys_reg, val);
1290 }
1291 
1292 void
1295 {
1296  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1297  RegId(VecPredRegClass, reg_idx));
1298  regFile.setVecPredReg(phys_reg, val);
1299 }
1300 
1301 void
1303 {
1304  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1305  RegId(CCRegClass, reg_idx));
1306 
1307  regFile.setCCReg(phys_reg, val);
1308 }
1309 
1310 const PCStateBase &
1312 {
1313  return commit.pcState(tid);
1314 }
1315 
1316 void
1318 {
1319  commit.pcState(val, tid);
1320 }
1321 
1322 void
1324 {
1325  thread[tid]->noSquashFromTC = true;
1326  commit.generateTCEvent(tid);
1327 }
1328 
1331 {
1332  instList.push_back(inst);
1333 
1334  return --(instList.end());
1335 }
1336 
1337 void
1339 {
1340  // Keep an instruction count.
1341  if (!inst->isMicroop() || inst->isLastMicroop()) {
1342  thread[tid]->numInst++;
1343  thread[tid]->threadStats.numInsts++;
1344  cpuStats.committedInsts[tid]++;
1345 
1346  // Check for instruction-count-based events.
1347  thread[tid]->comInstEventQueue.serviceEvents(thread[tid]->numInst);
1348  }
1349  thread[tid]->numOp++;
1350  thread[tid]->threadStats.numOps++;
1351  cpuStats.committedOps[tid]++;
1352 
1353  probeInstCommit(inst->staticInst, inst->pcState().instAddr());
1354 }
1355 
1356 void
1358 {
1359  DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1360  "[sn:%lli]\n",
1361  inst->threadNumber, inst->pcState(), inst->seqNum);
1362 
1363  removeInstsThisCycle = true;
1364 
1365  // Remove the front instruction.
1366  removeList.push(inst->getInstListIt());
1367 }
1368 
1369 void
1371 {
1372  DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1373  " list.\n", tid);
1374 
1375  ListIt end_it;
1376 
1377  bool rob_empty = false;
1378 
1379  if (instList.empty()) {
1380  return;
1381  } else if (rob.isEmpty(tid)) {
1382  DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1383  end_it = instList.begin();
1384  rob_empty = true;
1385  } else {
1386  end_it = (rob.readTailInst(tid))->getInstListIt();
1387  DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1388  }
1389 
1390  removeInstsThisCycle = true;
1391 
1392  ListIt inst_it = instList.end();
1393 
1394  inst_it--;
1395 
1396  // Walk through the instruction list, removing any instructions
1397  // that were inserted after the given instruction iterator, end_it.
1398  while (inst_it != end_it) {
1399  assert(!instList.empty());
1400 
1401  squashInstIt(inst_it, tid);
1402 
1403  inst_it--;
1404  }
1405 
1406  // If the ROB was empty, then we actually need to remove the first
1407  // instruction as well.
1408  if (rob_empty) {
1409  squashInstIt(inst_it, tid);
1410  }
1411 }
1412 
1413 void
1415 {
1416  assert(!instList.empty());
1417 
1418  removeInstsThisCycle = true;
1419 
1420  ListIt inst_iter = instList.end();
1421 
1422  inst_iter--;
1423 
1424  DPRINTF(O3CPU, "Deleting instructions from instruction "
1425  "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1426  tid, seq_num, (*inst_iter)->seqNum);
1427 
1428  while ((*inst_iter)->seqNum > seq_num) {
1429 
1430  bool break_loop = (inst_iter == instList.begin());
1431 
1432  squashInstIt(inst_iter, tid);
1433 
1434  inst_iter--;
1435 
1436  if (break_loop)
1437  break;
1438  }
1439 }
1440 
1441 void
1442 CPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1443 {
1444  if ((*instIt)->threadNumber == tid) {
1445  DPRINTF(O3CPU, "Squashing instruction, "
1446  "[tid:%i] [sn:%lli] PC %s\n",
1447  (*instIt)->threadNumber,
1448  (*instIt)->seqNum,
1449  (*instIt)->pcState());
1450 
1451  // Mark it as squashed.
1452  (*instIt)->setSquashed();
1453 
1454  // @todo: Formulate a consistent method for deleting
1455  // instructions from the instruction list
1456  // Remove the instruction from the list.
1457  removeList.push(instIt);
1458  }
1459 }
1460 
1461 void
1463 {
1464  while (!removeList.empty()) {
1465  DPRINTF(O3CPU, "Removing instruction, "
1466  "[tid:%i] [sn:%lli] PC %s\n",
1467  (*removeList.front())->threadNumber,
1468  (*removeList.front())->seqNum,
1469  (*removeList.front())->pcState());
1470 
1471  instList.erase(removeList.front());
1472 
1473  removeList.pop();
1474  }
1475 
1476  removeInstsThisCycle = false;
1477 }
1478 /*
1479 void
1480 CPU::removeAllInsts()
1481 {
1482  instList.clear();
1483 }
1484 */
1485 void
1487 {
1488  int num = 0;
1489 
1490  ListIt inst_list_it = instList.begin();
1491 
1492  cprintf("Dumping Instruction List\n");
1493 
1494  while (inst_list_it != instList.end()) {
1495  cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1496  "Squashed:%i\n\n",
1497  num, (*inst_list_it)->pcState().instAddr(),
1498  (*inst_list_it)->threadNumber,
1499  (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1500  (*inst_list_it)->isSquashed());
1501  inst_list_it++;
1502  ++num;
1503  }
1504 }
1505 /*
1506 void
1507 CPU::wakeDependents(const DynInstPtr &inst)
1508 {
1509  iew.wakeDependents(inst);
1510 }
1511 */
1512 void
1514 {
1515  if (activityRec.active() || tickEvent.scheduled()) {
1516  DPRINTF(Activity, "CPU already running.\n");
1517  return;
1518  }
1519 
1520  DPRINTF(Activity, "Waking up CPU\n");
1521 
1522  Cycles cycles(curCycle() - lastRunningCycle);
1523  // @todo: This is an oddity that is only here to match the stats
1524  if (cycles > 1) {
1525  --cycles;
1526  cpuStats.idleCycles += cycles;
1527  baseStats.numCycles += cycles;
1528  }
1529 
1530  schedule(tickEvent, clockEdge());
1531 }
1532 
1533 void
1535 {
1537  return;
1538 
1539  wakeCPU();
1540 
1541  DPRINTF(Quiesce, "Suspended Processor woken\n");
1542  threadContexts[tid]->activate();
1543 }
1544 
1545 ThreadID
1547 {
1548  for (ThreadID tid = 0; tid < numThreads; tid++) {
1549  if (!tids[tid]) {
1550  tids[tid] = true;
1551  return tid;
1552  }
1553  }
1554 
1555  return InvalidThreadID;
1556 }
1557 
1558 void
1560 {
1561  if (activeThreads.size() > 1) {
1562  //DEFAULT TO ROUND ROBIN SCHEME
1563  //e.g. Move highest priority to end of thread list
1564  std::list<ThreadID>::iterator list_begin = activeThreads.begin();
1565 
1566  unsigned high_thread = *list_begin;
1567 
1568  activeThreads.erase(list_begin);
1569 
1570  activeThreads.push_back(high_thread);
1571  }
1572 }
1573 
1574 void
1576 {
1577  DPRINTF(O3CPU, "Thread %d is inserted to exitingThreads list\n", tid);
1578 
1579  // the thread trying to exit can't be already halted
1580  assert(tcBase(tid)->status() != gem5::ThreadContext::Halted);
1581 
1582  // make sure the thread has not been added to the list yet
1583  assert(exitingThreads.count(tid) == 0);
1584 
1585  // add the thread to exitingThreads list to mark that this thread is
1586  // trying to exit. The boolean value in the pair denotes if a thread is
1587  // ready to exit. The thread is not ready to exit until the corresponding
1588  // exit trap event is processed in the future. Until then, it'll be still
1589  // an active thread that is trying to exit.
1590  exitingThreads.emplace(std::make_pair(tid, false));
1591 }
1592 
1593 bool
1595 {
1596  return exitingThreads.count(tid) == 1;
1597 }
1598 
1599 void
1601 {
1602  assert(exitingThreads.count(tid) == 1);
1603 
1604  // exit trap event has been processed. Now, the thread is ready to exit
1605  // and be removed from the CPU.
1606  exitingThreads[tid] = true;
1607 
1608  // we schedule a threadExitEvent in the next cycle to properly clean
1609  // up the thread's states in the pipeline. threadExitEvent has lower
1610  // priority than tickEvent, so the cleanup will happen at the very end
1611  // of the next cycle after all pipeline stages complete their operations.
1612  // We want all stages to complete squashing instructions before doing
1613  // the cleanup.
1614  if (!threadExitEvent.scheduled()) {
1615  schedule(threadExitEvent, nextCycle());
1616  }
1617 }
1618 
1619 void
1621 {
1622  // there must be at least one thread trying to exit
1623  assert(exitingThreads.size() > 0);
1624 
1625  // terminate all threads that are ready to exit
1626  auto it = exitingThreads.begin();
1627  while (it != exitingThreads.end()) {
1628  ThreadID thread_id = it->first;
1629  bool readyToExit = it->second;
1630 
1631  if (readyToExit) {
1632  DPRINTF(O3CPU, "Exiting thread %d\n", thread_id);
1633  haltContext(thread_id);
1635  it = exitingThreads.erase(it);
1636  } else {
1637  it++;
1638  }
1639  }
1640 }
1641 
1642 void
1643 CPU::htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
1644  HtmFailureFaultCause cause)
1645 {
1646  const Addr addr = 0x0ul;
1647  const int size = 8;
1648  const Request::Flags flags =
1650 
1651  // O3-specific actions
1654 
1655  // notify l1 d-cache (ruby) that core has aborted transaction
1656  RequestPtr req =
1657  std::make_shared<Request>(addr, size, flags, _dataRequestorId);
1658 
1659  req->taskId(taskId());
1660  req->setContext(thread[tid]->contextId());
1661  req->setHtmAbortCause(cause);
1662 
1663  assert(req->isHTMAbort());
1664 
1665  PacketPtr abort_pkt = Packet::createRead(req);
1666  uint8_t *memData = new uint8_t[8];
1667  assert(memData);
1668  abort_pkt->dataStatic(memData);
1669  abort_pkt->setHtmTransactional(htm_uid);
1670 
1671  // TODO include correct error handling here
1672  if (!iew.ldstQueue.getDataPort().sendTimingReq(abort_pkt)) {
1673  panic("HTM abort signal was not sent to the memory subsystem.");
1674  }
1675 }
1676 
1677 } // namespace o3
1678 } // namespace gem5
gem5::o3::Rename::isDrained
bool isDrained() const
Has the stage drained?
Definition: rename.cc:305
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::o3::CPU::setArchIntReg
void setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
Architectural register accessors.
Definition: cpu.cc:1257
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::Request::HTM_ABORT
@ HTM_ABORT
The request aborts a HTM transaction.
Definition: request.hh:216
gem5::o3::PhysRegFile::setCCReg
void setCCReg(PhysRegIdPtr phys_reg, RegVal val)
Sets a condition-code register to the given value.
Definition: regfile.hh:337
gem5::o3::CPU::addThreadToExitingList
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
Definition: cpu.cc:1575
gem5::o3::CPU::setVecElem
void setVecElem(PhysRegIdPtr reg_idx, RegVal val)
Definition: cpu.cc:1167
gem5::o3::PhysRegFile::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(PhysRegIdPtr phys_reg)
Reads a vector register for modification.
Definition: regfile.hh:218
gem5::o3::Commit::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: commit.cc:400
gem5::o3::CPU::dumpInsts
void dumpInsts()
Debug function to print all instructions on the list.
Definition: cpu.cc:1486
gem5::o3::CPU::ppDataAccessComplete
ProbePointArg< std::pair< DynInstPtr, PacketPtr > > * ppDataAccessComplete
Definition: cpu.hh:175
gem5::o3::CPU::isCpuDrained
bool isCpuDrained() const
Check if a system is in a drained state.
Definition: cpu.cc:951
gem5::o3::CPU::tids
std::vector< ThreadID > tids
Available thread ids in the cpu.
Definition: cpu.hh:599
gem5::o3::CPU::CPUStats::miscRegfileWrites
statistics::Scalar miscRegfileWrites
Definition: cpu.hh:669
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:109
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::o3::CPU::removeList
std::queue< ListIt > removeList
List of all the instructions that will be removed at the end of this cycle.
Definition: cpu.hh:440
gem5::o3::Rename::tick
void tick()
Ticks rename, which processes all input signals and attempts to rename as many instructions as possib...
Definition: rename.cc:389
gem5::o3::PhysRegFile::setVecElem
void setVecElem(PhysRegIdPtr phys_reg, RegVal val)
Sets a vector register to the given value.
Definition: regfile.hh:311
gem5::o3::Commit::regProbePoints
void regProbePoints()
Registers probes.
Definition: commit.cc:139
gem5::o3::Rename::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: rename.cc:325
gem5::o3::CPU::CPUStats::fpRegfileWrites
statistics::Scalar fpRegfileWrites
Definition: cpu.hh:657
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::CPU::readCCReg
RegVal readCCReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1139
gem5::o3::CPU::removeInstsThisCycle
bool removeInstsThisCycle
Records if instructions need to be removed this cycle due to being retired or squashed.
Definition: cpu.hh:452
gem5::o3::PhysRegFile::readVecReg
const TheISA::VecRegContainer & readVecReg(PhysRegIdPtr phys_reg) const
Reads a vector register.
Definition: regfile.hh:205
gem5::o3::CPU::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: cpu.hh:97
gem5::o3::CPU::cpuStats
gem5::o3::CPU::CPUStats cpuStats
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::o3::CPU::globalSeqNum
InstSeqNum globalSeqNum
The global sequence number counter.
Definition: cpu.hh:572
gem5::o3::CPU::removeInstsUntil
void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
Remove all instructions younger than the given sequence number.
Definition: cpu.cc:1414
gem5::o3::ROB::readTailInst
DynInstPtr readTailInst(ThreadID tid)
Returns pointer to the tail instruction within the ROB.
Definition: rob.cc:516
system.hh
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::o3::CPU::CPU
CPU(const O3CPUParams &params)
Constructs a CPU with the given parameters.
Definition: cpu.cc:73
gem5::o3::Commit::drain
void drain()
Initializes the draining of commit.
Definition: commit.cc:348
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
gem5::o3::PhysRegFile::setVecPredReg
void setVecPredReg(PhysRegIdPtr phys_reg, const TheISA::VecPredRegContainer &val)
Sets a predicate register to the given value.
Definition: regfile.hh:324
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::o3::CPU::regFile
PhysRegFile regFile
The register file.
Definition: cpu.hh:471
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::o3::PhysRegFile::readFloatReg
RegVal readFloatReg(PhysRegIdPtr phys_reg) const
Definition: regfile.hh:191
gem5::o3::LSQ::getCount
int getCount()
Returns the number of instructions in all of the queues.
Definition: lsq.cc:454
gem5::o3::CPU::decode
Decode decode
The decode stage.
Definition: cpu.hh:459
gem5::o3::CPU::CPUStats::ccRegfileWrites
statistics::Scalar ccRegfileWrites
Definition: cpu.hh:666
gem5::o3::CPU::activeThreads
std::list< ThreadID > activeThreads
Active Threads List.
Definition: cpu.hh:486
gem5::o3::Commit::setThreads
void setThreads(std::vector< ThreadState * > &threads)
Sets the list of threads.
Definition: commit.cc:248
gem5::o3::CPU::freeList
UnifiedFreeList freeList
The free list.
Definition: cpu.hh:474
gem5::o3::PhysRegFile::readIntReg
RegVal readIntReg(PhysRegIdPtr phys_reg) const
Reads an integer register.
Definition: regfile.hh:181
gem5::o3::CPU::processInterrupts
void processInterrupts(const Fault &interrupt)
Processes any an interrupt fault.
Definition: cpu.cc:828
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::o3::Commit::pcState
const PCStateBase & pcState(ThreadID tid)
Reads the PC of a specific thread.
Definition: commit.hh:309
gem5::o3::Decode::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: decode.cc:98
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::o3::Fetch::drainStall
void drainStall(ThreadID tid)
Stall the fetch stage after reaching a safe drain point.
Definition: fetch.cc:458
gem5::o3::CPU::readArchFloatReg
RegVal readArchFloatReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1198
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::o3::CPU::CPUStats::quiesceCycles
statistics::Scalar quiesceCycles
Stat for total number of cycles the CPU spends descheduled due to a quiesce operation or waiting for ...
Definition: cpu.hh:637
gem5::o3::CPU::getInterrupts
Fault getInterrupts()
Returns the Fault for any valid interrupt.
Definition: cpu.cc:821
gem5::o3::CPU::squashInstIt
void squashInstIt(const ListIt &instIt, ThreadID tid)
Removes the instruction pointed to by the iterator.
Definition: cpu.cc:1442
gem5::o3::CPU::htmSendAbortSignal
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: cpu.cc:1643
gem5::o3::Fetch::wakeFromQuiesce
void wakeFromQuiesce()
Tells fetch to wake up from a quiesce instruction.
Definition: fetch.cc:467
cur_tick.hh
gem5::o3::IEW::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: iew.cc:392
gem5::o3::CPU::readArchCCReg
RegVal readArchCCReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1248
gem5::o3::CPU::CPUStats::miscRegfileReads
statistics::Scalar miscRegfileReads
Definition: cpu.hh:668
gem5::o3::Commit::startupStage
void startupStage()
Initializes stage by sending back the number of free entries.
Definition: commit.cc:314
gem5::o3::CPU::CPUStats::intRegfileReads
statistics::Scalar intRegfileReads
Definition: cpu.hh:653
gem5::o3::IEW::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: iew.cc:293
gem5::o3::CPU::_status
Status _status
Overall CPU status.
Definition: cpu.hh:115
gem5::Packet::setHtmTransactional
void setHtmTransactional(uint64_t val)
Stipulates that this packet/request originates in the CPU executing in transactional mode,...
Definition: packet.cc:521
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::o3::CPU::timeBuffer
TimeBuffer< TimeStruct > timeBuffer
The main time buffer to do backwards communication.
Definition: cpu.hh:516
gem5::o3::CPU::readVecElem
RegVal readVecElem(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1118
gem5::ThreadContext::setStatus
virtual void setStatus(Status new_status)=0
gem5::ActivityRecorder::advance
void advance()
Advances the activity buffer, decrementing the activityCount if active communication just left the ti...
Definition: activity.cc:71
gem5::o3::CPU::removeThread
void removeThread(ThreadID tid)
Remove all of a thread's context from CPU.
Definition: cpu.cc:769
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::o3::CPU::setVecReg
void setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer &val)
Definition: cpu.cc:1160
gem5::o3::CPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1083
dyn_inst.hh
gem5::o3::CPU::CPUStats::totalIpc
statistics::Formula totalIpc
Stat for the total IPC.
Definition: cpu.hh:650
gem5::o3::CPU::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(PhysRegIdPtr reg_idx)
Definition: cpu.cc:1132
gem5::o3::CPU::renameMap
UnifiedRenameMap renameMap[MaxThreads]
The rename map.
Definition: cpu.hh:477
gem5::o3::Fetch::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: fetch.cc:298
gem5::o3::CPU::instList
std::list< DynInstPtr > instList
List of all the instructions in flight.
Definition: cpu.hh:435
gem5::o3::PhysRegFile::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(PhysRegIdPtr phys_reg)
Definition: regfile.hh:253
gem5::o3::Fetch::isDrained
bool isDrained() const
Has the stage drained?
Definition: fetch.cc:420
gem5::o3::CPU::verifyMemoryMode
void verifyMemoryMode() const override
Definition: cpu.cc:1055
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::o3::CPU::deactivateThread
void deactivateThread(ThreadID tid)
Remove Thread from Active Threads List.
Definition: cpu.cc:592
gem5::o3::CPU::CPUStats::intRegfileWrites
statistics::Scalar intRegfileWrites
Definition: cpu.hh:654
gem5::o3::CPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Definition: cpu.cc:857
gem5::EventBase::CPU_Exit_Pri
static const Priority CPU_Exit_Pri
If we want to exit a thread in a CPU, it comes after CPU_Tick_Pri.
Definition: eventq.hh:211
gem5::o3::CPU::readFloatReg
RegVal readFloatReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1097
gem5::o3::CPU::CPUStats::cpi
statistics::Formula cpi
Stat for the CPI per thread.
Definition: cpu.hh:644
gem5::o3::CPU::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: cpu.cc:940
gem5::o3::CPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: cpu.cc:851
gem5::o3::CPU::cleanUpRemovedInsts
void cleanUpRemovedInsts()
Cleans up all instructions on the remove list.
Definition: cpu.cc:1462
gem5::o3::Commit::deactivateThread
void deactivateThread(ThreadID tid)
Deschedules a thread from scheduling.
Definition: commit.cc:415
gem5::o3::ROB::resetEntries
void resetEntries()
Re-adjust ROB partitioning.
Definition: rob.cc:148
gem5::o3::CPU::iewQueue
TimeBuffer< IEWStruct > iewQueue
The IEW stage's instruction queue.
Definition: cpu.hh:528
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::o3::CPU::ppInstAccessComplete
ProbePointArg< PacketPtr > * ppInstAccessComplete
Definition: cpu.hh:174
gem5::o3::IEW::startupStage
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
Definition: iew.cc:270
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:254
gem5::RefCountingPtr< StaticInst >
gem5::o3::LSQ::resetHtmStartsStops
void resetHtmStartsStops(ThreadID tid)
Definition: lsq.cc:359
gem5::o3::CPU::checker
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
Definition: cpu.hh:578
gem5::o3::CPU::unscheduleTickEvent
void unscheduleTickEvent()
Unschedule tick event, regardless of its current state.
Definition: cpu.hh:137
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::CPU::totalInsts
Counter totalInsts() const override
Count the Total Instructions Committed in the CPU.
Definition: cpu.cc:616
gem5::o3::Fetch::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: fetch.cc:403
gem5::PhysRegIdPtr
PhysRegId * PhysRegIdPtr
Definition: reg_class.hh:334
gem5::o3::CPU::CPUStats::committedInsts
statistics::Vector committedInsts
Stat for the number of committed instructions per thread.
Definition: cpu.hh:639
gem5::o3::CPU::CPUStats::idleCycles
statistics::Scalar idleCycles
Stat for total number of cycles the CPU spends descheduled.
Definition: cpu.hh:634
gem5::o3::CPU::setArchFloatReg
void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
Definition: cpu.cc:1266
gem5::o3::IEW::instQueue
InstructionQueue instQueue
Instruction queue.
Definition: iew.hh:355
gem5::o3::CPU::decodeQueue
TimeBuffer< DecodeStruct > decodeQueue
The decode stage's instruction queue.
Definition: cpu.hh:522
gem5::Packet::dataStatic
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
Definition: packet.hh:1134
gem5::o3::Fetch::drainResume
void drainResume()
Resume after a drain.
Definition: fetch.cc:394
gem5::o3::CPU::CPUStats::totalCpi
statistics::Formula totalCpi
Stat for the total CPI.
Definition: cpu.hh:646
gem5::o3::CPU::setArchCCReg
void setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
Definition: cpu.cc:1302
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::o3::Rename::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: rename.cc:227
gem5::Flags< FlagsType >
gem5::o3::CPU::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(PhysRegIdPtr reg_idx)
Read physical vector register for modification.
Definition: cpu.cc:1111
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::o3::Commit::generateTCEvent
void generateTCEvent(ThreadID tid)
Records that commit needs to initiate a squash due to an external state update through the TC.
Definition: commit.cc:524
gem5::o3::CPU::setArchVecReg
void setArchVecReg(int reg_idx, const TheISA::VecRegContainer &val, ThreadID tid)
Definition: cpu.cc:1275
gem5::o3::Decode::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: decode.hh:132
gem5::o3::Decode::tick
void tick()
Ticks decode, processing all input signals and decoding as many instructions as possible.
Definition: decode.cc:544
gem5::o3::CPU::readArchVecPredReg
const TheISA::VecPredRegContainer & readArchVecPredReg(int reg_idx, ThreadID tid) const
Definition: cpu.cc:1232
gem5::o3::CPU::tryDrain
bool tryDrain()
Check if the pipeline has drained and signal drain done.
Definition: cpu.cc:925
gem5::o3::CPU::wakeup
virtual void wakeup(ThreadID tid) override
Definition: cpu.cc:1534
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::o3::CPU::insertThread
void insertThread(ThreadID tid)
Setup CPU to insert a thread's context.
Definition: cpu.cc:720
gem5::o3::IEW::isDrained
bool isDrained() const
Has the stage drained?
Definition: iew.cc:355
gem5::o3::CPU::setCCReg
void setCCReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1182
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::o3::CPU::CPUStats::vecPredRegfileReads
statistics::Scalar vecPredRegfileReads
Definition: cpu.hh:662
gem5::o3::PhysRegFile::readVecElem
RegVal readVecElem(PhysRegIdPtr phys_reg) const
Reads a vector element.
Definition: regfile.hh:226
gem5::o3::CPU::setIntReg
void setIntReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1146
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::CPU::scheduleTickEvent
void scheduleTickEvent(Cycles delay)
Schedule tick event, regardless of its current state.
Definition: cpu.hh:127
gem5::o3::CPU::totalOps
Counter totalOps() const override
Count the Total Ops (including micro ops) committed in the CPU.
Definition: cpu.cc:628
gem5::o3::CPU::suspendContext
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
Definition: cpu.cc:678
gem5::o3::Commit::isDrained
bool isDrained() const
Has the stage drained?
Definition: commit.cc:373
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::Commit::rob
ROB * rob
ROB interface.
Definition: commit.hh:342
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::o3::Scoreboard::setReg
void setReg(PhysRegIdPtr phys_reg)
Sets the register as ready.
Definition: scoreboard.hh:105
gem5::o3::CPU::fetch
Fetch fetch
The fetch stage.
Definition: cpu.hh:456
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::o3::CPU::scheduleThreadExitEvent
void scheduleThreadExitEvent(ThreadID tid)
If a thread is trying to exit and its corresponding trap event has been completed,...
Definition: cpu.cc:1600
gem5::o3::CPU::pcState
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1317
cpu.hh
gem5::o3::Decode::isDrained
bool isDrained() const
Has the stage drained?
Definition: decode.cc:207
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::o3::CPU::squashFromTC
void squashFromTC(ThreadID tid)
Initiates a squash of all in-flight instructions for a given thread.
Definition: cpu.cc:1323
gem5::o3::CPU::CPUStats::vecPredRegfileWrites
statistics::Scalar vecPredRegfileWrites
Definition: cpu.hh:663
gem5::o3::CPU::readIntReg
RegVal readIntReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1090
process.hh
gem5::o3::CPU::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const
Register accessors.
Definition: cpu.cc:1064
gem5::o3::Commit::resetHtmStartsStops
void resetHtmStartsStops(ThreadID)
Definition: commit.cc:435
gem5::o3::CPU::tcBase
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
Definition: cpu.hh:566
gem5::o3::CPU::activateThread
void activateThread(ThreadID tid)
Add Thread to Active Threads List.
Definition: cpu.cc:576
activity.hh
gem5::o3::CPU::thread
std::vector< ThreadState * > thread
Pointers to all of the threads in the CPU.
Definition: cpu.hh:584
gem5::o3::Fetch::deactivateThread
void deactivateThread(ThreadID tid)
For priority-based fetch policies, need to keep update priorityList.
Definition: fetch.cc:500
gem5::o3::CPU::setArchVecPredReg
void setArchVecPredReg(int reg_idx, const TheISA::VecPredRegContainer &val, ThreadID tid)
Definition: cpu.cc:1293
gem5::o3::Commit::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: commit.cc:334
gem5::o3::CPU::CPUStats::ccRegfileReads
statistics::Scalar ccRegfileReads
Definition: cpu.hh:665
gem5::o3::CPU::CPUStats::timesIdled
statistics::Scalar timesIdled
Stat for total number of times the CPU is descheduled.
Definition: cpu.hh:632
gem5::InvalidThreadID
const ThreadID InvalidThreadID
Definition: types.hh:243
gem5::o3::CPU::drain
DrainState drain() override
Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses.
Definition: cpu.cc:863
gem5::o3::CPU::wakeCPU
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
Definition: cpu.cc:1513
gem5::o3::CPU::readVecReg
const TheISA::VecRegContainer & readVecReg(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1104
gem5::o3::CPU::tickEvent
EventFunctionWrapper tickEvent
The tick event used for scheduling CPU ticks.
Definition: cpu.hh:120
gem5::o3::CPU::switchOut
void switchOut() override
Switches out this CPU.
Definition: cpu.cc:1020
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::o3::CPU::Idle
@ Idle
Definition: cpu.hh:105
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:274
gem5::o3::CPU::setArchVecElem
void setArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, RegVal val, ThreadID tid)
Definition: cpu.cc:1284
gem5::o3::CPU::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
Definition: cpu.cc:1077
gem5::o3::CPU::renameQueue
TimeBuffer< RenameStruct > renameQueue
The rename stage's instruction queue.
Definition: cpu.hh:525
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:71
std::pair
STL pair class.
Definition: stl.hh:58
gem5::o3::CPU::rob
ROB rob
The re-order buffer.
Definition: cpu.hh:483
gem5::statistics::DataWrap::precision
Derived & precision(int _precision)
Set the precision and marks this stat to print at the end of simulation.
Definition: statistics.hh:346
gem5::o3::IEW::tick
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle.
Definition: iew.cc:1432
gem5::o3::Fetch::tick
void tick()
Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible.
Definition: fetch.cc:839
gem5::o3::CPU::Running
@ Running
Definition: cpu.hh:104
gem5::o3::CPU::CPUStats::vecRegfileWrites
statistics::Scalar vecRegfileWrites
Definition: cpu.hh:660
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::CPU::CPUStats::vecRegfileReads
statistics::Scalar vecRegfileReads
Definition: cpu.hh:659
gem5::o3::CPU::CPUStats::committedOps
statistics::Vector committedOps
Stat for the number of committed ops (including micro ops) per thread.
Definition: cpu.hh:642
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
name
const std::string & name()
Definition: trace.cc:49
gem5::o3::UnifiedFreeList::getCCReg
PhysRegIdPtr getCCReg()
Gets a free cc register.
Definition: free_list.hh:197
full_system.hh
gem5::o3::CPU::getWritableArchVecReg
TheISA::VecRegContainer & getWritableArchVecReg(int reg_idx, ThreadID tid)
Read architectural vector register for modification.
Definition: cpu.cc:1215
gem5::ActivityRecorder::activity
void activity()
Records that there is activity this cycle.
Definition: activity.cc:55
gem5::o3::CPU::setFloatReg
void setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1153
gem5::o3::CPU::readArchVecElem
RegVal readArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const
Definition: cpu.cc:1223
gem5::o3::CPU::setVecPredReg
void setVecPredReg(PhysRegIdPtr reg_idx, const TheISA::VecPredRegContainer &val)
Definition: cpu.cc:1174
gem5::o3::Fetch::startupStage
void startupStage()
Initialize stage.
Definition: fetch.cc:287
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::o3::CPU::regProbePoints
void regProbePoints() override
Register probe points.
Definition: cpu.cc:344
gem5::o3::CPU::system
System * system
Pointer to the system.
Definition: cpu.hh:581
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::ActivityRecorder::reset
void reset()
Clears the time buffer and the activity count.
Definition: activity.cc:125
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::o3::CPU::lastRunningCycle
Cycles lastRunningCycle
The cycle that the CPU was last running, used for statistics.
Definition: cpu.hh:590
gem5::o3::CPU::updateThreadPriority
void updateThreadPriority()
Update The Order In Which We Process Threads.
Definition: cpu.cc:1559
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::CPU::getWritableArchVecPredReg
TheISA::VecPredRegContainer & getWritableArchVecPredReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1240
stat_control.hh
warn_if
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:273
gem5::o3::CPU::CPUStats::ipc
statistics::Formula ipc
Stat for the IPC per thread.
Definition: cpu.hh:648
gem5::o3::CPU::rename
Rename rename
The dispatch stage.
Definition: cpu.hh:462
gem5::o3::CPU::fetchQueue
TimeBuffer< FetchStruct > fetchQueue
The fetch stage's instruction queue.
Definition: cpu.hh:519
simple_thread.hh
gem5::o3::CPU::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU) override
Takes over from another CPU.
Definition: cpu.cc:1034
gem5::o3::UnifiedFreeList::getFloatReg
PhysRegIdPtr getFloatReg()
Gets a free fp register.
Definition: free_list.hh:185
gem5::o3::CPU::iew
IEW iew
The issue/execute/writeback stages.
Definition: cpu.hh:465
gem5::o3::CPU::removeInstsNotInROB
void removeInstsNotInROB(ThreadID tid)
Remove all instructions that are not currently in the ROB.
Definition: cpu.cc:1370
gem5::o3::IEW::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: iew.cc:383
gem5::Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:135
gem5::o3::CPU::exitThreads
void exitThreads()
Terminate all threads that are ready to exit.
Definition: cpu.cc:1620
gem5::o3::CPU::lastActivatedCycle
Tick lastActivatedCycle
The cycle that the CPU was last activated by a new thread.
Definition: cpu.hh:593
gem5::o3::Commit::drainResume
void drainResume()
Resumes execution after draining.
Definition: commit.cc:351
gem5::o3::Commit::executingHtmTransaction
bool executingHtmTransaction(ThreadID) const
Is the CPU currently processing a HTM transaction?
Definition: commit.cc:426
gem5::statistics::DataWrap::prereq
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Definition: statistics.hh:372
gem5::o3::CPU::commitDrained
void commitDrained(ThreadID tid)
Commit has reached a safe point to drain a thread.
Definition: cpu.cc:988
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::pseudo_inst::quiesceCycles
void quiesceCycles(ThreadContext *tc, uint64_t cycles)
Definition: pseudo_inst.cc:139
gem5::o3::Fetch::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: fetch.cc:450
gem5::o3::PhysRegFile::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(PhysRegIdPtr phys_reg) const
Reads a predicate register.
Definition: regfile.hh:241
gem5::o3::CPU::commitRenameMap
UnifiedRenameMap commitRenameMap[MaxThreads]
The commit rename map.
Definition: cpu.hh:480
gem5::o3::CPU::trap
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
Definition: cpu.cc:844
gem5::o3::CPU::drainResume
void drainResume() override
Resumes execution after a drain.
Definition: cpu.cc:991
gem5::o3::CPU::getFreeTid
ThreadID getFreeTid()
Gets a free thread id.
Definition: cpu.cc:1546
gem5::o3::CPU::addInst
ListIt addInst(const DynInstPtr &inst)
Function to add instruction onto the head of the list of the instructions.
Definition: cpu.cc:1330
gem5::o3::ROB::isEmpty
bool isEmpty() const
Returns if the ROB is empty.
Definition: rob.hh:195
gem5::o3::CPU::isThreadExiting
bool isThreadExiting(ThreadID tid) const
Is the thread trying to exit?
Definition: cpu.cc:1594
gem5::o3::Decode::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: decode.cc:198
gem5::o3::CPU::threadExitEvent
EventFunctionWrapper threadExitEvent
The exit event used for terminating all ready-to-exit threads.
Definition: cpu.hh:123
gem5::o3::UnifiedRenameMap::lookup
PhysRegIdPtr lookup(const RegId &arch_reg) const
Look up the physical register mapped to an architectural register.
Definition: rename_map.hh:261
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::CPU::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
Definition: cpu.cc:1070
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:224
gem5::o3::PhysRegFile::setFloatReg
void setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: regfile.hh:287
gem5::o3::Rename::startupStage
void startupStage()
Initializes variables for the stage.
Definition: rename.cc:221
thread_context.hh
gem5::o3::PhysRegFile::setIntReg
void setIntReg(PhysRegIdPtr phys_reg, RegVal val)
Sets an integer register to the given value.
Definition: regfile.hh:275
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::statistics::init
const FlagsType init
This Stat is Initialized.
Definition: info.hh:56
gem5::o3::CPU::SwitchedOut
@ SwitchedOut
Definition: cpu.hh:108
gem5::o3::CPU::exitingThreads
std::unordered_map< ThreadID, bool > exitingThreads
This is a list of threads that are trying to exit.
Definition: cpu.hh:493
gem5::o3::CPU::CPUStats::fpRegfileReads
statistics::Scalar fpRegfileReads
Definition: cpu.hh:656
gem5::o3::CPU::readArchIntReg
RegVal readArchIntReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1189
gem5::o3::Fetch::regProbePoints
void regProbePoints()
Registers probes.
Definition: fetch.cc:152
gem5::RiscvISA::sum
Bitfield< 18 > sum
Definition: misc.hh:555
gem5::o3::LSQ::getDataPort
RequestPort & getDataPort()
Definition: lsq.hh:873
gem5::ActivityRecorder::active
bool active()
Returns if the CPU should be active.
Definition: activity.hh:91
gem5::o3::Commit::tick
void tick()
Ticks the commit stage, which tries to commit instructions.
Definition: commit.cc:629
gem5::o3::Rename::regProbePoints
void regProbePoints()
Registers probes.
Definition: rename.cc:179
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:358
gem5::o3::CPU::scoreboard
Scoreboard scoreboard
Integer Register Scoreboard.
Definition: cpu.hh:496
gem5::DrainState::Running
@ Running
Running normally.
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::o3::IEW::ldstQueue
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:358
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::o3::CPU::commit
Commit commit
The commit stage.
Definition: cpu.hh:468
cpu.hh
std::list
STL list class.
Definition: stl.hh:51
gem5::o3::CPU::haltContext
void haltContext(ThreadID tid) override
Remove Thread from Active Threads List && Remove Thread Context from CPU.
Definition: cpu.cc:698
gem5::EventBase::CPU_Tick_Pri
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:204
gem5::o3::PhysRegFile::setVecReg
void setVecReg(PhysRegIdPtr phys_reg, const TheISA::VecRegContainer &val)
Sets a vector register to the given value.
Definition: regfile.hh:299
gem5::o3::CPU::activityRec
ActivityRecorder activityRec
The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and...
Definition: cpu.hh:535
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::o3::Decode::startupStage
void startupStage()
Definition: decode.cc:92
gem5::o3::CPU::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1125
gem5::Packet::createRead
static PacketPtr createRead(const RequestPtr &req)
Constructor-like methods that return Packets based on Request objects.
Definition: packet.hh:1007
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
thread_context.hh
limits.hh
gem5::o3::CPU::activateContext
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
Definition: cpu.cc:640
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1040
gem5::o3::Rename::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: rename.cc:319
gem5::o3::UnifiedFreeList::getIntReg
PhysRegIdPtr getIntReg()
Gets a free integer register.
Definition: free_list.hh:182
gem5::o3::CPU::tick
void tick()
Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should d...
Definition: cpu.cc:488
gem5::o3::PhysRegFile::readCCReg
RegVal readCCReg(PhysRegIdPtr phys_reg)
Reads a condition-code register.
Definition: regfile.hh:262
gem5::o3::CPU::startup
void startup() override
Definition: cpu.cc:564
gem5::o3::CPU::CPUStats::CPUStats
CPUStats(CPU *cpu)
Definition: cpu.cc:360
thread_context.hh
gem5::o3::CPU::isa
std::vector< TheISA::ISA * > isa
Definition: cpu.hh:498
gem5::o3::Commit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: commit.cc:358
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::o3::CPU::instDone
void instDone(ThreadID tid, const DynInstPtr &inst)
Function to tell the CPU that an instruction has completed.
Definition: cpu.cc:1338
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::CPU::init
void init() override
Initialize the CPU.
Definition: cpu.cc:546
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::o3::UnifiedRenameMap::setEntry
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
Definition: rename_map.hh:302
gem5::o3::CPU::removeFrontInst
void removeFrontInst(const DynInstPtr &inst)
Remove an instruction from the front end of the list.
Definition: cpu.cc:1357
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::o3::CPU::readArchVecReg
const TheISA::VecRegContainer & readArchVecReg(int reg_idx, ThreadID tid) const
Definition: cpu.cc:1207
gem5::Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:117
gem5::o3::IEW::regProbePoints
void regProbePoints()
Registers probes.
Definition: iew.cc:125
gem5::o3::InstructionQueue::getCount
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
Definition: inst_queue.hh:274

Generated on Wed May 4 2022 12:13:46 for gem5 by doxygen 1.8.17