gem5  v22.0.0.2
cpu.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019-2020 ARM Limited
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Copyright (c) 2004-2006 The Regents of The University of Michigan
16  * Copyright (c) 2011 Regents of the University of California
17  * All rights reserved.
18  *
19  * Redistribution and use in source and binary forms, with or without
20  * modification, are permitted provided that the following conditions are
21  * met: redistributions of source code must retain the above copyright
22  * notice, this list of conditions and the following disclaimer;
23  * redistributions in binary form must reproduce the above copyright
24  * notice, this list of conditions and the following disclaimer in the
25  * documentation and/or other materials provided with the distribution;
26  * neither the name of the copyright holders nor the names of its
27  * contributors may be used to endorse or promote products derived from
28  * this software without specific prior written permission.
29  *
30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41  */
42 
43 #include "cpu/o3/cpu.hh"
44 
45 #include "config/the_isa.hh"
46 #include "cpu/activity.hh"
47 #include "cpu/checker/cpu.hh"
49 #include "cpu/o3/dyn_inst.hh"
50 #include "cpu/o3/limits.hh"
51 #include "cpu/o3/thread_context.hh"
52 #include "cpu/simple_thread.hh"
53 #include "cpu/thread_context.hh"
54 #include "debug/Activity.hh"
55 #include "debug/Drain.hh"
56 #include "debug/O3CPU.hh"
57 #include "debug/Quiesce.hh"
58 #include "enums/MemoryMode.hh"
59 #include "sim/cur_tick.hh"
60 #include "sim/full_system.hh"
61 #include "sim/process.hh"
62 #include "sim/stat_control.hh"
63 #include "sim/system.hh"
64 
65 namespace gem5
66 {
67 
68 struct BaseCPUParams;
69 
70 namespace o3
71 {
72 
73 CPU::CPU(const BaseO3CPUParams &params)
74  : BaseCPU(params),
75  mmu(params.mmu),
76  tickEvent([this]{ tick(); }, "O3CPU tick",
77  false, Event::CPU_Tick_Pri),
78  threadExitEvent([this]{ exitThreads(); }, "O3CPU exit threads",
79  false, Event::CPU_Exit_Pri),
80 #ifndef NDEBUG
81  instcount(0),
82 #endif
83  removeInstsThisCycle(false),
84  fetch(this, params),
85  decode(this, params),
86  rename(this, params),
87  iew(this, params),
88  commit(this, params),
89 
90  regFile(params.numPhysIntRegs,
91  params.numPhysFloatRegs,
92  params.numPhysVecRegs,
93  params.numPhysVecPredRegs,
94  params.numPhysCCRegs,
95  params.isa[0]->regClasses()),
96 
97  freeList(name() + ".freelist", &regFile),
98 
99  rob(this, params),
100 
101  scoreboard(name() + ".scoreboard", regFile.totalNumPhysRegs()),
102 
103  isa(numThreads, NULL),
104 
105  timeBuffer(params.backComSize, params.forwardComSize),
106  fetchQueue(params.backComSize, params.forwardComSize),
107  decodeQueue(params.backComSize, params.forwardComSize),
108  renameQueue(params.backComSize, params.forwardComSize),
109  iewQueue(params.backComSize, params.forwardComSize),
110  activityRec(name(), NumStages,
111  params.backComSize + params.forwardComSize,
112  params.activity),
113 
114  globalSeqNum(1),
115  system(params.system),
116  lastRunningCycle(curCycle()),
117  cpuStats(this)
118 {
119  fatal_if(FullSystem && params.numThreads > 1,
120  "SMT is not supported in O3 in full system mode currently.");
121 
122  fatal_if(!FullSystem && params.numThreads < params.workload.size(),
123  "More workload items (%d) than threads (%d) on CPU %s.",
124  params.workload.size(), params.numThreads, name());
125 
126  if (!params.switched_out) {
127  _status = Running;
128  } else {
129  _status = SwitchedOut;
130  }
131 
132  if (params.checker) {
133  BaseCPU *temp_checker = params.checker;
134  checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
135  checker->setIcachePort(&fetch.getInstPort());
136  checker->setSystem(params.system);
137  } else {
138  checker = NULL;
139  }
140 
141  if (!FullSystem) {
142  thread.resize(numThreads);
143  tids.resize(numThreads);
144  }
145 
146  // The stages also need their CPU pointer setup. However this
147  // must be done at the upper level CPU because they have pointers
148  // to the upper level CPU, and not this CPU.
149 
150  // Set up Pointers to the activeThreads list for each stage
151  fetch.setActiveThreads(&activeThreads);
152  decode.setActiveThreads(&activeThreads);
153  rename.setActiveThreads(&activeThreads);
154  iew.setActiveThreads(&activeThreads);
155  commit.setActiveThreads(&activeThreads);
156 
157  // Give each of the stages the time buffer they will use.
158  fetch.setTimeBuffer(&timeBuffer);
159  decode.setTimeBuffer(&timeBuffer);
160  rename.setTimeBuffer(&timeBuffer);
161  iew.setTimeBuffer(&timeBuffer);
162  commit.setTimeBuffer(&timeBuffer);
163 
164  // Also setup each of the stages' queues.
165  fetch.setFetchQueue(&fetchQueue);
166  decode.setFetchQueue(&fetchQueue);
167  commit.setFetchQueue(&fetchQueue);
168  decode.setDecodeQueue(&decodeQueue);
169  rename.setDecodeQueue(&decodeQueue);
170  rename.setRenameQueue(&renameQueue);
171  iew.setRenameQueue(&renameQueue);
172  iew.setIEWQueue(&iewQueue);
173  commit.setIEWQueue(&iewQueue);
174  commit.setRenameQueue(&renameQueue);
175 
176  commit.setIEWStage(&iew);
177  rename.setIEWStage(&iew);
178  rename.setCommitStage(&commit);
179 
180  ThreadID active_threads;
181  if (FullSystem) {
182  active_threads = 1;
183  } else {
184  active_threads = params.workload.size();
185 
186  if (active_threads > MaxThreads) {
187  panic("Workload Size too large. Increase the 'MaxThreads' "
188  "constant in cpu/o3/limits.hh or edit your workload size.");
189  }
190  }
191 
192  // Make Sure That this a Valid Architeture
193  assert(numThreads);
194  const auto &regClasses = params.isa[0]->regClasses();
195 
196  assert(params.numPhysIntRegs >=
197  numThreads * regClasses.at(IntRegClass).numRegs());
198  assert(params.numPhysFloatRegs >=
199  numThreads * regClasses.at(FloatRegClass).numRegs());
200  assert(params.numPhysVecRegs >=
201  numThreads * regClasses.at(VecRegClass).numRegs());
202  assert(params.numPhysVecPredRegs >=
203  numThreads * regClasses.at(VecPredRegClass).numRegs());
204  assert(params.numPhysCCRegs >=
205  numThreads * regClasses.at(CCRegClass).numRegs());
206 
207  // Just make this a warning and go ahead anyway, to keep from having to
208  // add checks everywhere.
209  warn_if(regClasses.at(CCRegClass).numRegs() == 0 &&
210  params.numPhysCCRegs != 0,
211  "Non-zero number of physical CC regs specified, even though\n"
212  " ISA does not use them.");
213 
214  rename.setScoreboard(&scoreboard);
215  iew.setScoreboard(&scoreboard);
216 
217  // Setup the rename map for whichever stages need it.
218  for (ThreadID tid = 0; tid < numThreads; tid++) {
219  isa[tid] = dynamic_cast<TheISA::ISA *>(params.isa[tid]);
220  commitRenameMap[tid].init(regClasses, &regFile, &freeList);
221  renameMap[tid].init(regClasses, &regFile, &freeList);
222  }
223 
224  // Initialize rename map to assign physical registers to the
225  // architectural registers for active threads only.
226  for (ThreadID tid = 0; tid < active_threads; tid++) {
227  for (auto type = (RegClassType)0; type <= CCRegClass;
228  type = (RegClassType)(type + 1)) {
229  for (RegIndex ridx = 0; ridx < regClasses.at(type).numRegs();
230  ++ridx) {
231  // Note that we can't use the rename() method because we don't
232  // want special treatment for the zero register at this point
233  RegId rid = RegId(type, ridx);
234  PhysRegIdPtr phys_reg = freeList.getReg(type);
235  renameMap[tid].setEntry(rid, phys_reg);
236  commitRenameMap[tid].setEntry(rid, phys_reg);
237  }
238  }
239  }
240 
241  rename.setRenameMap(renameMap);
242  commit.setRenameMap(commitRenameMap);
243  rename.setFreeList(&freeList);
244 
245  // Setup the ROB for whichever stages need it.
246  commit.setROB(&rob);
247 
248  lastActivatedCycle = 0;
249 
250  DPRINTF(O3CPU, "Creating O3CPU object.\n");
251 
252  // Setup any thread state.
253  thread.resize(numThreads);
254 
255  for (ThreadID tid = 0; tid < numThreads; ++tid) {
256  if (FullSystem) {
257  // SMT is not supported in FS mode yet.
258  assert(numThreads == 1);
259  thread[tid] = new ThreadState(this, 0, NULL);
260  } else {
261  if (tid < params.workload.size()) {
262  DPRINTF(O3CPU, "Workload[%i] process is %#x", tid,
263  thread[tid]);
264  thread[tid] = new ThreadState(this, tid, params.workload[tid]);
265  } else {
266  //Allocate Empty thread so M5 can use later
267  //when scheduling threads to CPU
268  Process* dummy_proc = NULL;
269 
270  thread[tid] = new ThreadState(this, tid, dummy_proc);
271  }
272  }
273 
275 
276  // Setup the TC that will serve as the interface to the threads/CPU.
277  auto *o3_tc = new ThreadContext;
278 
279  tc = o3_tc;
280 
281  // If we're using a checker, then the TC should be the
282  // CheckerThreadContext.
283  if (params.checker) {
284  tc = new CheckerThreadContext<ThreadContext>(o3_tc, checker);
285  }
286 
287  o3_tc->cpu = this;
288  o3_tc->thread = thread[tid];
289 
290  // Give the thread the TC.
291  thread[tid]->tc = tc;
292 
293  // Add the TC to the CPU's list of TC's.
294  threadContexts.push_back(tc);
295  }
296 
297  // O3CPU always requires an interrupt controller.
298  if (!params.switched_out && interrupts.empty()) {
299  fatal("O3CPU %s has no interrupt controller.\n"
300  "Ensure createInterruptController() is called.\n", name());
301  }
302 }
303 
304 void
306 {
307  BaseCPU::regProbePoints();
308 
310  getProbeManager(), "InstAccessComplete");
313  getProbeManager(), "DataAccessComplete");
314 
319 }
320 
322  : statistics::Group(cpu),
323  ADD_STAT(timesIdled, statistics::units::Count::get(),
324  "Number of times that the entire CPU went into an idle state "
325  "and unscheduled itself"),
326  ADD_STAT(idleCycles, statistics::units::Cycle::get(),
327  "Total number of cycles that the CPU has spent unscheduled due "
328  "to idling"),
329  ADD_STAT(quiesceCycles, statistics::units::Cycle::get(),
330  "Total number of cycles that CPU has spent quiesced or waiting "
331  "for an interrupt"),
332  ADD_STAT(committedInsts, statistics::units::Count::get(),
333  "Number of Instructions Simulated"),
334  ADD_STAT(committedOps, statistics::units::Count::get(),
335  "Number of Ops (including micro ops) Simulated"),
336  ADD_STAT(cpi, statistics::units::Rate<
337  statistics::units::Cycle, statistics::units::Count>::get(),
338  "CPI: Cycles Per Instruction"),
339  ADD_STAT(totalCpi, statistics::units::Rate<
340  statistics::units::Cycle, statistics::units::Count>::get(),
341  "CPI: Total CPI of All Threads"),
342  ADD_STAT(ipc, statistics::units::Rate<
343  statistics::units::Count, statistics::units::Cycle>::get(),
344  "IPC: Instructions Per Cycle"),
345  ADD_STAT(totalIpc, statistics::units::Rate<
346  statistics::units::Count, statistics::units::Cycle>::get(),
347  "IPC: Total IPC of All Threads"),
348  ADD_STAT(intRegfileReads, statistics::units::Count::get(),
349  "Number of integer regfile reads"),
350  ADD_STAT(intRegfileWrites, statistics::units::Count::get(),
351  "Number of integer regfile writes"),
352  ADD_STAT(fpRegfileReads, statistics::units::Count::get(),
353  "Number of floating regfile reads"),
354  ADD_STAT(fpRegfileWrites, statistics::units::Count::get(),
355  "Number of floating regfile writes"),
356  ADD_STAT(vecRegfileReads, statistics::units::Count::get(),
357  "number of vector regfile reads"),
358  ADD_STAT(vecRegfileWrites, statistics::units::Count::get(),
359  "number of vector regfile writes"),
360  ADD_STAT(vecPredRegfileReads, statistics::units::Count::get(),
361  "number of predicate regfile reads"),
362  ADD_STAT(vecPredRegfileWrites, statistics::units::Count::get(),
363  "number of predicate regfile writes"),
364  ADD_STAT(ccRegfileReads, statistics::units::Count::get(),
365  "number of cc regfile reads"),
366  ADD_STAT(ccRegfileWrites, statistics::units::Count::get(),
367  "number of cc regfile writes"),
368  ADD_STAT(miscRegfileReads, statistics::units::Count::get(),
369  "number of misc regfile reads"),
370  ADD_STAT(miscRegfileWrites, statistics::units::Count::get(),
371  "number of misc regfile writes")
372 {
373  // Register any of the O3CPU's stats here.
374  timesIdled
375  .prereq(timesIdled);
376 
377  idleCycles
378  .prereq(idleCycles);
379 
382 
383  // Number of Instructions simulated
384  // --------------------------------
385  // Should probably be in Base CPU but need templated
386  // MaxThreads so put in here instead
388  .init(cpu->numThreads)
390 
392  .init(cpu->numThreads)
394 
395  cpi
396  .precision(6);
397  cpi = cpu->baseStats.numCycles / committedInsts;
398 
399  totalCpi
400  .precision(6);
401  totalCpi = cpu->baseStats.numCycles / sum(committedInsts);
402 
403  ipc
404  .precision(6);
405  ipc = committedInsts / cpu->baseStats.numCycles;
406 
407  totalIpc
408  .precision(6);
409  totalIpc = sum(committedInsts) / cpu->baseStats.numCycles;
410 
413 
416 
419 
422 
425 
428 
431 
434 
437 
440 
443 
446 }
447 
448 void
450 {
451  DPRINTF(O3CPU, "\n\nO3CPU: Ticking main, O3CPU.\n");
452  assert(!switchedOut());
453  assert(drainState() != DrainState::Drained);
454 
455  ++baseStats.numCycles;
456  updateCycleCounters(BaseCPU::CPU_STATE_ON);
457 
458 // activity = false;
459 
460  //Tick each of the stages
461  fetch.tick();
462 
463  decode.tick();
464 
465  rename.tick();
466 
467  iew.tick();
468 
469  commit.tick();
470 
471  // Now advance the time buffers
472  timeBuffer.advance();
473 
474  fetchQueue.advance();
475  decodeQueue.advance();
476  renameQueue.advance();
477  iewQueue.advance();
478 
480 
481  if (removeInstsThisCycle) {
483  }
484 
485  if (!tickEvent.scheduled()) {
486  if (_status == SwitchedOut) {
487  DPRINTF(O3CPU, "Switched out!\n");
488  // increment stat
489  lastRunningCycle = curCycle();
490  } else if (!activityRec.active() || _status == Idle) {
491  DPRINTF(O3CPU, "Idle!\n");
492  lastRunningCycle = curCycle();
494  } else {
495  schedule(tickEvent, clockEdge(Cycles(1)));
496  DPRINTF(O3CPU, "Scheduling next tick!\n");
497  }
498  }
499 
500  if (!FullSystem)
502 
503  tryDrain();
504 }
505 
506 void
508 {
509  BaseCPU::init();
510 
511  for (ThreadID tid = 0; tid < numThreads; ++tid) {
512  // Set noSquashFromTC so that the CPU doesn't squash when initially
513  // setting up registers.
514  thread[tid]->noSquashFromTC = true;
515  }
516 
517  // Clear noSquashFromTC.
518  for (int tid = 0; tid < numThreads; ++tid)
519  thread[tid]->noSquashFromTC = false;
520 
522 }
523 
524 void
526 {
527  BaseCPU::startup();
528 
531  iew.startupStage();
534 }
535 
536 void
538 {
540  std::find(activeThreads.begin(), activeThreads.end(), tid);
541 
542  DPRINTF(O3CPU, "[tid:%i] Calling activate thread.\n", tid);
543  assert(!switchedOut());
544 
545  if (isActive == activeThreads.end()) {
546  DPRINTF(O3CPU, "[tid:%i] Adding to active threads list\n", tid);
547 
548  activeThreads.push_back(tid);
549  }
550 }
551 
552 void
554 {
555  // hardware transactional memory
556  // shouldn't deactivate thread in the middle of a transaction
557  assert(!commit.executingHtmTransaction(tid));
558 
559  //Remove From Active List, if Active
561  std::find(activeThreads.begin(), activeThreads.end(), tid);
562 
563  DPRINTF(O3CPU, "[tid:%i] Calling deactivate thread.\n", tid);
564  assert(!switchedOut());
565 
566  if (thread_it != activeThreads.end()) {
567  DPRINTF(O3CPU,"[tid:%i] Removing from active threads list\n",
568  tid);
569  activeThreads.erase(thread_it);
570  }
571 
572  fetch.deactivateThread(tid);
574 }
575 
576 Counter
578 {
579  Counter total(0);
580 
581  ThreadID size = thread.size();
582  for (ThreadID i = 0; i < size; i++)
583  total += thread[i]->numInst;
584 
585  return total;
586 }
587 
588 Counter
590 {
591  Counter total(0);
592 
593  ThreadID size = thread.size();
594  for (ThreadID i = 0; i < size; i++)
595  total += thread[i]->numOp;
596 
597  return total;
598 }
599 
600 void
602 {
603  assert(!switchedOut());
604 
605  // Needs to set each stage to running as well.
606  activateThread(tid);
607 
608  // We don't want to wake the CPU if it is drained. In that case,
609  // we just want to flag the thread as active and schedule the tick
610  // event from drainResume() instead.
611  if (drainState() == DrainState::Drained)
612  return;
613 
614  // If we are time 0 or if the last activation time is in the past,
615  // schedule the next tick and wake up the fetch unit
618 
619  // Be sure to signal that there's some activity so the CPU doesn't
620  // deschedule itself.
623 
624  Cycles cycles(curCycle() - lastRunningCycle);
625  // @todo: This is an oddity that is only here to match the stats
626  if (cycles != 0)
627  --cycles;
628  cpuStats.quiesceCycles += cycles;
629 
631 
632  _status = Running;
633 
634  BaseCPU::activateContext(tid);
635  }
636 }
637 
638 void
640 {
641  DPRINTF(O3CPU,"[tid:%i] Suspending Thread Context.\n", tid);
642  assert(!switchedOut());
643 
644  deactivateThread(tid);
645 
646  // If this was the last thread then unschedule the tick event.
647  if (activeThreads.size() == 0) {
649  lastRunningCycle = curCycle();
650  _status = Idle;
651  }
652 
653  DPRINTF(Quiesce, "Suspending Context\n");
654 
655  BaseCPU::suspendContext(tid);
656 }
657 
658 void
660 {
661  //For now, this is the same as deallocate
662  DPRINTF(O3CPU,"[tid:%i] Halt Context called. Deallocating\n", tid);
663  assert(!switchedOut());
664 
665  deactivateThread(tid);
666  removeThread(tid);
667 
668  // If this was the last thread then unschedule the tick event.
669  if (activeThreads.size() == 0) {
670  if (tickEvent.scheduled())
671  {
673  }
674  lastRunningCycle = curCycle();
675  _status = Idle;
676  }
677  updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
678 }
679 
680 void
682 {
683  DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
684  // Will change now that the PC and thread state is internal to the CPU
685  // and not in the ThreadContext.
686  gem5::ThreadContext *src_tc;
687  if (FullSystem)
688  src_tc = system->threads[tid];
689  else
690  src_tc = tcBase(tid);
691 
692  //Bind Int Regs to Rename Map
693  const auto &regClasses = isa[tid]->regClasses();
694 
695  for (auto type = (RegClassType)0; type <= CCRegClass;
696  type = (RegClassType)(type + 1)) {
697  for (RegIndex idx = 0; idx < regClasses.at(type).numRegs(); idx++) {
698  PhysRegIdPtr phys_reg = freeList.getReg(type);
699  renameMap[tid].setEntry(RegId(type, idx), phys_reg);
700  scoreboard.setReg(phys_reg);
701  }
702  }
703 
704  //Copy Thread Data Into RegFile
705  //copyFromTC(tid);
706 
707  //Set PC/NPC/NNPC
708  pcState(src_tc->pcState(), tid);
709 
711 
712  activateContext(tid);
713 
714  //Reset ROB/IQ/LSQ Entries
716 }
717 
718 void
720 {
721  DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
722 
723  // Copy Thread Data From RegFile
724  // If thread is suspended, it might be re-allocated
725  // copyToTC(tid);
726 
727 
728  // @todo: 2-27-2008: Fix how we free up rename mappings
729  // here to alleviate the case for double-freeing registers
730  // in SMT workloads.
731 
732  // clear all thread-specific states in each stage of the pipeline
733  // since this thread is going to be completely removed from the CPU
734  commit.clearStates(tid);
735  fetch.clearStates(tid);
736  decode.clearStates(tid);
737  rename.clearStates(tid);
738  iew.clearStates(tid);
739 
740  // Flush out any old data from the time buffers.
741  for (int i = 0; i < timeBuffer.getSize(); ++i) {
742  timeBuffer.advance();
743  fetchQueue.advance();
744  decodeQueue.advance();
745  renameQueue.advance();
746  iewQueue.advance();
747  }
748 
749  // at this step, all instructions in the pipeline should be already
750  // either committed successfully or squashed. All thread-specific
751  // queues in the pipeline must be empty.
752  assert(iew.instQueue.getCount(tid) == 0);
753  assert(iew.ldstQueue.getCount(tid) == 0);
754  assert(commit.rob->isEmpty(tid));
755 
756  // Reset ROB/IQ/LSQ Entries
757 
758  // Commented out for now. This should be possible to do by
759  // telling all the pipeline stages to drain first, and then
760  // checking until the drain completes. Once the pipeline is
761  // drained, call resetEntries(). - 10-09-06 ktlim
762 /*
763  if (activeThreads.size() >= 1) {
764  commit.rob->resetEntries();
765  iew.resetEntries();
766  }
767 */
768 }
769 
770 Fault
772 {
773  // Check if there are any outstanding interrupts
774  return interrupts[0]->getInterrupt();
775 }
776 
777 void
778 CPU::processInterrupts(const Fault &interrupt)
779 {
780  // Check for interrupts here. For now can copy the code that
781  // exists within isa_fullsys_traits.hh. Also assume that thread 0
782  // is the one that handles the interrupts.
783  // @todo: Possibly consolidate the interrupt checking code.
784  // @todo: Allow other threads to handle interrupts.
785 
786  assert(interrupt != NoFault);
787  interrupts[0]->updateIntrInfo();
788 
789  DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
790  trap(interrupt, 0, nullptr);
791 }
792 
793 void
794 CPU::trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
795 {
796  // Pass the thread's TC into the invoke method.
797  fault->invoke(threadContexts[tid], inst);
798 }
799 
800 void
802 {
803  thread[tid]->serialize(cp);
804 }
805 
806 void
808 {
809  thread[tid]->unserialize(cp);
810 }
811 
814 {
815  // Deschedule any power gating event (if any)
816  deschedulePowerGatingEvent();
817 
818  // If the CPU isn't doing anything, then return immediately.
819  if (switchedOut())
820  return DrainState::Drained;
821 
822  DPRINTF(Drain, "Draining...\n");
823 
824  // We only need to signal a drain to the commit stage as this
825  // initiates squashing controls the draining. Once the commit
826  // stage commits an instruction where it is safe to stop, it'll
827  // squash the rest of the instructions in the pipeline and force
828  // the fetch stage to stall. The pipeline will be drained once all
829  // in-flight instructions have retired.
830  commit.drain();
831 
832  // Wake the CPU and record activity so everything can drain out if
833  // the CPU was not able to immediately drain.
834  if (!isCpuDrained()) {
835  // If a thread is suspended, wake it up so it can be drained
836  for (auto t : threadContexts) {
837  if (t->status() == gem5::ThreadContext::Suspended){
838  DPRINTF(Drain, "Currently suspended so activate %i \n",
839  t->threadId());
840  t->activate();
841  // As the thread is now active, change the power state as well
842  activateContext(t->threadId());
843  }
844  }
845 
846  wakeCPU();
848 
849  DPRINTF(Drain, "CPU not drained\n");
850 
851  return DrainState::Draining;
852  } else {
853  DPRINTF(Drain, "CPU is already drained\n");
854  if (tickEvent.scheduled())
855  deschedule(tickEvent);
856 
857  // Flush out any old data from the time buffers. In
858  // particular, there might be some data in flight from the
859  // fetch stage that isn't visible in any of the CPU buffers we
860  // test in isCpuDrained().
861  for (int i = 0; i < timeBuffer.getSize(); ++i) {
862  timeBuffer.advance();
863  fetchQueue.advance();
864  decodeQueue.advance();
865  renameQueue.advance();
866  iewQueue.advance();
867  }
868 
870  return DrainState::Drained;
871  }
872 }
873 
874 bool
876 {
877  if (drainState() != DrainState::Draining || !isCpuDrained())
878  return false;
879 
880  if (tickEvent.scheduled())
881  deschedule(tickEvent);
882 
883  DPRINTF(Drain, "CPU done draining, processing drain event\n");
884  signalDrainDone();
885 
886  return true;
887 }
888 
889 void
891 {
892  assert(isCpuDrained());
898 }
899 
900 bool
902 {
903  bool drained(true);
904 
905  if (!instList.empty() || !removeList.empty()) {
906  DPRINTF(Drain, "Main CPU structures not drained.\n");
907  drained = false;
908  }
909 
910  if (!fetch.isDrained()) {
911  DPRINTF(Drain, "Fetch not drained.\n");
912  drained = false;
913  }
914 
915  if (!decode.isDrained()) {
916  DPRINTF(Drain, "Decode not drained.\n");
917  drained = false;
918  }
919 
920  if (!rename.isDrained()) {
921  DPRINTF(Drain, "Rename not drained.\n");
922  drained = false;
923  }
924 
925  if (!iew.isDrained()) {
926  DPRINTF(Drain, "IEW not drained.\n");
927  drained = false;
928  }
929 
930  if (!commit.isDrained()) {
931  DPRINTF(Drain, "Commit not drained.\n");
932  drained = false;
933  }
934 
935  return drained;
936 }
937 
939 
940 void
942 {
943  if (switchedOut())
944  return;
945 
946  DPRINTF(Drain, "Resuming...\n");
948 
949  fetch.drainResume();
951 
952  _status = Idle;
953  for (ThreadID i = 0; i < thread.size(); i++) {
955  DPRINTF(Drain, "Activating thread: %i\n", i);
956  activateThread(i);
957  _status = Running;
958  }
959  }
960 
961  assert(!tickEvent.scheduled());
962  if (_status == Running)
963  schedule(tickEvent, nextCycle());
964 
965  // Reschedule any power gating event (if any)
966  schedulePowerGatingEvent();
967 }
968 
969 void
971 {
972  DPRINTF(O3CPU, "Switching out\n");
973  BaseCPU::switchOut();
974 
975  activityRec.reset();
976 
978 
979  if (checker)
980  checker->switchOut();
981 }
982 
983 void
984 CPU::takeOverFrom(BaseCPU *oldCPU)
985 {
986  BaseCPU::takeOverFrom(oldCPU);
987 
991  iew.takeOverFrom();
993 
994  assert(!tickEvent.scheduled());
995 
996  auto *oldO3CPU = dynamic_cast<CPU *>(oldCPU);
997  if (oldO3CPU)
998  globalSeqNum = oldO3CPU->globalSeqNum;
999 
1000  lastRunningCycle = curCycle();
1001  _status = Idle;
1002 }
1003 
1004 void
1006 {
1007  if (!system->isTimingMode()) {
1008  fatal("The O3 CPU requires the memory system to be in "
1009  "'timing' mode.\n");
1010  }
1011 }
1012 
1013 RegVal
1014 CPU::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1015 {
1016  return isa[tid]->readMiscRegNoEffect(misc_reg);
1017 }
1018 
1019 RegVal
1020 CPU::readMiscReg(int misc_reg, ThreadID tid)
1021 {
1023  return isa[tid]->readMiscReg(misc_reg);
1024 }
1025 
1026 void
1028 {
1029  isa[tid]->setMiscRegNoEffect(misc_reg, val);
1030 }
1031 
1032 void
1033 CPU::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
1034 {
1036  isa[tid]->setMiscReg(misc_reg, val);
1037 }
1038 
1039 RegVal
1041 {
1042  switch (phys_reg->classValue()) {
1043  case IntRegClass:
1045  break;
1046  case FloatRegClass:
1048  break;
1049  case CCRegClass:
1051  break;
1052  case VecRegClass:
1053  case VecElemClass:
1055  break;
1056  case VecPredRegClass:
1058  break;
1059  default:
1060  break;
1061  }
1062  return regFile.getReg(phys_reg);
1063 }
1064 
1065 void
1066 CPU::getReg(PhysRegIdPtr phys_reg, void *val)
1067 {
1068  switch (phys_reg->classValue()) {
1069  case IntRegClass:
1071  break;
1072  case FloatRegClass:
1074  break;
1075  case CCRegClass:
1077  break;
1078  case VecRegClass:
1079  case VecElemClass:
1081  break;
1082  case VecPredRegClass:
1084  break;
1085  default:
1086  break;
1087  }
1088  regFile.getReg(phys_reg, val);
1089 }
1090 
1091 void *
1093 {
1094  switch (phys_reg->classValue()) {
1095  case VecRegClass:
1097  break;
1098  case VecPredRegClass:
1100  break;
1101  default:
1102  break;
1103  }
1104  return regFile.getWritableReg(phys_reg);
1105 }
1106 
1107 void
1109 {
1110  switch (phys_reg->classValue()) {
1111  case IntRegClass:
1113  break;
1114  case FloatRegClass:
1116  break;
1117  case CCRegClass:
1119  break;
1120  case VecRegClass:
1121  case VecElemClass:
1123  break;
1124  case VecPredRegClass:
1126  break;
1127  default:
1128  break;
1129  }
1130  regFile.setReg(phys_reg, val);
1131 }
1132 
1133 void
1134 CPU::setReg(PhysRegIdPtr phys_reg, const void *val)
1135 {
1136  switch (phys_reg->classValue()) {
1137  case IntRegClass:
1139  break;
1140  case FloatRegClass:
1142  break;
1143  case CCRegClass:
1145  break;
1146  case VecRegClass:
1147  case VecElemClass:
1149  break;
1150  case VecPredRegClass:
1152  break;
1153  default:
1154  break;
1155  }
1156  regFile.setReg(phys_reg, val);
1157 }
1158 
1159 RegVal
1161 {
1162  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
1163  return regFile.getReg(phys_reg);
1164 }
1165 
1166 void
1167 CPU::getArchReg(const RegId &reg, void *val, ThreadID tid)
1168 {
1169  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
1170  regFile.getReg(phys_reg, val);
1171 }
1172 
1173 void *
1175 {
1176  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
1177  return regFile.getWritableReg(phys_reg);
1178 }
1179 
1180 void
1182 {
1183  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
1184  regFile.setReg(phys_reg, val);
1185 }
1186 
1187 void
1188 CPU::setArchReg(const RegId &reg, const void *val, ThreadID tid)
1189 {
1190  PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
1191  regFile.setReg(phys_reg, val);
1192 }
1193 
1194 const PCStateBase &
1196 {
1197  return commit.pcState(tid);
1198 }
1199 
1200 void
1202 {
1203  commit.pcState(val, tid);
1204 }
1205 
1206 void
1208 {
1209  thread[tid]->noSquashFromTC = true;
1210  commit.generateTCEvent(tid);
1211 }
1212 
1215 {
1216  instList.push_back(inst);
1217 
1218  return --(instList.end());
1219 }
1220 
1221 void
1223 {
1224  // Keep an instruction count.
1225  if (!inst->isMicroop() || inst->isLastMicroop()) {
1226  thread[tid]->numInst++;
1227  thread[tid]->threadStats.numInsts++;
1228  cpuStats.committedInsts[tid]++;
1229 
1230  // Check for instruction-count-based events.
1231  thread[tid]->comInstEventQueue.serviceEvents(thread[tid]->numInst);
1232  }
1233  thread[tid]->numOp++;
1234  thread[tid]->threadStats.numOps++;
1235  cpuStats.committedOps[tid]++;
1236 
1237  probeInstCommit(inst->staticInst, inst->pcState().instAddr());
1238 }
1239 
1240 void
1242 {
1243  DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1244  "[sn:%lli]\n",
1245  inst->threadNumber, inst->pcState(), inst->seqNum);
1246 
1247  removeInstsThisCycle = true;
1248 
1249  // Remove the front instruction.
1250  removeList.push(inst->getInstListIt());
1251 }
1252 
1253 void
1255 {
1256  DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1257  " list.\n", tid);
1258 
1259  ListIt end_it;
1260 
1261  bool rob_empty = false;
1262 
1263  if (instList.empty()) {
1264  return;
1265  } else if (rob.isEmpty(tid)) {
1266  DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1267  end_it = instList.begin();
1268  rob_empty = true;
1269  } else {
1270  end_it = (rob.readTailInst(tid))->getInstListIt();
1271  DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1272  }
1273 
1274  removeInstsThisCycle = true;
1275 
1276  ListIt inst_it = instList.end();
1277 
1278  inst_it--;
1279 
1280  // Walk through the instruction list, removing any instructions
1281  // that were inserted after the given instruction iterator, end_it.
1282  while (inst_it != end_it) {
1283  assert(!instList.empty());
1284 
1285  squashInstIt(inst_it, tid);
1286 
1287  inst_it--;
1288  }
1289 
1290  // If the ROB was empty, then we actually need to remove the first
1291  // instruction as well.
1292  if (rob_empty) {
1293  squashInstIt(inst_it, tid);
1294  }
1295 }
1296 
1297 void
1299 {
1300  assert(!instList.empty());
1301 
1302  removeInstsThisCycle = true;
1303 
1304  ListIt inst_iter = instList.end();
1305 
1306  inst_iter--;
1307 
1308  DPRINTF(O3CPU, "Deleting instructions from instruction "
1309  "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1310  tid, seq_num, (*inst_iter)->seqNum);
1311 
1312  while ((*inst_iter)->seqNum > seq_num) {
1313 
1314  bool break_loop = (inst_iter == instList.begin());
1315 
1316  squashInstIt(inst_iter, tid);
1317 
1318  inst_iter--;
1319 
1320  if (break_loop)
1321  break;
1322  }
1323 }
1324 
1325 void
1326 CPU::squashInstIt(const ListIt &instIt, ThreadID tid)
1327 {
1328  if ((*instIt)->threadNumber == tid) {
1329  DPRINTF(O3CPU, "Squashing instruction, "
1330  "[tid:%i] [sn:%lli] PC %s\n",
1331  (*instIt)->threadNumber,
1332  (*instIt)->seqNum,
1333  (*instIt)->pcState());
1334 
1335  // Mark it as squashed.
1336  (*instIt)->setSquashed();
1337 
1338  // @todo: Formulate a consistent method for deleting
1339  // instructions from the instruction list
1340  // Remove the instruction from the list.
1341  removeList.push(instIt);
1342  }
1343 }
1344 
1345 void
1347 {
1348  while (!removeList.empty()) {
1349  DPRINTF(O3CPU, "Removing instruction, "
1350  "[tid:%i] [sn:%lli] PC %s\n",
1351  (*removeList.front())->threadNumber,
1352  (*removeList.front())->seqNum,
1353  (*removeList.front())->pcState());
1354 
1355  instList.erase(removeList.front());
1356 
1357  removeList.pop();
1358  }
1359 
1360  removeInstsThisCycle = false;
1361 }
1362 /*
1363 void
1364 CPU::removeAllInsts()
1365 {
1366  instList.clear();
1367 }
1368 */
1369 void
1371 {
1372  int num = 0;
1373 
1374  ListIt inst_list_it = instList.begin();
1375 
1376  cprintf("Dumping Instruction List\n");
1377 
1378  while (inst_list_it != instList.end()) {
1379  cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1380  "Squashed:%i\n\n",
1381  num, (*inst_list_it)->pcState().instAddr(),
1382  (*inst_list_it)->threadNumber,
1383  (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1384  (*inst_list_it)->isSquashed());
1385  inst_list_it++;
1386  ++num;
1387  }
1388 }
1389 /*
1390 void
1391 CPU::wakeDependents(const DynInstPtr &inst)
1392 {
1393  iew.wakeDependents(inst);
1394 }
1395 */
1396 void
1398 {
1399  if (activityRec.active() || tickEvent.scheduled()) {
1400  DPRINTF(Activity, "CPU already running.\n");
1401  return;
1402  }
1403 
1404  DPRINTF(Activity, "Waking up CPU\n");
1405 
1406  Cycles cycles(curCycle() - lastRunningCycle);
1407  // @todo: This is an oddity that is only here to match the stats
1408  if (cycles > 1) {
1409  --cycles;
1410  cpuStats.idleCycles += cycles;
1411  baseStats.numCycles += cycles;
1412  }
1413 
1414  schedule(tickEvent, clockEdge());
1415 }
1416 
1417 void
1419 {
1421  return;
1422 
1423  wakeCPU();
1424 
1425  DPRINTF(Quiesce, "Suspended Processor woken\n");
1426  threadContexts[tid]->activate();
1427 }
1428 
1429 ThreadID
1431 {
1432  for (ThreadID tid = 0; tid < numThreads; tid++) {
1433  if (!tids[tid]) {
1434  tids[tid] = true;
1435  return tid;
1436  }
1437  }
1438 
1439  return InvalidThreadID;
1440 }
1441 
1442 void
1444 {
1445  if (activeThreads.size() > 1) {
1446  //DEFAULT TO ROUND ROBIN SCHEME
1447  //e.g. Move highest priority to end of thread list
1448  std::list<ThreadID>::iterator list_begin = activeThreads.begin();
1449 
1450  unsigned high_thread = *list_begin;
1451 
1452  activeThreads.erase(list_begin);
1453 
1454  activeThreads.push_back(high_thread);
1455  }
1456 }
1457 
1458 void
1460 {
1461  DPRINTF(O3CPU, "Thread %d is inserted to exitingThreads list\n", tid);
1462 
1463  // the thread trying to exit can't be already halted
1464  assert(tcBase(tid)->status() != gem5::ThreadContext::Halted);
1465 
1466  // make sure the thread has not been added to the list yet
1467  assert(exitingThreads.count(tid) == 0);
1468 
1469  // add the thread to exitingThreads list to mark that this thread is
1470  // trying to exit. The boolean value in the pair denotes if a thread is
1471  // ready to exit. The thread is not ready to exit until the corresponding
1472  // exit trap event is processed in the future. Until then, it'll be still
1473  // an active thread that is trying to exit.
1474  exitingThreads.emplace(std::make_pair(tid, false));
1475 }
1476 
1477 bool
1479 {
1480  return exitingThreads.count(tid) == 1;
1481 }
1482 
1483 void
1485 {
1486  assert(exitingThreads.count(tid) == 1);
1487 
1488  // exit trap event has been processed. Now, the thread is ready to exit
1489  // and be removed from the CPU.
1490  exitingThreads[tid] = true;
1491 
1492  // we schedule a threadExitEvent in the next cycle to properly clean
1493  // up the thread's states in the pipeline. threadExitEvent has lower
1494  // priority than tickEvent, so the cleanup will happen at the very end
1495  // of the next cycle after all pipeline stages complete their operations.
1496  // We want all stages to complete squashing instructions before doing
1497  // the cleanup.
1498  if (!threadExitEvent.scheduled()) {
1499  schedule(threadExitEvent, nextCycle());
1500  }
1501 }
1502 
1503 void
1505 {
1506  // there must be at least one thread trying to exit
1507  assert(exitingThreads.size() > 0);
1508 
1509  // terminate all threads that are ready to exit
1510  auto it = exitingThreads.begin();
1511  while (it != exitingThreads.end()) {
1512  ThreadID thread_id = it->first;
1513  bool readyToExit = it->second;
1514 
1515  if (readyToExit) {
1516  DPRINTF(O3CPU, "Exiting thread %d\n", thread_id);
1517  haltContext(thread_id);
1519  it = exitingThreads.erase(it);
1520  } else {
1521  it++;
1522  }
1523  }
1524 }
1525 
1526 void
1527 CPU::htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
1528  HtmFailureFaultCause cause)
1529 {
1530  const Addr addr = 0x0ul;
1531  const int size = 8;
1532  const Request::Flags flags =
1534 
1535  // O3-specific actions
1538 
1539  // notify l1 d-cache (ruby) that core has aborted transaction
1540  RequestPtr req =
1541  std::make_shared<Request>(addr, size, flags, _dataRequestorId);
1542 
1543  req->taskId(taskId());
1544  req->setContext(thread[tid]->contextId());
1545  req->setHtmAbortCause(cause);
1546 
1547  assert(req->isHTMAbort());
1548 
1549  PacketPtr abort_pkt = Packet::createRead(req);
1550  uint8_t *memData = new uint8_t[8];
1551  assert(memData);
1552  abort_pkt->dataStatic(memData);
1553  abort_pkt->setHtmTransactional(htm_uid);
1554 
1555  // TODO include correct error handling here
1556  if (!iew.ldstQueue.getDataPort().sendTimingReq(abort_pkt)) {
1557  panic("HTM abort signal was not sent to the memory subsystem.");
1558  }
1559 }
1560 
1561 } // namespace o3
1562 } // namespace gem5
gem5::o3::Rename::isDrained
bool isDrained() const
Has the stage drained?
Definition: rename.cc:305
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::o3::CPU::addThreadToExitingList
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
Definition: cpu.cc:1459
gem5::o3::Commit::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: commit.cc:400
gem5::o3::CPU::dumpInsts
void dumpInsts()
Debug function to print all instructions on the list.
Definition: cpu.cc:1370
gem5::o3::CPU::getWritableArchReg
void * getWritableArchReg(const RegId &reg, ThreadID tid)
Definition: cpu.cc:1174
gem5::o3::CPU::ppDataAccessComplete
ProbePointArg< std::pair< DynInstPtr, PacketPtr > > * ppDataAccessComplete
Definition: cpu.hh:175
gem5::o3::CPU::isCpuDrained
bool isCpuDrained() const
Check if a system is in a drained state.
Definition: cpu.cc:901
gem5::o3::CPU::tids
std::vector< ThreadID > tids
Available thread ids in the cpu.
Definition: cpu.hh:546
gem5::o3::CPU::CPUStats::miscRegfileWrites
statistics::Scalar miscRegfileWrites
Definition: cpu.hh:616
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:109
gem5::RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:495
gem5::o3::CPU::removeList
std::queue< ListIt > removeList
List of all the instructions that will be removed at the end of this cycle.
Definition: cpu.hh:387
gem5::o3::Rename::tick
void tick()
Ticks rename, which processes all input signals and attempts to rename as many instructions as possib...
Definition: rename.cc:389
gem5::o3::Commit::regProbePoints
void regProbePoints()
Registers probes.
Definition: commit.cc:139
gem5::o3::CPU::getReg
RegVal getReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1040
gem5::o3::Rename::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: rename.cc:325
gem5::o3::CPU::CPUStats::fpRegfileWrites
statistics::Scalar fpRegfileWrites
Definition: cpu.hh:604
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::CPU::removeInstsThisCycle
bool removeInstsThisCycle
Records if instructions need to be removed this cycle due to being retired or squashed.
Definition: cpu.hh:399
gem5::o3::CPU::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: cpu.hh:97
gem5::o3::CPU::cpuStats
gem5::o3::CPU::CPUStats cpuStats
gem5::cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:155
gem5::o3::CPU::globalSeqNum
InstSeqNum globalSeqNum
The global sequence number counter.
Definition: cpu.hh:519
gem5::o3::CPU::removeInstsUntil
void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
Remove all instructions younger than the given sequence number.
Definition: cpu.cc:1298
gem5::o3::ROB::readTailInst
DynInstPtr readTailInst(ThreadID tid)
Returns pointer to the tail instruction within the ROB.
Definition: rob.cc:516
system.hh
gem5::o3::Commit::drain
void drain()
Initializes the draining of commit.
Definition: commit.cc:348
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::o3::CPU::regFile
PhysRegFile regFile
The register file.
Definition: cpu.hh:418
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::o3::LSQ::getCount
int getCount()
Returns the number of instructions in all of the queues.
Definition: lsq.cc:473
gem5::o3::CPU::decode
Decode decode
The decode stage.
Definition: cpu.hh:406
gem5::o3::CPU::CPUStats::ccRegfileWrites
statistics::Scalar ccRegfileWrites
Definition: cpu.hh:613
gem5::o3::CPU::activeThreads
std::list< ThreadID > activeThreads
Active Threads List.
Definition: cpu.hh:433
gem5::o3::Commit::setThreads
void setThreads(std::vector< ThreadState * > &threads)
Sets the list of threads.
Definition: commit.cc:248
gem5::o3::CPU::freeList
UnifiedFreeList freeList
The free list.
Definition: cpu.hh:421
gem5::o3::CPU::processInterrupts
void processInterrupts(const Fault &interrupt)
Processes any an interrupt fault.
Definition: cpu.cc:778
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::Request::HTM_ABORT
@ HTM_ABORT
The request aborts a HTM transaction.
Definition: request.hh:216
gem5::o3::Commit::pcState
const PCStateBase & pcState(ThreadID tid)
Reads the PC of a specific thread.
Definition: commit.hh:309
gem5::Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:117
gem5::o3::Decode::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: decode.cc:98
gem5::o3::PhysRegFile::getWritableReg
void * getWritableReg(PhysRegIdPtr phys_reg)
Definition: regfile.hh:232
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::o3::Fetch::drainStall
void drainStall(ThreadID tid)
Stall the fetch stage after reaching a safe drain point.
Definition: fetch.cc:458
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::o3::CPU::CPUStats::quiesceCycles
statistics::Scalar quiesceCycles
Stat for total number of cycles the CPU spends descheduled due to a quiesce operation or waiting for ...
Definition: cpu.hh:584
gem5::o3::CPU::getInterrupts
Fault getInterrupts()
Returns the Fault for any valid interrupt.
Definition: cpu.cc:771
gem5::o3::CPU::squashInstIt
void squashInstIt(const ListIt &instIt, ThreadID tid)
Removes the instruction pointed to by the iterator.
Definition: cpu.cc:1326
gem5::o3::CPU::htmSendAbortSignal
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: cpu.cc:1527
gem5::o3::Fetch::wakeFromQuiesce
void wakeFromQuiesce()
Tells fetch to wake up from a quiesce instruction.
Definition: fetch.cc:467
cur_tick.hh
gem5::o3::CPU::setReg
void setReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1108
gem5::o3::IEW::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: iew.cc:392
gem5::o3::CPU::CPUStats::miscRegfileReads
statistics::Scalar miscRegfileReads
Definition: cpu.hh:615
gem5::o3::Commit::startupStage
void startupStage()
Initializes stage by sending back the number of free entries.
Definition: commit.cc:314
gem5::o3::CPU::CPUStats::intRegfileReads
statistics::Scalar intRegfileReads
Definition: cpu.hh:600
gem5::o3::IEW::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: iew.cc:293
gem5::o3::CPU::_status
Status _status
Overall CPU status.
Definition: cpu.hh:115
gem5::Packet::setHtmTransactional
void setHtmTransactional(uint64_t val)
Stipulates that this packet/request originates in the CPU executing in transactional mode,...
Definition: packet.cc:512
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::o3::CPU::timeBuffer
TimeBuffer< TimeStruct > timeBuffer
The main time buffer to do backwards communication.
Definition: cpu.hh:463
gem5::ThreadContext::setStatus
virtual void setStatus(Status new_status)=0
gem5::ActivityRecorder::advance
void advance()
Advances the activity buffer, decrementing the activityCount if active communication just left the ti...
Definition: activity.cc:71
gem5::o3::PhysRegFile::setReg
void setReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: regfile.hh:248
gem5::o3::CPU::removeThread
void removeThread(ThreadID tid)
Remove all of a thread's context from CPU.
Definition: cpu.cc:719
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::o3::CPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1033
dyn_inst.hh
gem5::o3::CPU::CPUStats::totalIpc
statistics::Formula totalIpc
Stat for the total IPC.
Definition: cpu.hh:597
gem5::o3::CPU::renameMap
UnifiedRenameMap renameMap[MaxThreads]
The rename map.
Definition: cpu.hh:424
gem5::o3::Fetch::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: fetch.cc:298
gem5::o3::CPU::instList
std::list< DynInstPtr > instList
List of all the instructions in flight.
Definition: cpu.hh:382
gem5::o3::Fetch::isDrained
bool isDrained() const
Has the stage drained?
Definition: fetch.cc:420
gem5::o3::CPU::verifyMemoryMode
void verifyMemoryMode() const override
Definition: cpu.cc:1005
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::o3::CPU::deactivateThread
void deactivateThread(ThreadID tid)
Remove Thread from Active Threads List.
Definition: cpu.cc:553
gem5::o3::CPU::CPUStats::intRegfileWrites
statistics::Scalar intRegfileWrites
Definition: cpu.hh:601
gem5::o3::CPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Definition: cpu.cc:807
gem5::EventBase::CPU_Exit_Pri
static const Priority CPU_Exit_Pri
If we want to exit a thread in a CPU, it comes after CPU_Tick_Pri.
Definition: eventq.hh:211
gem5::o3::CPU::CPUStats::cpi
statistics::Formula cpi
Stat for the CPI per thread.
Definition: cpu.hh:591
gem5::o3::CPU::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: cpu.cc:890
gem5::o3::CPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: cpu.cc:801
gem5::o3::CPU::cleanUpRemovedInsts
void cleanUpRemovedInsts()
Cleans up all instructions on the remove list.
Definition: cpu.cc:1346
gem5::o3::Commit::deactivateThread
void deactivateThread(ThreadID tid)
Deschedules a thread from scheduling.
Definition: commit.cc:415
gem5::o3::ROB::resetEntries
void resetEntries()
Re-adjust ROB partitioning.
Definition: rob.cc:148
gem5::o3::CPU::iewQueue
TimeBuffer< IEWStruct > iewQueue
The IEW stage's instruction queue.
Definition: cpu.hh:475
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::o3::CPU::ppInstAccessComplete
ProbePointArg< PacketPtr > * ppInstAccessComplete
Definition: cpu.hh:174
gem5::o3::IEW::startupStage
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
Definition: iew.cc:270
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:312
gem5::RefCountingPtr< StaticInst >
gem5::o3::LSQ::resetHtmStartsStops
void resetHtmStartsStops(ThreadID tid)
Definition: lsq.cc:361
gem5::o3::CPU::checker
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
Definition: cpu.hh:525
gem5::o3::CPU::unscheduleTickEvent
void unscheduleTickEvent()
Unschedule tick event, regardless of its current state.
Definition: cpu.hh:137
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::CPU::totalInsts
Counter totalInsts() const override
Count the Total Instructions Committed in the CPU.
Definition: cpu.cc:577
gem5::o3::Fetch::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: fetch.cc:403
gem5::PhysRegIdPtr
PhysRegId * PhysRegIdPtr
Definition: reg_class.hh:340
gem5::o3::CPU::CPUStats::committedInsts
statistics::Vector committedInsts
Stat for the number of committed instructions per thread.
Definition: cpu.hh:586
gem5::o3::CPU::CPUStats::idleCycles
statistics::Scalar idleCycles
Stat for total number of cycles the CPU spends descheduled.
Definition: cpu.hh:581
gem5::o3::IEW::instQueue
InstructionQueue instQueue
Instruction queue.
Definition: iew.hh:355
gem5::o3::CPU::decodeQueue
TimeBuffer< DecodeStruct > decodeQueue
The decode stage's instruction queue.
Definition: cpu.hh:469
gem5::Packet::dataStatic
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
Definition: packet.hh:1147
gem5::o3::Fetch::drainResume
void drainResume()
Resume after a drain.
Definition: fetch.cc:394
gem5::o3::CPU::CPUStats::totalCpi
statistics::Formula totalCpi
Stat for the total CPI.
Definition: cpu.hh:593
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::o3::Rename::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: rename.cc:227
gem5::Flags< FlagsType >
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::o3::Commit::generateTCEvent
void generateTCEvent(ThreadID tid)
Records that commit needs to initiate a squash due to an external state update through the TC.
Definition: commit.cc:524
gem5::o3::Decode::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: decode.hh:132
gem5::o3::Decode::tick
void tick()
Ticks decode, processing all input signals and decoding as many instructions as possible.
Definition: decode.cc:544
gem5::o3::CPU::tryDrain
bool tryDrain()
Check if the pipeline has drained and signal drain done.
Definition: cpu.cc:875
gem5::o3::CPU::wakeup
virtual void wakeup(ThreadID tid) override
Definition: cpu.cc:1418
gem5::o3::UnifiedFreeList::getReg
PhysRegIdPtr getReg(RegClassType type)
Gets a free register of type type.
Definition: free_list.hh:162
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::o3::CPU::insertThread
void insertThread(ThreadID tid)
Setup CPU to insert a thread's context.
Definition: cpu.cc:681
gem5::o3::IEW::isDrained
bool isDrained() const
Has the stage drained?
Definition: iew.cc:355
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::o3::CPU::CPUStats::vecPredRegfileReads
statistics::Scalar vecPredRegfileReads
Definition: cpu.hh:609
gem5::VegaISA::t
Bitfield< 51 > t
Definition: pagetable.hh:56
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::o3::CPU::scheduleTickEvent
void scheduleTickEvent(Cycles delay)
Schedule tick event, regardless of its current state.
Definition: cpu.hh:127
gem5::o3::CPU::totalOps
Counter totalOps() const override
Count the Total Ops (including micro ops) committed in the CPU.
Definition: cpu.cc:589
gem5::o3::CPU::suspendContext
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
Definition: cpu.cc:639
gem5::o3::Commit::isDrained
bool isDrained() const
Has the stage drained?
Definition: commit.cc:373
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::Commit::rob
ROB * rob
ROB interface.
Definition: commit.hh:342
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::o3::Scoreboard::setReg
void setReg(PhysRegIdPtr phys_reg)
Sets the register as ready.
Definition: scoreboard.hh:97
gem5::o3::CPU::fetch
Fetch fetch
The fetch stage.
Definition: cpu.hh:403
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::o3::CPU::scheduleThreadExitEvent
void scheduleThreadExitEvent(ThreadID tid)
If a thread is trying to exit and its corresponding trap event has been completed,...
Definition: cpu.cc:1484
gem5::o3::CPU::pcState
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1201
gem5::o3::PhysRegFile::getReg
RegVal getReg(PhysRegIdPtr phys_reg) const
Definition: regfile.hh:165
gem5::X86ISA::type
type
Definition: misc.hh:727
cpu.hh
gem5::o3::Decode::isDrained
bool isDrained() const
Has the stage drained?
Definition: decode.cc:207
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::o3::CPU::squashFromTC
void squashFromTC(ThreadID tid)
Initiates a squash of all in-flight instructions for a given thread.
Definition: cpu.cc:1207
gem5::o3::CPU::CPUStats::vecPredRegfileWrites
statistics::Scalar vecPredRegfileWrites
Definition: cpu.hh:610
process.hh
gem5::o3::CPU::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const
Register accessors.
Definition: cpu.cc:1014
gem5::o3::Commit::resetHtmStartsStops
void resetHtmStartsStops(ThreadID)
Definition: commit.cc:435
gem5::o3::CPU::tcBase
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
Definition: cpu.hh:513
gem5::o3::CPU::activateThread
void activateThread(ThreadID tid)
Add Thread to Active Threads List.
Definition: cpu.cc:537
activity.hh
gem5::o3::CPU::thread
std::vector< ThreadState * > thread
Pointers to all of the threads in the CPU.
Definition: cpu.hh:531
gem5::o3::Fetch::deactivateThread
void deactivateThread(ThreadID tid)
For priority-based fetch policies, need to keep update priorityList.
Definition: fetch.cc:500
gem5::o3::Commit::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: commit.cc:334
gem5::o3::CPU::getWritableReg
void * getWritableReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1092
gem5::o3::CPU::CPUStats::ccRegfileReads
statistics::Scalar ccRegfileReads
Definition: cpu.hh:612
gem5::o3::CPU::CPUStats::timesIdled
statistics::Scalar timesIdled
Stat for total number of times the CPU is descheduled.
Definition: cpu.hh:579
gem5::InvalidThreadID
const ThreadID InvalidThreadID
Definition: types.hh:236
gem5::o3::CPU::drain
DrainState drain() override
Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses.
Definition: cpu.cc:813
gem5::o3::CPU::wakeCPU
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
Definition: cpu.cc:1397
gem5::o3::CPU::tickEvent
EventFunctionWrapper tickEvent
The tick event used for scheduling CPU ticks.
Definition: cpu.hh:120
gem5::o3::CPU::switchOut
void switchOut() override
Switches out this CPU.
Definition: cpu.cc:970
flags
uint8_t flags
Definition: helpers.cc:66
gem5::o3::CPU::CPU
CPU(const BaseO3CPUParams &params)
Constructs a CPU with the given parameters.
Definition: cpu.cc:73
gem5::o3::CPU::Idle
@ Idle
Definition: cpu.hh:105
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::System::isTimingMode
bool isTimingMode() const
Is the system in timing mode?
Definition: system.hh:274
gem5::o3::CPU::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
Definition: cpu.cc:1027
gem5::o3::CPU::renameQueue
TimeBuffer< RenameStruct > renameQueue
The rename stage's instruction queue.
Definition: cpu.hh:472
std::pair
STL pair class.
Definition: stl.hh:58
gem5::o3::CPU::rob
ROB rob
The re-order buffer.
Definition: cpu.hh:430
gem5::statistics::DataWrap::precision
Derived & precision(int _precision)
Set the precision and marks this stat to print at the end of simulation.
Definition: statistics.hh:346
gem5::o3::IEW::tick
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle.
Definition: iew.cc:1432
gem5::o3::Fetch::tick
void tick()
Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible.
Definition: fetch.cc:839
gem5::o3::CPU::Running
@ Running
Definition: cpu.hh:104
gem5::o3::CPU::CPUStats::vecRegfileWrites
statistics::Scalar vecRegfileWrites
Definition: cpu.hh:607
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::CPU::CPUStats::vecRegfileReads
statistics::Scalar vecRegfileReads
Definition: cpu.hh:606
gem5::o3::CPU::CPUStats::committedOps
statistics::Vector committedOps
Stat for the number of committed ops (including micro ops) per thread.
Definition: cpu.hh:589
name
const std::string & name()
Definition: trace.cc:49
full_system.hh
gem5::ActivityRecorder::activity
void activity()
Records that there is activity this cycle.
Definition: activity.cc:55
gem5::o3::Fetch::startupStage
void startupStage()
Initialize stage.
Definition: fetch.cc:287
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::o3::CPU::regProbePoints
void regProbePoints() override
Register probe points.
Definition: cpu.cc:305
gem5::o3::CPU::system
System * system
Pointer to the system.
Definition: cpu.hh:528
gem5::Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:135
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::ActivityRecorder::reset
void reset()
Clears the time buffer and the activity count.
Definition: activity.cc:125
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::o3::CPU::lastRunningCycle
Cycles lastRunningCycle
The cycle that the CPU was last running, used for statistics.
Definition: cpu.hh:537
gem5::o3::CPU::updateThreadPriority
void updateThreadPriority()
Update The Order In Which We Process Threads.
Definition: cpu.cc:1443
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
stat_control.hh
warn_if
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:273
gem5::o3::CPU::CPUStats::ipc
statistics::Formula ipc
Stat for the IPC per thread.
Definition: cpu.hh:595
gem5::o3::CPU::rename
Rename rename
The dispatch stage.
Definition: cpu.hh:409
gem5::o3::CPU::fetchQueue
TimeBuffer< FetchStruct > fetchQueue
The fetch stage's instruction queue.
Definition: cpu.hh:466
simple_thread.hh
gem5::o3::CPU::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU) override
Takes over from another CPU.
Definition: cpu.cc:984
gem5::o3::CPU::iew
IEW iew
The issue/execute/writeback stages.
Definition: cpu.hh:412
gem5::o3::CPU::removeInstsNotInROB
void removeInstsNotInROB(ThreadID tid)
Remove all instructions that are not currently in the ROB.
Definition: cpu.cc:1254
gem5::o3::IEW::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: iew.cc:383
gem5::o3::CPU::exitThreads
void exitThreads()
Terminate all threads that are ready to exit.
Definition: cpu.cc:1504
gem5::o3::CPU::lastActivatedCycle
Tick lastActivatedCycle
The cycle that the CPU was last activated by a new thread.
Definition: cpu.hh:540
gem5::o3::Commit::drainResume
void drainResume()
Resumes execution after draining.
Definition: commit.cc:351
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:56
gem5::o3::Commit::executingHtmTransaction
bool executingHtmTransaction(ThreadID) const
Is the CPU currently processing a HTM transaction?
Definition: commit.cc:426
gem5::statistics::DataWrap::prereq
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Definition: statistics.hh:372
gem5::o3::CPU::commitDrained
void commitDrained(ThreadID tid)
Commit has reached a safe point to drain a thread.
Definition: cpu.cc:938
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::pseudo_inst::quiesceCycles
void quiesceCycles(ThreadContext *tc, uint64_t cycles)
Definition: pseudo_inst.cc:139
gem5::o3::Fetch::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: fetch.cc:450
gem5::o3::CPU::commitRenameMap
UnifiedRenameMap commitRenameMap[MaxThreads]
The commit rename map.
Definition: cpu.hh:427
gem5::o3::CPU::trap
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
Definition: cpu.cc:794
gem5::o3::CPU::drainResume
void drainResume() override
Resumes execution after a drain.
Definition: cpu.cc:941
gem5::o3::CPU::getFreeTid
ThreadID getFreeTid()
Gets a free thread id.
Definition: cpu.cc:1430
gem5::o3::CPU::addInst
ListIt addInst(const DynInstPtr &inst)
Function to add instruction onto the head of the list of the instructions.
Definition: cpu.cc:1214
gem5::o3::CPU::setArchReg
void setArchReg(const RegId &reg, RegVal val, ThreadID tid)
Definition: cpu.cc:1181
gem5::o3::ROB::isEmpty
bool isEmpty() const
Returns if the ROB is empty.
Definition: rob.hh:195
gem5::o3::CPU::isThreadExiting
bool isThreadExiting(ThreadID tid) const
Is the thread trying to exit?
Definition: cpu.cc:1478
gem5::o3::Decode::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: decode.cc:198
gem5::o3::CPU::threadExitEvent
EventFunctionWrapper threadExitEvent
The exit event used for terminating all ready-to-exit threads.
Definition: cpu.hh:123
gem5::o3::UnifiedRenameMap::lookup
PhysRegIdPtr lookup(const RegId &arch_reg) const
Look up the physical register mapped to an architectural register.
Definition: rename_map.hh:225
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::CPU::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
Definition: cpu.cc:1020
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:245
gem5::o3::Rename::startupStage
void startupStage()
Initializes variables for the stage.
Definition: rename.cc:221
thread_context.hh
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::statistics::init
const FlagsType init
This Stat is Initialized.
Definition: info.hh:56
gem5::o3::CPU::SwitchedOut
@ SwitchedOut
Definition: cpu.hh:108
gem5::o3::CPU::exitingThreads
std::unordered_map< ThreadID, bool > exitingThreads
This is a list of threads that are trying to exit.
Definition: cpu.hh:440
gem5::o3::CPU::CPUStats::fpRegfileReads
statistics::Scalar fpRegfileReads
Definition: cpu.hh:603
gem5::o3::Fetch::regProbePoints
void regProbePoints()
Registers probes.
Definition: fetch.cc:152
gem5::RiscvISA::sum
Bitfield< 18 > sum
Definition: misc.hh:555
gem5::o3::LSQ::getDataPort
RequestPort & getDataPort()
Definition: lsq.hh:892
gem5::ActivityRecorder::active
bool active()
Returns if the CPU should be active.
Definition: activity.hh:91
gem5::o3::Commit::tick
void tick()
Ticks the commit stage, which tries to commit instructions.
Definition: commit.cc:629
gem5::o3::Rename::regProbePoints
void regProbePoints()
Registers probes.
Definition: rename.cc:179
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:358
gem5::o3::CPU::scoreboard
Scoreboard scoreboard
Integer Register Scoreboard.
Definition: cpu.hh:443
gem5::DrainState::Running
@ Running
Running normally.
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::o3::IEW::ldstQueue
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:358
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::o3::CPU::commit
Commit commit
The commit stage.
Definition: cpu.hh:415
cpu.hh
std::list
STL list class.
Definition: stl.hh:51
gem5::o3::CPU::haltContext
void haltContext(ThreadID tid) override
Remove Thread from Active Threads List && Remove Thread Context from CPU.
Definition: cpu.cc:659
gem5::EventBase::CPU_Tick_Pri
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:204
gem5::o3::CPU::activityRec
ActivityRecorder activityRec
The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and...
Definition: cpu.hh:482
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::o3::Decode::startupStage
void startupStage()
Definition: decode.cc:92
gem5::Packet::createRead
static PacketPtr createRead(const RequestPtr &req)
Constructor-like methods that return Packets based on Request objects.
Definition: packet.hh:1020
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
thread_context.hh
limits.hh
gem5::o3::CPU::activateContext
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
Definition: cpu.cc:601
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1040
gem5::o3::Rename::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: rename.cc:319
gem5::o3::CPU::tick
void tick()
Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should d...
Definition: cpu.cc:449
gem5::o3::CPU::getArchReg
RegVal getArchReg(const RegId &reg, ThreadID tid)
Architectural register accessors.
Definition: cpu.cc:1160
gem5::PhysRegId::classValue
constexpr RegClassType classValue() const
Class accessor.
Definition: reg_class.hh:191
gem5::o3::CPU::startup
void startup() override
Definition: cpu.cc:525
gem5::o3::CPU::CPUStats::CPUStats
CPUStats(CPU *cpu)
Definition: cpu.cc:321
thread_context.hh
gem5::o3::CPU::isa
std::vector< TheISA::ISA * > isa
Definition: cpu.hh:445
gem5::o3::Commit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: commit.cc:358
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::o3::CPU::instDone
void instDone(ThreadID tid, const DynInstPtr &inst)
Function to tell the CPU that an instruction has completed.
Definition: cpu.cc:1222
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
gem5::o3::CPU::init
void init() override
Initialize the CPU.
Definition: cpu.cc:507
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::o3::UnifiedRenameMap::setEntry
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
Definition: rename_map.hh:247
gem5::o3::CPU::removeFrontInst
void removeFrontInst(const DynInstPtr &inst)
Remove an instruction from the front end of the list.
Definition: cpu.cc:1241
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::o3::IEW::regProbePoints
void regProbePoints()
Registers probes.
Definition: iew.cc:125
gem5::o3::InstructionQueue::getCount
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
Definition: inst_queue.hh:275

Generated on Thu Jul 28 2022 13:32:22 for gem5 by doxygen 1.8.17