53 #include "debug/Activity.hh"
54 #include "debug/Drain.hh"
55 #include "debug/O3CPU.hh"
56 #include "debug/Quiesce.hh"
57 #include "enums/MemoryMode.hh"
75 tickEvent([this]{
tick(); },
"O3CPU tick",
77 threadExitEvent([
this]{ exitThreads(); },
"O3CPU exit threads",
82 removeInstsThisCycle(
false),
89 regFile(params.numPhysIntRegs,
90 params.numPhysFloatRegs,
91 params.numPhysVecRegs,
92 params.numPhysVecPredRegs,
94 params.isa[0]->regClasses()),
96 freeList(
name() +
".freelist", ®File),
100 scoreboard(
name() +
".scoreboard", regFile.totalNumPhysRegs()),
102 isa(numThreads, NULL),
104 timeBuffer(params.backComSize, params.forwardComSize),
105 fetchQueue(params.backComSize, params.forwardComSize),
106 decodeQueue(params.backComSize, params.forwardComSize),
107 renameQueue(params.backComSize, params.forwardComSize),
108 iewQueue(params.backComSize, params.forwardComSize),
109 activityRec(
name(), NumStages,
110 params.backComSize + params.forwardComSize,
115 lastRunningCycle(curCycle()),
119 "SMT is not supported in O3 in full system mode currently.");
122 "More workload items (%d) than threads (%d) on CPU %s.",
123 params.workload.size(), params.numThreads,
name());
125 if (!params.switched_out) {
128 _status = SwitchedOut;
131 if (params.checker) {
132 BaseCPU *temp_checker = params.checker;
133 checker =
dynamic_cast<Checker<DynInstPtr> *
>(temp_checker);
134 checker->setIcachePort(&fetch.getInstPort());
135 checker->setSystem(params.system);
141 thread.resize(numThreads);
142 tids.resize(numThreads);
150 fetch.setActiveThreads(&activeThreads);
151 decode.setActiveThreads(&activeThreads);
152 rename.setActiveThreads(&activeThreads);
153 iew.setActiveThreads(&activeThreads);
154 commit.setActiveThreads(&activeThreads);
157 fetch.setTimeBuffer(&timeBuffer);
158 decode.setTimeBuffer(&timeBuffer);
159 rename.setTimeBuffer(&timeBuffer);
160 iew.setTimeBuffer(&timeBuffer);
161 commit.setTimeBuffer(&timeBuffer);
164 fetch.setFetchQueue(&fetchQueue);
165 decode.setFetchQueue(&fetchQueue);
166 commit.setFetchQueue(&fetchQueue);
167 decode.setDecodeQueue(&decodeQueue);
168 rename.setDecodeQueue(&decodeQueue);
169 rename.setRenameQueue(&renameQueue);
170 iew.setRenameQueue(&renameQueue);
171 iew.setIEWQueue(&iewQueue);
172 commit.setIEWQueue(&iewQueue);
173 commit.setRenameQueue(&renameQueue);
175 commit.setIEWStage(&iew);
176 rename.setIEWStage(&iew);
177 rename.setCommitStage(&commit);
183 active_threads = params.workload.size();
186 panic(
"Workload Size too large. Increase the 'MaxThreads' "
187 "constant in cpu/o3/limits.hh or edit your workload size.");
193 const auto ®Classes = params.isa[0]->regClasses();
195 assert(params.numPhysIntRegs >=
196 numThreads * regClasses.at(
IntRegClass)->numRegs());
197 assert(params.numPhysFloatRegs >=
199 assert(params.numPhysVecRegs >=
200 numThreads * regClasses.at(
VecRegClass)->numRegs());
201 assert(params.numPhysVecPredRegs >=
203 assert(params.numPhysCCRegs >=
204 numThreads * regClasses.at(
CCRegClass)->numRegs());
209 params.numPhysCCRegs != 0,
210 "Non-zero number of physical CC regs specified, even though\n"
211 " ISA does not use them.");
213 rename.setScoreboard(&scoreboard);
214 iew.setScoreboard(&scoreboard);
217 for (
ThreadID tid = 0; tid < numThreads; tid++) {
218 isa[tid] = params.isa[tid];
219 commitRenameMap[tid].init(regClasses, ®File, &freeList);
220 renameMap[tid].init(regClasses, ®File, &freeList);
225 for (
ThreadID tid = 0; tid < active_threads; tid++) {
228 for (
auto &
id: *regClasses.at(
type)) {
232 renameMap[tid].setEntry(
id, phys_reg);
233 commitRenameMap[tid].setEntry(
id, phys_reg);
238 rename.setRenameMap(renameMap);
239 commit.setRenameMap(commitRenameMap);
240 rename.setFreeList(&freeList);
245 lastActivatedCycle = 0;
247 DPRINTF(O3CPU,
"Creating O3CPU object.\n");
250 thread.resize(numThreads);
252 for (
ThreadID tid = 0; tid < numThreads; ++tid) {
255 assert(numThreads == 1);
256 thread[tid] =
new ThreadState(
this, 0, NULL);
258 if (tid < params.workload.size()) {
259 DPRINTF(O3CPU,
"Workload[%i] process is %#x", tid,
261 thread[tid] =
new ThreadState(
this, tid, params.workload[tid]);
265 Process* dummy_proc = NULL;
267 thread[tid] =
new ThreadState(
this, tid, dummy_proc);
274 auto *o3_tc =
new ThreadContext;
280 if (params.checker) {
281 tc =
new CheckerThreadContext<ThreadContext>(o3_tc, checker);
285 o3_tc->thread = thread[tid];
288 thread[tid]->tc = tc;
291 threadContexts.push_back(tc);
295 if (!params.switched_out && interrupts.empty()) {
296 fatal(
"O3CPU %s has no interrupt controller.\n"
297 "Ensure createInterruptController() is called.\n",
name());
319 : statistics::
Group(cpu),
321 "Number of times that the entire CPU went into an idle state "
322 "and unscheduled itself"),
323 ADD_STAT(idleCycles, statistics::units::Cycle::get(),
324 "Total number of cycles that the CPU has spent unscheduled due "
327 "Total number of cycles that CPU has spent quiesced or waiting "
330 "Number of Instructions Simulated"),
332 "Number of Ops (including micro ops) Simulated"),
333 ADD_STAT(cpi, statistics::units::Rate<
334 statistics::units::Cycle, statistics::units::
Count>::get(),
335 "CPI: Cycles Per Instruction"),
336 ADD_STAT(totalCpi, statistics::units::Rate<
337 statistics::units::Cycle, statistics::units::
Count>::get(),
338 "CPI: Total CPI of All Threads"),
339 ADD_STAT(ipc, statistics::units::Rate<
340 statistics::units::
Count, statistics::units::Cycle>::get(),
341 "IPC: Instructions Per Cycle"),
342 ADD_STAT(totalIpc, statistics::units::Rate<
343 statistics::units::
Count, statistics::units::Cycle>::get(),
344 "IPC: Total IPC of All Threads"),
346 "Number of integer regfile reads"),
348 "Number of integer regfile writes"),
350 "Number of floating regfile reads"),
352 "Number of floating regfile writes"),
354 "number of vector regfile reads"),
356 "number of vector regfile writes"),
357 ADD_STAT(vecPredRegfileReads, statistics::units::
Count::get(),
358 "number of predicate regfile reads"),
359 ADD_STAT(vecPredRegfileWrites, statistics::units::
Count::get(),
360 "number of predicate regfile writes"),
362 "number of cc regfile reads"),
364 "number of cc regfile writes"),
366 "number of misc regfile reads"),
368 "number of misc regfile writes")
448 DPRINTF(O3CPU,
"\n\nO3CPU: Ticking main, O3CPU.\n");
484 DPRINTF(O3CPU,
"Switched out!\n");
493 DPRINTF(O3CPU,
"Scheduling next tick!\n");
511 thread[tid]->noSquashFromTC =
true;
516 thread[tid]->noSquashFromTC =
false;
539 DPRINTF(O3CPU,
"[tid:%i] Calling activate thread.\n", tid);
543 DPRINTF(O3CPU,
"[tid:%i] Adding to active threads list\n", tid);
560 DPRINTF(O3CPU,
"[tid:%i] Calling deactivate thread.\n", tid);
564 DPRINTF(O3CPU,
"[tid:%i] Removing from active threads list\n",
638 DPRINTF(O3CPU,
"[tid:%i] Suspending Thread Context.\n", tid);
650 DPRINTF(Quiesce,
"Suspending Context\n");
659 DPRINTF(O3CPU,
"[tid:%i] Halt Context called. Deallocating\n", tid);
680 DPRINTF(O3CPU,
"[tid:%i] Initializing thread into CPU");
690 const auto ®Classes =
isa[tid]->regClasses();
694 for (
auto &
id: *regClasses.at(
type)) {
718 DPRINTF(O3CPU,
"[tid:%i] Removing thread context from CPU.\n", tid);
786 DPRINTF(O3CPU,
"Interrupt %s being handled\n", interrupt->name());
787 trap(interrupt, 0,
nullptr);
800 thread[tid]->serialize(cp);
806 thread[tid]->unserialize(cp);
819 DPRINTF(Drain,
"Draining...\n");
835 DPRINTF(Drain,
"Currently suspended so activate %i \n",
846 DPRINTF(Drain,
"CPU not drained\n");
850 DPRINTF(Drain,
"CPU is already drained\n");
880 DPRINTF(Drain,
"CPU done draining, processing drain event\n");
903 DPRINTF(Drain,
"Main CPU structures not drained.\n");
908 DPRINTF(Drain,
"Fetch not drained.\n");
913 DPRINTF(Drain,
"Decode not drained.\n");
918 DPRINTF(Drain,
"Rename not drained.\n");
923 DPRINTF(Drain,
"IEW not drained.\n");
928 DPRINTF(Drain,
"Commit not drained.\n");
943 DPRINTF(Drain,
"Resuming...\n");
952 DPRINTF(Drain,
"Activating thread: %i\n",
i);
969 DPRINTF(O3CPU,
"Switching out\n");
993 auto *oldO3CPU =
dynamic_cast<CPU *
>(oldCPU);
1005 fatal(
"The O3 CPU requires the memory system to be in "
1006 "'timing' mode.\n");
1013 return isa[tid]->readMiscRegNoEffect(misc_reg);
1020 return isa[tid]->readMiscReg(misc_reg);
1026 isa[tid]->setMiscRegNoEffect(misc_reg,
val);
1033 isa[tid]->setMiscReg(misc_reg,
val);
1211 thread[tid]->noSquashFromTC =
true;
1227 if (!inst->isMicroop() || inst->isLastMicroop()) {
1229 thread[tid]->threadStats.numInsts++;
1233 thread[tid]->comInstEventQueue.serviceEvents(
thread[tid]->numInst);
1236 thread[tid]->threadStats.numOps++;
1245 DPRINTF(O3CPU,
"Removing committed instruction [tid:%i] PC %s "
1247 inst->threadNumber, inst->pcState(), inst->seqNum);
1258 DPRINTF(O3CPU,
"Thread %i: Deleting instructions from instruction"
1263 bool rob_empty =
false;
1268 DPRINTF(O3CPU,
"ROB is empty, squashing all insts.\n");
1273 DPRINTF(O3CPU,
"ROB is not empty, squashing insts not in ROB.\n");
1284 while (inst_it != end_it) {
1310 DPRINTF(O3CPU,
"Deleting instructions from instruction "
1311 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1312 tid, seq_num, (*inst_iter)->seqNum);
1314 while ((*inst_iter)->seqNum > seq_num) {
1316 bool break_loop = (inst_iter ==
instList.begin());
1330 if ((*instIt)->threadNumber == tid) {
1331 DPRINTF(O3CPU,
"Squashing instruction, "
1332 "[tid:%i] [sn:%lli] PC %s\n",
1333 (*instIt)->threadNumber,
1335 (*instIt)->pcState());
1338 (*instIt)->setSquashed();
1351 DPRINTF(O3CPU,
"Removing instruction, "
1352 "[tid:%i] [sn:%lli] PC %s\n",
1378 cprintf(
"Dumping Instruction List\n");
1380 while (inst_list_it !=
instList.end()) {
1381 cprintf(
"Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1383 num, (*inst_list_it)->pcState().instAddr(),
1384 (*inst_list_it)->threadNumber,
1385 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1386 (*inst_list_it)->isSquashed());
1402 DPRINTF(Activity,
"CPU already running.\n");
1406 DPRINTF(Activity,
"Waking up CPU\n");
1427 DPRINTF(Quiesce,
"Suspended Processor woken\n");
1452 unsigned high_thread = *list_begin;
1463 DPRINTF(O3CPU,
"Thread %d is inserted to exitingThreads list\n", tid);
1515 bool readyToExit = it->second;
1518 DPRINTF(O3CPU,
"Exiting thread %d\n", thread_id);
1546 req->setContext(
thread[tid]->contextId());
1547 req->setHtmAbortCause(cause);
1549 assert(req->isHTMAbort());
1552 uint8_t *memData =
new uint8_t[8];
1559 panic(
"HTM abort signal was not sent to the memory subsystem.");
void advance()
Advances the activity buffer, decrementing the activityCount if active communication just left the ti...
void reset()
Clears the time buffer and the activity count.
void activity()
Records that there is activity this cycle.
bool active()
Returns if the CPU should be active.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
void schedulePowerGatingEvent()
void regProbePoints() override
Register probe points for this object.
uint32_t taskId() const
Get cpu task id.
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
gem5::BaseCPU::BaseCPUStats baseStats
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
void deschedulePowerGatingEvent()
std::vector< BaseInterrupts * > interrupts
void startup() override
startup() is the final initialization call before simulation.
virtual void switchOut()
Prepare for another CPU to take over execution.
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
std::vector< ThreadContext * > threadContexts
bool switchedOut() const
Determine if the CPU is switched out.
virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc)
Helper method to trigger PMU probes for a committed instruction.
RequestorID _dataRequestorId
data side request id that must be placed in all requests
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Tick nextCycle() const
Based on the clock of the object, determine the start tick of the first cycle that is at least one cy...
Cycles is a wrapper class for representing cycle counts, i.e.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
void dataStatic(T *p)
Set the data pointer to the following value that should not be freed.
static PacketPtr createRead(const RequestPtr &req)
Constructor-like methods that return Packets based on Request objects.
void setHtmTransactional(uint64_t val)
Stipulates that this packet/request originates in the CPU executing in transactional mode,...
constexpr RegClassType classValue() const
ProbePointArg generates a point for the class of Arg.
Register ID: describe an architectural register with its class and index.
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
@ PHYSICAL
The virtual address is also the physical address.
@ HTM_ABORT
The request aborts a HTM transaction.
bool isTimingMode() const
Is the system in timing mode?
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual void setStatus(Status new_status)=0
virtual const PCStateBase & pcState() const =0
@ Halted
Permanently shut down.
@ Suspended
Temporarily inactive.
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
std::vector< BaseISA * > isa
void instDone(ThreadID tid, const DynInstPtr &inst)
Function to tell the CPU that an instruction has completed.
IEW iew
The issue/execute/writeback stages.
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
void dumpInsts()
Debug function to print all instructions on the list.
void drainSanityCheck() const
Perform sanity checks after a drain.
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override
This function is used to instruct the memory subsystem that a transaction should be aborted and the s...
std::list< DynInstPtr > instList
List of all the instructions in flight.
ListIt addInst(const DynInstPtr &inst)
Function to add instruction onto the head of the list of the instructions.
void setArchReg(const RegId ®, RegVal val, ThreadID tid)
ROB rob
The re-order buffer.
InstSeqNum globalSeqNum
The global sequence number counter.
void haltContext(ThreadID tid) override
Remove Thread from Active Threads List && Remove Thread Context from CPU.
TimeBuffer< DecodeStruct > decodeQueue
The decode stage's instruction queue.
EventFunctionWrapper tickEvent
The tick event used for scheduling CPU ticks.
UnifiedRenameMap commitRenameMap[MaxThreads]
The commit rename map.
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
void startup() override
startup() is the final initialization call before simulation.
void drainResume() override
Resumes execution after a drain.
RegVal getReg(PhysRegIdPtr phys_reg)
Rename rename
The dispatch stage.
void regProbePoints() override
Register probe points.
void deactivateThread(ThreadID tid)
Remove Thread from Active Threads List.
Counter totalInsts() const override
Count the Total Instructions Committed in the CPU.
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
CPU(const BaseO3CPUParams ¶ms)
Constructs a CPU with the given parameters.
ProbePointArg< PacketPtr > * ppInstAccessComplete
void * getWritableReg(PhysRegIdPtr phys_reg)
void exitThreads()
Terminate all threads that are ready to exit.
ThreadID getFreeTid()
Gets a free thread id.
std::vector< ThreadState * > thread
Pointers to all of the threads in the CPU.
void tick()
Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should d...
void removeThread(ThreadID tid)
Remove all of a thread's context from CPU.
void commitDrained(ThreadID tid)
Commit has reached a safe point to drain a thread.
void unscheduleTickEvent()
Unschedule tick event, regardless of its current state.
gem5::o3::CPU::CPUStats cpuStats
UnifiedFreeList freeList
The free list.
Status _status
Overall CPU status.
std::list< DynInstPtr >::iterator ListIt
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
virtual void wakeup(ThreadID tid) override
bool removeInstsThisCycle
Records if instructions need to be removed this cycle due to being retired or squashed.
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
std::vector< ThreadID > tids
Available thread ids in the cpu.
UnifiedRenameMap renameMap[MaxThreads]
The rename map.
ProbePointArg< std::pair< DynInstPtr, PacketPtr > > * ppDataAccessComplete
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
Remove all instructions younger than the given sequence number.
std::queue< ListIt > removeList
List of all the instructions that will be removed at the end of this cycle.
TimeBuffer< FetchStruct > fetchQueue
The fetch stage's instruction queue.
void cleanUpRemovedInsts()
Cleans up all instructions on the remove list.
void setReg(PhysRegIdPtr phys_reg, RegVal val)
Commit commit
The commit stage.
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
void removeInstsNotInROB(ThreadID tid)
Remove all instructions that are not currently in the ROB.
void takeOverFrom(BaseCPU *oldCPU) override
Takes over from another CPU.
void switchOut() override
Switches out this CPU.
PhysRegFile regFile
The register file.
Cycles lastRunningCycle
The cycle that the CPU was last running, used for statistics.
bool tryDrain()
Check if the pipeline has drained and signal drain done.
ActivityRecorder activityRec
The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and...
void processInterrupts(const Fault &interrupt)
Processes any an interrupt fault.
void squashFromTC(ThreadID tid)
Initiates a squash of all in-flight instructions for a given thread.
TimeBuffer< TimeStruct > timeBuffer
The main time buffer to do backwards communication.
Tick lastActivatedCycle
The cycle that the CPU was last activated by a new thread.
void squashInstIt(const ListIt &instIt, ThreadID tid)
Removes the instruction pointed to by the iterator.
System * system
Pointer to the system.
Decode decode
The decode stage.
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
RegVal getArchReg(const RegId ®, ThreadID tid)
Architectural register accessors.
TimeBuffer< IEWStruct > iewQueue
The IEW stage's instruction queue.
EventFunctionWrapper threadExitEvent
The exit event used for terminating all ready-to-exit threads.
DrainState drain() override
Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses.
std::list< ThreadID > activeThreads
Active Threads List.
Fault getInterrupts()
Returns the Fault for any valid interrupt.
void scheduleTickEvent(Cycles delay)
Schedule tick event, regardless of its current state.
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const
Register accessors.
bool isCpuDrained() const
Check if a system is in a drained state.
Fetch fetch
The fetch stage.
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
void scheduleThreadExitEvent(ThreadID tid)
If a thread is trying to exit and its corresponding trap event has been completed,...
void updateThreadPriority()
Update The Order In Which We Process Threads.
bool isThreadExiting(ThreadID tid) const
Is the thread trying to exit?
void removeFrontInst(const DynInstPtr &inst)
Remove an instruction from the front end of the list.
void * getWritableArchReg(const RegId ®, ThreadID tid)
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
void init() override
Initialize the CPU.
void activateThread(ThreadID tid)
Add Thread to Active Threads List.
Scoreboard scoreboard
Integer Register Scoreboard.
std::unordered_map< ThreadID, bool > exitingThreads
This is a list of threads that are trying to exit.
Counter totalOps() const override
Count the Total Ops (including micro ops) committed in the CPU.
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
void insertThread(ThreadID tid)
Setup CPU to insert a thread's context.
TimeBuffer< RenameStruct > renameQueue
The rename stage's instruction queue.
void startupStage()
Initializes stage by sending back the number of free entries.
bool executingHtmTransaction(ThreadID) const
Is the CPU currently processing a HTM transaction?
void deactivateThread(ThreadID tid)
Deschedules a thread from scheduling.
void tick()
Ticks the commit stage, which tries to commit instructions.
void resetHtmStartsStops(ThreadID)
void drainSanityCheck() const
Perform sanity checks after a drain.
void takeOverFrom()
Takes over from another CPU's thread.
void clearStates(ThreadID tid)
Clear all thread-specific states.
void drainResume()
Resumes execution after draining.
const PCStateBase & pcState(ThreadID tid)
Reads the PC of a specific thread.
void drain()
Initializes the draining of commit.
void generateTCEvent(ThreadID tid)
Records that commit needs to initiate a squash due to an external state update through the TC.
void regProbePoints()
Registers probes.
void setThreads(std::vector< ThreadState * > &threads)
Sets the list of threads.
bool isDrained() const
Has the stage drained?
void takeOverFrom()
Takes over from another CPU's thread.
bool isDrained() const
Has the stage drained?
void clearStates(ThreadID tid)
Clear all thread-specific states.
void drainSanityCheck() const
Perform sanity checks after a drain.
void tick()
Ticks decode, processing all input signals and decoding as many instructions as possible.
void deactivateThread(ThreadID tid)
For priority-based fetch policies, need to keep update priorityList.
void takeOverFrom()
Takes over from another CPU's thread.
void startupStage()
Initialize stage.
void wakeFromQuiesce()
Tells fetch to wake up from a quiesce instruction.
void drainSanityCheck() const
Perform sanity checks after a drain.
void regProbePoints()
Registers probes.
void drainStall(ThreadID tid)
Stall the fetch stage after reaching a safe drain point.
void drainResume()
Resume after a drain.
void clearStates(ThreadID tid)
Clear all thread-specific states.
bool isDrained() const
Has the stage drained?
void tick()
Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible.
void takeOverFrom()
Takes over from another CPU's thread.
void clearStates(ThreadID tid)
Clear all thread-specific states.
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
void drainSanityCheck() const
Perform sanity checks after a drain.
bool isDrained() const
Has the stage drained?
InstructionQueue instQueue
Instruction queue.
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle.
LSQ ldstQueue
Load / store queue.
void regProbePoints()
Registers probes.
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
RequestPort & getDataPort()
int getCount()
Returns the number of instructions in all of the queues.
void resetHtmStartsStops(ThreadID tid)
RegVal getReg(PhysRegIdPtr phys_reg) const
void * getWritableReg(PhysRegIdPtr phys_reg)
void setReg(PhysRegIdPtr phys_reg, RegVal val)
void resetEntries()
Re-adjust ROB partitioning.
DynInstPtr readTailInst(ThreadID tid)
Returns pointer to the tail instruction within the ROB.
bool isEmpty() const
Returns if the ROB is empty.
void startupStage()
Initializes variables for the stage.
void tick()
Ticks rename, which processes all input signals and attempts to rename as many instructions as possib...
void drainSanityCheck() const
Perform sanity checks after a drain.
void takeOverFrom()
Takes over from another CPU's thread.
void regProbePoints()
Registers probes.
bool isDrained() const
Has the stage drained?
void clearStates(ThreadID tid)
Clear all thread-specific states.
void setReg(PhysRegIdPtr phys_reg)
Sets the register as ready.
PhysRegIdPtr getReg(RegClassType type)
Gets a free register of type type.
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
PhysRegIdPtr lookup(const RegId &arch_reg) const
Look up the physical register mapped to an architectural register.
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Derived & precision(int _precision)
Set the precision and marks this stat to print at the end of simulation.
Derived & init(size_type size)
Set this vector to have the given size.
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
void signalDrainDone() const
Signal that an object is drained.
DrainState drainState() const
Return the current drain state of an object.
DrainState
Object drain/handover states.
@ Draining
Draining buffers pending serialization/handover.
@ Running
Running normally.
@ Drained
Buffers drained, ready for serialization/handover.
void deschedule(Event &event)
bool scheduled() const
Determine if the current event is scheduled.
void schedule(Event &event, Tick when)
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
static const Priority CPU_Exit_Pri
If we want to exit a thread in a CPU, it comes after CPU_Tick_Pri.
#define panic(...)
This implements a cprintf based panic() function.
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
#define fatal(...)
This implements a cprintf based fatal() function.
ProbeManager * getProbeManager()
Get the probe manager for this object.
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
static constexpr int MaxThreads
void quiesceCycles(ThreadContext *tc, uint64_t cycles)
const FlagsType total
Print the total.
double Counter
All counters are of 64-bit values.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
int16_t ThreadID
Thread index/ID type.
std::shared_ptr< Request > RequestPtr
const ThreadID InvalidThreadID
void cprintf(const char *format, const Args &...args)
Tick curTick()
The universal simulation clock.
std::ostream CheckpointOut
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
constexpr decltype(nullptr) NoFault
RegClassType
Enumerate the classes of registers.
@ FloatRegClass
Floating-point register.
@ CCRegClass
Condition-code register.
@ VecRegClass
Vector Register.
@ IntRegClass
Integer register.
@ VecElemClass
Vector Register Native Elem lane.
statistics::Scalar numCycles
statistics::Scalar timesIdled
Stat for total number of times the CPU is descheduled.
statistics::Scalar ccRegfileReads
statistics::Scalar ccRegfileWrites
statistics::Scalar quiesceCycles
Stat for total number of cycles the CPU spends descheduled due to a quiesce operation or waiting for ...
statistics::Scalar intRegfileReads
statistics::Scalar vecRegfileWrites
statistics::Formula ipc
Stat for the IPC per thread.
statistics::Scalar miscRegfileReads
statistics::Scalar fpRegfileWrites
statistics::Scalar vecPredRegfileWrites
statistics::Formula totalCpi
Stat for the total CPI.
statistics::Scalar vecPredRegfileReads
statistics::Scalar vecRegfileReads
statistics::Vector committedInsts
Stat for the number of committed instructions per thread.
statistics::Scalar fpRegfileReads
statistics::Scalar idleCycles
Stat for total number of cycles the CPU spends descheduled.
statistics::Formula cpi
Stat for the CPI per thread.
statistics::Scalar intRegfileWrites
statistics::Scalar miscRegfileWrites
statistics::Formula totalIpc
Stat for the total IPC.
statistics::Vector committedOps
Stat for the number of committed ops (including micro ops) per thread.
const std::string & name()