59 #include "debug/Activity.hh"
60 #include "debug/Commit.hh"
61 #include "debug/CommitRate.hh"
62 #include "debug/Drain.hh"
63 #include "debug/ExecFaulting.hh"
64 #include "debug/HtmCpu.hh"
65 #include "debug/O3PipeView.hh"
66 #include "params/BaseO3CPU.hh"
85 : commitPolicy(params.smtCommitPolicy),
87 iewToCommitDelay(params.iewToCommitDelay),
88 commitToIEWDelay(params.commitToIEWDelay),
89 renameToROBDelay(params.renameToROBDelay),
90 fetchToCommitDelay(params.commitToFetchDelay),
91 renameWidth(params.renameWidth),
92 commitWidth(params.commitWidth),
93 numThreads(params.numThreads),
96 trapLatency(params.trapLatency),
97 canHandleInterrupts(true),
98 avoidQuiesceLiveLock(false),
102 fatal(
"commitWidth (%d) is larger than compiled limit (%d),\n"
103 "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
122 pc[tid].reset(params.isa[0]->newPCState());
149 : statistics::
Group(cpu,
"commit"),
150 ADD_STAT(commitSquashedInsts, statistics::units::
Count::get(),
151 "The number of squashed insts skipped by commit"),
152 ADD_STAT(commitNonSpecStalls, statistics::units::
Count::get(),
153 "The number of times commit has been forced to stall to "
154 "communicate backwards"),
156 "The number of times a branch was mispredicted"),
158 "Number of insts commited each cycle"),
160 "Number of instructions committed"),
162 "Number of ops (including micro ops) committed"),
164 "Number of memory references committed"),
165 ADD_STAT(loads, statistics::units::
Count::get(),
"Number of loads committed"),
167 "Number of atomic instructions committed"),
169 "Number of memory barriers committed"),
171 "Number of branches committed"),
172 ADD_STAT(vectorInstructions, statistics::units::
Count::get(),
173 "Number of committed Vector instructions."),
175 "Number of committed floating point instructions."),
177 "Number of committed integer instructions."),
179 "Number of function calls committed."),
181 "Class of committed instruction"),
182 ADD_STAT(commitEligibleSamples, statistics::units::Cycle::get(),
183 "number cycles where commit BW limit reached")
185 using namespace statistics;
320 toIEW->commitInfo[tid].usedROB =
true;
322 toIEW->commitInfo[tid].emptyROB =
true;
366 panic(
"cannot drain partially through a HTM transaction");
384 if (
pc[tid]->microPC() != 0)
451 while (threads != end) {
464 DPRINTF(Activity,
"Deactivating stage.\n");
467 DPRINTF(Activity,
"Activating stage.\n");
480 while (threads != end) {
500 DPRINTF(
Commit,
"Generating trap event for [tid:%i]\n", tid);
506 Cycles latency = std::dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ?
510 if (inst_fault !=
nullptr &&
511 std::dynamic_pointer_cast<GenericHtmFailureFault>(inst_fault)) {
519 thread[tid]->trapPending =
true;
526 DPRINTF(
Commit,
"Generating TC squash event for [tid:%i]\n", tid);
550 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
554 toIEW->commitInfo[tid].squash =
true;
558 toIEW->commitInfo[tid].robSquashing =
true;
560 toIEW->commitInfo[tid].mispredictInst = NULL;
561 toIEW->commitInfo[tid].squashInst = NULL;
571 DPRINTF(
Commit,
"Squashing from trap, restarting at PC %s\n", *
pc[tid]);
573 thread[tid]->trapPending =
false;
574 thread[tid]->noSquashFromTC =
false;
590 thread[tid]->noSquashFromTC =
false;
591 assert(!
thread[tid]->trapPending);
603 "restarting at PC %s\n", *
pc[tid]);
619 DPRINTF(
Commit,
"Executing squash after for [tid:%i] inst [sn:%llu]\n",
620 tid, head_inst->seqNum);
641 while (threads != end) {
654 " insts this cycle.\n", tid);
656 toIEW->commitInfo[tid].robSquashing =
true;
668 while (threads != end) {
678 DPRINTF(
Commit,
"[tid:%i] Instruction [sn:%llu] PC %s is head of"
679 " ROB and ready to commit\n",
680 tid, inst->seqNum, inst->pcState());
687 DPRINTF(
Commit,
"[tid:%i] Can't commit, Instruction [sn:%llu] PC "
688 "%s is head of ROB and not ready\n",
689 tid, inst->seqNum, inst->pcState());
692 DPRINTF(
Commit,
"[tid:%i] ROB has %d insts & %d free entries.\n",
698 DPRINTF(Activity,
"Activity This Cycle.\n");
710 DPRINTF(
Commit,
"Pending interrupt is cleared by requestor before "
711 "it got handled. Restart fetching from the orig path.\n");
712 toIEW->commitInfo[0].clearInterrupt =
true;
726 toIEW->commitInfo[0].clearInterrupt =
true;
728 assert(!
thread[0]->noSquashFromTC);
729 thread[0]->noSquashFromTC =
true;
740 thread[0]->noSquashFromTC =
false;
752 "flight, ROB is %sempty\n",
779 toIEW->commitInfo[0].interruptPending =
true;
797 int num_squashing_threads = 0;
799 while (threads != end) {
831 if (
fromIEW->mispredictInst[tid]) {
833 "[tid:%i] Squashing due to branch mispred "
834 "PC:%#x [sn:%llu]\n",
836 fromIEW->mispredictInst[tid]->pcState().instAddr(),
840 "[tid:%i] Squashing due to order violation [sn:%llu]\n",
841 tid,
fromIEW->squashedSeqNum[tid]);
853 if (
fromIEW->includeSquashInst[tid]) {
864 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
866 toIEW->commitInfo[tid].squash =
true;
870 toIEW->commitInfo[tid].robSquashing =
true;
872 toIEW->commitInfo[tid].mispredictInst =
874 toIEW->commitInfo[tid].branchTaken =
876 toIEW->commitInfo[tid].squashInst =
878 if (
toIEW->commitInfo[tid].mispredictInst) {
879 if (
toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
880 toIEW->commitInfo[tid].branchTaken =
true;
882 ++
stats.branchMispredicts;
889 num_squashing_threads++;
895 if (num_squashing_threads) {
910 while (threads != end) {
914 toIEW->commitInfo[tid].usedROB =
true;
934 toIEW->commitInfo[tid].usedROB =
true;
935 toIEW->commitInfo[tid].emptyROB =
true;
955 DPRINTF(
Commit,
"Trying to commit instructions in the ROB.\n");
957 unsigned num_committed = 0;
976 toIEW->commitInfo[0].clearInterrupt =
true;
991 ThreadID tid = head_inst->threadNumber;
993 assert(tid == commit_thread);
996 "Trying to commit head instruction, [tid:%i] [sn:%llu]\n",
997 tid, head_inst->seqNum);
1001 if (head_inst->isSquashed()) {
1008 ++
stats.commitSquashedInsts;
1015 set(
pc[tid], head_inst->pcState());
1018 bool commit_success =
commitHead(head_inst, num_committed);
1020 if (commit_success) {
1022 stats.committedInstType[tid][head_inst->opClass()]++;
1028 if (head_inst->isHtmStart())
1032 if (head_inst->inHtmTransactionalState()) {
1039 if (head_inst->isHtmStop())
1045 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1052 assert(!head_inst->isStoreConditional() ||
1053 head_inst->isCompleted() ||
1054 !head_inst->readPredicate());
1057 head_inst->updateMiscRegs();
1067 head_inst->staticInst->advancePC(*
pc[tid]);
1074 if (head_inst->isSquashAfter())
1079 !
thread[tid]->trapPending) {
1083 DPRINTF(Drain,
"Draining: %i:%s\n", tid, *
pc[tid]);
1090 bool onInstBoundary = !head_inst->isMicroop() ||
1091 head_inst->isLastMicroop() ||
1092 !head_inst->isDelayedCommit();
1094 if (onInstBoundary) {
1099 assert(!
thread[tid]->noSquashFromTC &&
1100 !
thread[tid]->trapPending);
1102 oldpc =
pc[tid]->instAddr();
1103 thread[tid]->pcEventQueue.service(
1104 oldpc,
thread[tid]->getTC());
1106 }
while (oldpc !=
pc[tid]->instAddr());
1109 "PC skip function event, stopping commit\n");
1127 "[tid:%i] [sn:%llu].\n",
1128 head_inst->pcState(), tid ,head_inst->seqNum);
1134 DPRINTF(CommitRate,
"%i\n", num_committed);
1135 stats.numCommittedDist.sample(num_committed);
1138 stats.commitEligibleSamples++;
1147 ThreadID tid = head_inst->threadNumber;
1151 if (!head_inst->isExecuted()) {
1154 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1155 || head_inst->isReadBarrier() || head_inst->isWriteBarrier()
1156 || head_inst->isAtomic()
1157 || (head_inst->isLoad() && head_inst->strictlyOrdered()));
1160 "Encountered a barrier or non-speculative "
1161 "instruction [tid:%i] [sn:%llu] "
1162 "at the head of the ROB, PC %s.\n",
1163 tid, head_inst->seqNum, head_inst->pcState());
1167 "[tid:%i] [sn:%llu] "
1168 "Waiting for all stores to writeback.\n",
1169 tid, head_inst->seqNum);
1173 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1177 head_inst->clearCanCommit();
1179 if (head_inst->isLoad() && head_inst->strictlyOrdered()) {
1181 "Strictly ordered load, PC %s.\n",
1182 tid, head_inst->seqNum, head_inst->pcState());
1183 toIEW->commitInfo[tid].strictlyOrdered =
true;
1184 toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1186 ++
stats.commitNonSpecStalls;
1193 Fault inst_fault = head_inst->getFault();
1198 if (inst_fault !=
NoFault && head_inst->inHtmTransactionalState()) {
1200 if (!std::dynamic_pointer_cast<GenericHtmFailureFault>(inst_fault)) {
1201 DPRINTF(HtmCpu,
"%s - fault (%s) encountered within transaction"
1202 " - converting to GenericHtmFailureFault\n",
1203 head_inst->staticInst->getName(), inst_fault->name());
1204 inst_fault = std::make_shared<GenericHtmFailureFault>(
1205 head_inst->getHtmTransactionUid(),
1213 if (!head_inst->isStore() && inst_fault ==
NoFault) {
1214 head_inst->setCompleted();
1218 DPRINTF(
Commit,
"Inst [tid:%i] [sn:%llu] PC %s has a fault\n",
1219 tid, head_inst->seqNum, head_inst->pcState());
1223 "[tid:%i] [sn:%llu] "
1224 "Stores outstanding, fault must wait.\n",
1225 tid, head_inst->seqNum);
1229 head_inst->setCompleted();
1238 assert(!
thread[tid]->noSquashFromTC);
1242 thread[tid]->noSquashFromTC =
true;
1252 head_inst->staticInst);
1255 thread[tid]->noSquashFromTC =
false;
1260 "[tid:%i] [sn:%llu] Committing instruction with fault\n",
1261 tid, head_inst->seqNum);
1262 if (head_inst->traceData) {
1265 if (debug::ExecFaulting
1266 &&
dynamic_cast<ReExec*
>(inst_fault.get()) ==
nullptr) {
1268 head_inst->traceData->setFaulting(
true);
1269 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1270 head_inst->traceData->setCPSeq(
thread[tid]->numOp);
1271 head_inst->traceData->dump();
1273 delete head_inst->traceData;
1274 head_inst->traceData = NULL;
1285 "[tid:%i] [sn:%llu] Committing instruction with PC %s\n",
1286 tid, head_inst->seqNum, head_inst->pcState());
1287 if (head_inst->traceData) {
1288 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1289 head_inst->traceData->setCPSeq(
thread[tid]->numOp);
1290 head_inst->traceData->dump();
1291 delete head_inst->traceData;
1292 head_inst->traceData = NULL;
1294 if (head_inst->isReturn()) {
1296 "[tid:%i] [sn:%llu] Return Instruction Committed PC %s \n",
1297 tid, head_inst->seqNum, head_inst->pcState());
1301 for (
int i = 0;
i < head_inst->numDestRegs();
i++) {
1303 head_inst->renamedDestIdx(
i));
1308 if (head_inst->isHtmStart())
1315 if (debug::O3PipeView) {
1316 head_inst->commitTick =
curTick() - head_inst->fetchTick;
1321 if (head_inst->isStore() || head_inst->isAtomic())
1331 DPRINTF(
Commit,
"Getting instructions from Rename stage.\n");
1336 for (
int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1340 if (!inst->isSquashed() &&
1345 DPRINTF(
Commit,
"[tid:%i] [sn:%llu] Inserting PC %s into ROB.\n",
1346 tid, inst->seqNum, inst->pcState());
1355 "Instruction PC %s was squashed, skipping.\n",
1356 tid, inst->seqNum, inst->pcState());
1366 for (
int inst_num = 0; inst_num <
fromIEW->size; ++inst_num) {
1367 assert(
fromIEW->insts[inst_num]);
1368 if (!
fromIEW->insts[inst_num]->isSquashed()) {
1371 fromIEW->insts[inst_num]->threadNumber,
1372 fromIEW->insts[inst_num]->pcState(),
1373 fromIEW->insts[inst_num]->seqNum);
1376 fromIEW->insts[inst_num]->setCanCommit();
1386 if (!inst->isMicroop() || inst->isLastMicroop())
1387 stats.instsCommitted[tid]++;
1388 stats.opsCommitted[tid]++;
1392 if (!inst->isNop() && !inst->isInstPrefetch()) {
1399 if (inst->isControl())
1400 stats.branches[tid]++;
1405 if (inst->isMemRef()) {
1406 stats.memRefs[tid]++;
1408 if (inst->isLoad()) {
1412 if (inst->isAtomic()) {
1417 if (inst->isFullMemBarrier()) {
1418 stats.membars[tid]++;
1422 if (inst->isInteger())
1423 stats.integer[tid]++;
1426 if (inst->isFloating())
1427 stats.floating[tid]++;
1429 if (inst->isVector())
1430 stats.vectorInstructions[tid]++;
1434 stats.functionCalls[tid]++;
1448 case CommitPolicy::RoundRobin:
1451 case CommitPolicy::OldestReady:
1477 while (pri_iter != end) {
1501 unsigned oldest = 0;
1502 unsigned oldest_seq_num = 0;
1508 while (threads != end) {
1522 oldest_seq_num = head_inst->seqNum;
1524 }
else if (head_inst->seqNum < oldest_seq_num) {
1526 oldest_seq_num = head_inst->seqNum;
Cycles syscallRetryLatency
void clearInterrupts(ThreadID tid)
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
bool checkInterrupts(ThreadID tid) const
void traceFunctions(Addr pc)
virtual PCStateBase * newPCState(Addr new_inst_addr=0) const =0
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Cycles is a wrapper class for representing cycle counts, i.e.
virtual std::string name() const
ProbePointArg generates a point for the class of Arg.
virtual BaseISA * getIsaPtr() const =0
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
void instDone(ThreadID tid, const DynInstPtr &inst)
Function to tell the CPU that an instruction has completed.
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
std::list< DynInstPtr > instList
List of all the instructions in flight.
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
void commitDrained(ThreadID tid)
Commit has reached a safe point to drain a thread.
void activityThisCycle()
Records that there was time buffer activity this cycle.
void processInterrupts(const Fault &interrupt)
Processes any an interrupt fault.
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
Fault getInterrupts()
Returns the Fault for any valid interrupt.
void scheduleThreadExitEvent(ThreadID tid)
If a thread is trying to exit and its corresponding trap event has been completed,...
bool isThreadExiting(ThreadID tid) const
Is the thread trying to exit?
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
Commit handles single threaded and SMT commit.
ThreadStatus commitStatus[MaxThreads]
Per-thread status.
TimeBuffer< IEWStruct >::wire fromIEW
Wire to read information from IEW queue.
std::vector< ThreadState * > thread
Vector of all of the threads.
ThreadID oldestReady()
Returns the thread ID to use based on an oldest instruction policy.
ProbePointArg< DynInstPtr > * ppCommitStall
void squashFromSquashAfter(ThreadID tid)
Handles a squash from a squashAfter() request.
void squashAll(ThreadID tid)
Squashes all in flight instructions.
void startupStage()
Initializes stage by sending back the number of free entries.
bool changedROBNumEntries[MaxThreads]
Records if the number of ROB entries has changed this cycle.
bool changedROBEntries()
Returns if any of the threads have the number of ROB entries changed on this cycle.
DynInstPtr squashAfterInst[MaxThreads]
Instruction passed to squashAfter().
bool executingHtmTransaction(ThreadID) const
Is the CPU currently processing a HTM transaction?
CommitStatus _status
Overall commit status.
void setIEWQueue(TimeBuffer< IEWStruct > *iq_ptr)
Sets the pointer to the queue coming from IEW.
size_t numROBFreeEntries(ThreadID tid)
Returns the number of free ROB entries for a specific thread.
void setFetchQueue(TimeBuffer< FetchStruct > *fq_ptr)
void processTrapEvent(ThreadID tid)
Mark the thread as processing a trap.
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets the pointer to the queue coming from rename.
bool checkEmptyROB[MaxThreads]
Records if commit should check if the ROB is truly empty (see commit_impl.hh).
void generateTrapEvent(ThreadID tid, Fault inst_fault)
Generates an event to schedule a squash due to a trap.
void deactivateThread(ThreadID tid)
Deschedules a thread from scheduling.
TimeBuffer< TimeStruct >::wire toIEW
Wire to write information heading to previous stages.
CPU * cpu
Pointer to O3CPU.
void squashFromTC(ThreadID tid)
Handles squashing due to an TC write.
const ThreadID numThreads
Number of Active Threads.
ProbePointArg< DynInstPtr > * ppSquash
To probe when an instruction is squashed.
Commit(CPU *_cpu, const BaseO3CPUParams ¶ms)
Construct a Commit with the given parameters.
bool trapInFlight[MaxThreads]
Records if there is a trap currently in flight.
void handleInterrupt()
Handles processing an interrupt.
const Cycles fetchToCommitDelay
void propagateInterrupt()
Get fetch redirecting so we can handle an interrupt.
std::string name() const
Returns the name of the Commit.
TimeBuffer< FetchStruct > * fetchQueue
void setROB(ROB *rob_ptr)
Sets pointer to the ROB.
int htmStarts[MaxThreads]
CommitPolicy commitPolicy
Commit policy used in SMT mode.
TimeBuffer< TimeStruct >::wire robInfoFromIEW
Wire to read information from IEW (for ROB).
void tick()
Ticks the commit stage, which tries to commit instructions.
void setIEWStage(IEW *iew_stage)
Sets the pointer to the IEW stage.
const unsigned renameWidth
Rename width, in instructions.
bool drainPending
Is a drain pending? Commit is looking for an instruction boundary while there are no pending interrup...
const Cycles trapLatency
The latency to handle a trap.
ProbePointArg< DynInstPtr > * ppCommit
Probe Points.
bool wroteToTimeBuffer
Records that commit has written to the time buffer this cycle.
TimeBuffer< IEWStruct > * iewQueue
IEW instruction queue interface.
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the main time buffer pointer, used for backwards communication.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
const Cycles renameToROBDelay
Rename to ROB delay.
std::list< ThreadID > * activeThreads
Pointer to the list of active threads.
void updateStatus()
Updates the overall status of commit with the nextStatus, and tell the CPU if commit is active/inacti...
void squashAfter(ThreadID tid, const DynInstPtr &head_inst)
Handle squashing from instruction with SquashAfter set.
bool commitHead(const DynInstPtr &head_inst, unsigned inst_num)
Tries to commit the head ROB instruction passed in.
void resetHtmStartsStops(ThreadID)
void getInsts()
Gets instructions from rename and inserts them into the ROB.
bool tcSquash[MaxThreads]
Records if a thread has to squash this cycle due to an XC write.
void drainSanityCheck() const
Perform sanity checks after a drain.
void takeOverFrom()
Takes over from another CPU's thread.
void clearStates(ThreadID tid)
Clear all thread-specific states.
void drainResume()
Resumes execution after draining.
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue interface, for ROB.
void drain()
Initializes the draining of commit.
bool trapSquash[MaxThreads]
Records if a thread has to squash this cycle due to a trap.
InstSeqNum youngestSeqNum[MaxThreads]
The sequence number of the youngest valid instruction in the ROB.
InstSeqNum lastCommitedSeqNum[MaxThreads]
The sequence number of the last commited instruction.
CommitStatus _nextStatus
Next commit status, to be set at the end of the cycle.
bool drainImminent
Is a drain imminent? Commit has found an instruction boundary while no interrupts were present or in ...
void commitInsts()
Commits as many instructions as possible.
void markCompletedInsts()
Marks completed instructions using information sent from IEW.
void setRenameMap(UnifiedRenameMap rm_ptr[MaxThreads])
Sets pointer to the commited state rename map.
bool canHandleInterrupts
True if last committed microop can be followed by an interrupt.
TimeBuffer< TimeStruct > * timeBuffer
Time buffer interface.
TimeBuffer< RenameStruct >::wire fromRename
Wire to read information from rename queue.
ThreadID roundRobin()
Returns the thread ID to use based on a round robin policy.
void generateTCEvent(ThreadID tid)
Records that commit needs to initiate a squash due to an external state update through the TC.
std::unique_ptr< PCStateBase > pc[MaxThreads]
The commit PC state of each thread.
void regProbePoints()
Registers probes.
IEW * iewStage
The pointer to the IEW stage.
void setThreads(std::vector< ThreadState * > &threads)
Sets the list of threads.
void updateComInstStats(const DynInstPtr &inst)
Updates commit stats based on this instruction.
ThreadID getCommittingThread()
Gets the thread to commit, based on the SMT policy.
const Cycles iewToCommitDelay
IEW to Commit delay.
bool avoidQuiesceLiveLock
Have we had an interrupt pending and then seen it de-asserted because of a masking change?...
std::list< ThreadID > priority_list
Priority List used for Commit Policy.
void commit()
Handles any squashes that are sent from IEW, and adds instructions to the ROB and tries to commit ins...
UnifiedRenameMap * renameMap[MaxThreads]
Rename map interface.
void squashFromTrap(ThreadID tid)
Handles squashing due to a trap.
bool committedStores[MaxThreads]
Records if there were any stores committed this cycle.
const unsigned commitWidth
Commit width, in instructions.
bool isDrained() const
Has the stage drained?
Fault interrupt
The interrupt fault.
TimeBuffer< FetchStruct >::wire fromFetch
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
bool hasStoresToWB()
Returns if the LSQ has any stores to writeback.
int countInsts()
This is more of a debugging function than anything.
void insertInst(const DynInstPtr &inst)
Function to insert an instruction into the ROB.
unsigned getMaxEntries(ThreadID tid)
Returns the maximum number of entries for a specific thread.
unsigned numFreeEntries()
Returns the number of total free entries in the ROB.
void resetEntries()
Re-adjust ROB partitioning.
void squash(InstSeqNum squash_num, ThreadID tid)
Squashes all instructions younger than the given sequence number for the specific thread.
bool isHeadReady(ThreadID tid)
Is the oldest instruction across all threads ready.
void retireHead(ThreadID tid)
Retires the head instruction, removing it from the ROB.
DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst)
Returns a pointer to the instruction with the given sequence if it is in the ROB.
void drainSanityCheck() const
Perform sanity checks after a drain.
void doSquash(ThreadID tid)
Executes the squash, marking squashed instructions.
const DynInstPtr & readHeadInst(ThreadID tid)
Returns pointer to the head instruction within the ROB.
unsigned getThreadEntries(ThreadID tid)
Returns the number of entries being used by a specific thread.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to the list of active threads.
bool isEmpty() const
Returns if the ROB is empty.
void takeOverFrom()
Takes over another CPU's thread.
bool isDoneSquashing(ThreadID tid) const
Reads the PC of the oldest head instruction.
Unified register rename map for all classes of registers.
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
Derived & ysubnames(const char **names)
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Distribution & init(Counter min, Counter max, Counter bkt)
Set the parameters of this distribution.
std::vector< Info * > stats
Derived & init(size_type _x, size_type _y)
Derived & init(size_type size)
Set this vector to have the given size.
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
void schedule(Event &event, Tick when)
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
#define panic(...)
This implements a cprintf based panic() function.
#define fatal(...)
This implements a cprintf based fatal() function.
ProbeManager * getProbeManager()
Get the probe manager for this object.
static constexpr int MaxThreads
static constexpr int MaxWidth
const FlagsType pdf
Print the percent of the total that this entry represents.
const FlagsType total
Print the total.
const FlagsType dist
Print the distribution.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
int16_t ThreadID
Thread index/ID type.
const ThreadID InvalidThreadID
Tick curTick()
The universal simulation clock.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
constexpr decltype(nullptr) NoFault
statistics::Vector amos
Stat for the total number of committed atomics.
statistics::Vector instsCommitted
Total number of instructions committed.
CommitStats(CPU *cpu, Commit *commit)
statistics::Distribution numCommittedDist
Distribution of the number of committed instructions each cycle.
statistics::Scalar commitNonSpecStalls
Stat for the total number of times commit has had to stall due to a non-speculative instruction reach...
statistics::Scalar commitSquashedInsts
Stat for the total number of squashed instructions discarded by commit.
statistics::Scalar branchMispredicts
Stat for the total number of branch mispredicts that caused a squash.
statistics::Vector2d committedInstType
Committed instructions by instruction type (OpClass)
statistics::Vector integer
Total number of integer instructions.
statistics::Vector vectorInstructions
Total number of vector instructions.
statistics::Vector branches
Total number of committed branches.
statistics::Vector memRefs
Stat for the total number of committed memory references.
statistics::Vector floating
Total number of floating point instructions.
statistics::Vector loads
Stat for the total number of committed loads.
statistics::Vector functionCalls
Total number of function calls.
statistics::Vector opsCommitted
Total number of ops (including micro ops) committed.
statistics::Vector membars
Total number of committed memory barriers.