gem5  v21.2.1.1
commit.cc
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41 
42 #include "cpu/o3/commit.hh"
43 
44 #include <algorithm>
45 #include <set>
46 #include <string>
47 
48 #include "base/compiler.hh"
49 #include "base/loader/symtab.hh"
50 #include "base/logging.hh"
51 #include "config/the_isa.hh"
52 #include "cpu/base.hh"
53 #include "cpu/checker/cpu.hh"
54 #include "cpu/exetrace.hh"
55 #include "cpu/o3/cpu.hh"
56 #include "cpu/o3/dyn_inst.hh"
57 #include "cpu/o3/limits.hh"
58 #include "cpu/o3/thread_state.hh"
59 #include "cpu/timebuf.hh"
60 #include "debug/Activity.hh"
61 #include "debug/Commit.hh"
62 #include "debug/CommitRate.hh"
63 #include "debug/Drain.hh"
64 #include "debug/ExecFaulting.hh"
65 #include "debug/HtmCpu.hh"
66 #include "debug/O3PipeView.hh"
67 #include "params/O3CPU.hh"
68 #include "sim/faults.hh"
69 #include "sim/full_system.hh"
70 
71 namespace gem5
72 {
73 
74 namespace o3
75 {
76 
77 void
79 {
80  // This will get reset by commit if it was switched out at the
81  // time of this event processing.
82  trapSquash[tid] = true;
83 }
84 
85 Commit::Commit(CPU *_cpu, const O3CPUParams &params)
86  : commitPolicy(params.smtCommitPolicy),
87  cpu(_cpu),
88  iewToCommitDelay(params.iewToCommitDelay),
89  commitToIEWDelay(params.commitToIEWDelay),
90  renameToROBDelay(params.renameToROBDelay),
91  fetchToCommitDelay(params.commitToFetchDelay),
92  renameWidth(params.renameWidth),
93  commitWidth(params.commitWidth),
94  numThreads(params.numThreads),
95  drainPending(false),
96  drainImminent(false),
97  trapLatency(params.trapLatency),
98  canHandleInterrupts(true),
99  avoidQuiesceLiveLock(false),
100  stats(_cpu, this)
101 {
102  if (commitWidth > MaxWidth)
103  fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
104  "\tincrease MaxWidth in src/cpu/o3/limits.hh\n",
105  commitWidth, static_cast<int>(MaxWidth));
106 
107  _status = Active;
109 
110  if (commitPolicy == CommitPolicy::RoundRobin) {
111  //Set-Up Priority List
112  for (ThreadID tid = 0; tid < numThreads; tid++) {
113  priority_list.push_back(tid);
114  }
115  }
116 
117  for (ThreadID tid = 0; tid < MaxThreads; tid++) {
118  commitStatus[tid] = Idle;
119  changedROBNumEntries[tid] = false;
120  trapSquash[tid] = false;
121  tcSquash[tid] = false;
122  squashAfterInst[tid] = nullptr;
123  pc[tid].reset(params.isa[0]->newPCState());
124  youngestSeqNum[tid] = 0;
125  lastCommitedSeqNum[tid] = 0;
126  trapInFlight[tid] = false;
127  committedStores[tid] = false;
128  checkEmptyROB[tid] = false;
129  renameMap[tid] = nullptr;
130  htmStarts[tid] = 0;
131  htmStops[tid] = 0;
132  }
133  interrupt = NoFault;
134 }
135 
136 std::string Commit::name() const { return cpu->name() + ".commit"; }
137 
138 void
140 {
142  cpu->getProbeManager(), "Commit");
144  cpu->getProbeManager(), "CommitStall");
146  cpu->getProbeManager(), "Squash");
147 }
148 
150  : statistics::Group(cpu, "commit"),
151  ADD_STAT(commitSquashedInsts, statistics::units::Count::get(),
152  "The number of squashed insts skipped by commit"),
153  ADD_STAT(commitNonSpecStalls, statistics::units::Count::get(),
154  "The number of times commit has been forced to stall to "
155  "communicate backwards"),
156  ADD_STAT(branchMispredicts, statistics::units::Count::get(),
157  "The number of times a branch was mispredicted"),
158  ADD_STAT(numCommittedDist, statistics::units::Count::get(),
159  "Number of insts commited each cycle"),
160  ADD_STAT(instsCommitted, statistics::units::Count::get(),
161  "Number of instructions committed"),
162  ADD_STAT(opsCommitted, statistics::units::Count::get(),
163  "Number of ops (including micro ops) committed"),
164  ADD_STAT(memRefs, statistics::units::Count::get(),
165  "Number of memory references committed"),
166  ADD_STAT(loads, statistics::units::Count::get(), "Number of loads committed"),
167  ADD_STAT(amos, statistics::units::Count::get(),
168  "Number of atomic instructions committed"),
169  ADD_STAT(membars, statistics::units::Count::get(),
170  "Number of memory barriers committed"),
171  ADD_STAT(branches, statistics::units::Count::get(),
172  "Number of branches committed"),
173  ADD_STAT(vectorInstructions, statistics::units::Count::get(),
174  "Number of committed Vector instructions."),
175  ADD_STAT(floating, statistics::units::Count::get(),
176  "Number of committed floating point instructions."),
177  ADD_STAT(integer, statistics::units::Count::get(),
178  "Number of committed integer instructions."),
179  ADD_STAT(functionCalls, statistics::units::Count::get(),
180  "Number of function calls committed."),
181  ADD_STAT(committedInstType, statistics::units::Count::get(),
182  "Class of committed instruction"),
183  ADD_STAT(commitEligibleSamples, statistics::units::Cycle::get(),
184  "number cycles where commit BW limit reached")
185 {
186  using namespace statistics;
187 
191 
193  .init(0,commit->commitWidth,1)
195 
197  .init(cpu->numThreads)
198  .flags(total);
199 
201  .init(cpu->numThreads)
202  .flags(total);
203 
204  memRefs
205  .init(cpu->numThreads)
206  .flags(total);
207 
208  loads
209  .init(cpu->numThreads)
210  .flags(total);
211 
212  amos
213  .init(cpu->numThreads)
214  .flags(total);
215 
216  membars
217  .init(cpu->numThreads)
218  .flags(total);
219 
220  branches
221  .init(cpu->numThreads)
222  .flags(total);
223 
225  .init(cpu->numThreads)
226  .flags(total);
227 
228  floating
229  .init(cpu->numThreads)
230  .flags(total);
231 
232  integer
233  .init(cpu->numThreads)
234  .flags(total);
235 
237  .init(commit->numThreads)
238  .flags(total);
239 
241  .init(commit->numThreads,enums::Num_OpClass)
242  .flags(total | pdf | dist);
243 
244  committedInstType.ysubnames(enums::OpClassStrings);
245 }
246 
247 void
249 {
250  thread = threads;
251 }
252 
253 void
255 {
256  timeBuffer = tb_ptr;
257 
258  // Setup wire to send information back to IEW.
259  toIEW = timeBuffer->getWire(0);
260 
261  // Setup wire to read data from IEW (for the ROB).
263 }
264 
265 void
267 {
268  fetchQueue = fq_ptr;
269 
270  // Setup wire to get instructions from rename (for the ROB).
272 }
273 
274 void
276 {
277  renameQueue = rq_ptr;
278 
279  // Setup wire to get instructions from rename (for the ROB).
281 }
282 
283 void
285 {
286  iewQueue = iq_ptr;
287 
288  // Setup wire to get instructions from IEW.
289  fromIEW = iewQueue->getWire(-iewToCommitDelay);
290 }
291 
292 void
294 {
295  iewStage = iew_stage;
296 }
297 
298 void
300 {
301  activeThreads = at_ptr;
302 }
303 
304 void
306 {
307  for (ThreadID tid = 0; tid < numThreads; tid++)
308  renameMap[tid] = &rm_ptr[tid];
309 }
310 
311 void Commit::setROB(ROB *rob_ptr) { rob = rob_ptr; }
312 
313 void
315 {
317  rob->resetEntries();
318 
319  // Broadcast the number of free entries.
320  for (ThreadID tid = 0; tid < numThreads; tid++) {
321  toIEW->commitInfo[tid].usedROB = true;
322  toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
323  toIEW->commitInfo[tid].emptyROB = true;
324  }
325 
326  // Commit must broadcast the number of free entries it has at the
327  // start of the simulation, so it starts as active.
329 
331 }
332 
333 void
335 {
336  commitStatus[tid] = Idle;
337  changedROBNumEntries[tid] = false;
338  checkEmptyROB[tid] = false;
339  trapInFlight[tid] = false;
340  committedStores[tid] = false;
341  trapSquash[tid] = false;
342  tcSquash[tid] = false;
343  pc[tid].reset(cpu->tcBase(tid)->getIsaPtr()->newPCState());
344  lastCommitedSeqNum[tid] = 0;
345  squashAfterInst[tid] = NULL;
346 }
347 
348 void Commit::drain() { drainPending = true; }
349 
350 void
352 {
353  drainPending = false;
354  drainImminent = false;
355 }
356 
357 void
359 {
360  assert(isDrained());
362 
363  // hardware transactional memory
364  // cannot drain partially through a transaction
365  for (ThreadID tid = 0; tid < numThreads; tid++) {
366  if (executingHtmTransaction(tid)) {
367  panic("cannot drain partially through a HTM transaction");
368  }
369  }
370 }
371 
372 bool
374 {
375  /* Make sure no one is executing microcode. There are two reasons
376  * for this:
377  * - Hardware virtualized CPUs can't switch into the middle of a
378  * microcode sequence.
379  * - The current fetch implementation will most likely get very
380  * confused if it tries to start fetching an instruction that
381  * is executing in the middle of a ucode sequence that changes
382  * address mappings. This can happen on for example x86.
383  */
384  for (ThreadID tid = 0; tid < numThreads; tid++) {
385  if (pc[tid]->microPC() != 0)
386  return false;
387  }
388 
389  /* Make sure that all instructions have finished committing before
390  * declaring the system as drained. We want the pipeline to be
391  * completely empty when we declare the CPU to be drained. This
392  * makes debugging easier since CPU handover and restoring from a
393  * checkpoint with a different CPU should have the same timing.
394  */
395  return rob->isEmpty() &&
396  interrupt == NoFault;
397 }
398 
399 void
401 {
402  _status = Active;
404  for (ThreadID tid = 0; tid < numThreads; tid++) {
405  commitStatus[tid] = Idle;
406  changedROBNumEntries[tid] = false;
407  trapSquash[tid] = false;
408  tcSquash[tid] = false;
409  squashAfterInst[tid] = NULL;
410  }
411  rob->takeOverFrom();
412 }
413 
414 void
416 {
417  std::list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
418  priority_list.end(), tid);
419 
420  if (thread_it != priority_list.end()) {
421  priority_list.erase(thread_it);
422  }
423 }
424 
425 bool
427 {
428  if (tid == InvalidThreadID)
429  return false;
430  else
431  return (htmStarts[tid] > htmStops[tid]);
432 }
433 
434 void
436 {
437  if (tid != InvalidThreadID)
438  {
439  htmStarts[tid] = 0;
440  htmStops[tid] = 0;
441  }
442 }
443 
444 
445 void
447 {
448  // reset ROB changed variable
449  std::list<ThreadID>::iterator threads = activeThreads->begin();
451 
452  while (threads != end) {
453  ThreadID tid = *threads++;
454 
455  changedROBNumEntries[tid] = false;
456 
457  // Also check if any of the threads has a trap pending
458  if (commitStatus[tid] == TrapPending ||
459  commitStatus[tid] == FetchTrapPending) {
461  }
462  }
463 
464  if (_nextStatus == Inactive && _status == Active) {
465  DPRINTF(Activity, "Deactivating stage.\n");
467  } else if (_nextStatus == Active && _status == Inactive) {
468  DPRINTF(Activity, "Activating stage.\n");
470  }
471 
473 }
474 
475 bool
477 {
478  std::list<ThreadID>::iterator threads = activeThreads->begin();
480 
481  while (threads != end) {
482  ThreadID tid = *threads++;
483 
484  if (changedROBNumEntries[tid]) {
485  return true;
486  }
487  }
488 
489  return false;
490 }
491 
492 size_t
494 {
495  return rob->numFreeEntries(tid);
496 }
497 
498 void
500 {
501  DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
502 
504  [this, tid]{ processTrapEvent(tid); },
505  "Trap", true, Event::CPU_Tick_Pri);
506 
507  Cycles latency = std::dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ?
508  cpu->syscallRetryLatency : trapLatency;
509 
510  // hardware transactional memory
511  if (inst_fault != nullptr &&
512  std::dynamic_pointer_cast<GenericHtmFailureFault>(inst_fault)) {
513  // TODO
514  // latency = default abort/restore latency
515  // could also do some kind of exponential back off if desired
516  }
517 
518  cpu->schedule(trap, cpu->clockEdge(latency));
519  trapInFlight[tid] = true;
520  thread[tid]->trapPending = true;
521 }
522 
523 void
525 {
526  assert(!trapInFlight[tid]);
527  DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
528 
529  tcSquash[tid] = true;
530 }
531 
532 void
534 {
535  // If we want to include the squashing instruction in the squash,
536  // then use one older sequence number.
537  // Hopefully this doesn't mess things up. Basically I want to squash
538  // all instructions of this thread.
539  InstSeqNum squashed_inst = rob->isEmpty(tid) ?
540  lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
541 
542  // All younger instructions will be squashed. Set the sequence
543  // number as the youngest instruction in the ROB (0 in this case.
544  // Hopefully nothing breaks.)
546 
547  rob->squash(squashed_inst, tid);
548  changedROBNumEntries[tid] = true;
549 
550  // Send back the sequence number of the squashed instruction.
551  toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
552 
553  // Send back the squash signal to tell stages that they should
554  // squash.
555  toIEW->commitInfo[tid].squash = true;
556 
557  // Send back the rob squashing signal so other stages know that
558  // the ROB is in the process of squashing.
559  toIEW->commitInfo[tid].robSquashing = true;
560 
561  toIEW->commitInfo[tid].mispredictInst = NULL;
562  toIEW->commitInfo[tid].squashInst = NULL;
563 
564  set(toIEW->commitInfo[tid].pc, pc[tid]);
565 }
566 
567 void
569 {
570  squashAll(tid);
571 
572  DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", *pc[tid]);
573 
574  thread[tid]->trapPending = false;
575  thread[tid]->noSquashFromTC = false;
576  trapInFlight[tid] = false;
577 
578  trapSquash[tid] = false;
579 
580  commitStatus[tid] = ROBSquashing;
582 }
583 
584 void
586 {
587  squashAll(tid);
588 
589  DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", *pc[tid]);
590 
591  thread[tid]->noSquashFromTC = false;
592  assert(!thread[tid]->trapPending);
593 
594  commitStatus[tid] = ROBSquashing;
596 
597  tcSquash[tid] = false;
598 }
599 
600 void
602 {
603  DPRINTF(Commit, "Squashing after squash after request, "
604  "restarting at PC %s\n", *pc[tid]);
605 
606  squashAll(tid);
607  // Make sure to inform the fetch stage of which instruction caused
608  // the squash. It'll try to re-fetch an instruction executing in
609  // microcode unless this is set.
610  toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
611  squashAfterInst[tid] = NULL;
612 
613  commitStatus[tid] = ROBSquashing;
615 }
616 
617 void
619 {
620  DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%llu]\n",
621  tid, head_inst->seqNum);
622 
623  assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
625  squashAfterInst[tid] = head_inst;
626 }
627 
628 void
630 {
631  wroteToTimeBuffer = false;
633 
634  if (activeThreads->empty())
635  return;
636 
637  std::list<ThreadID>::iterator threads = activeThreads->begin();
639 
640  // Check if any of the threads are done squashing. Change the
641  // status if they are done.
642  while (threads != end) {
643  ThreadID tid = *threads++;
644 
645  // Clear the bit saying if the thread has committed stores
646  // this cycle.
647  committedStores[tid] = false;
648 
649  if (commitStatus[tid] == ROBSquashing) {
650 
651  if (rob->isDoneSquashing(tid)) {
652  commitStatus[tid] = Running;
653  } else {
654  DPRINTF(Commit,"[tid:%i] Still Squashing, cannot commit any"
655  " insts this cycle.\n", tid);
656  rob->doSquash(tid);
657  toIEW->commitInfo[tid].robSquashing = true;
658  wroteToTimeBuffer = true;
659  }
660  }
661  }
662 
663  commit();
664 
666 
667  threads = activeThreads->begin();
668 
669  while (threads != end) {
670  ThreadID tid = *threads++;
671 
672  if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
673  // The ROB has more instructions it can commit. Its next status
674  // will be active.
676 
677  [[maybe_unused]] const DynInstPtr &inst = rob->readHeadInst(tid);
678 
679  DPRINTF(Commit,"[tid:%i] Instruction [sn:%llu] PC %s is head of"
680  " ROB and ready to commit\n",
681  tid, inst->seqNum, inst->pcState());
682 
683  } else if (!rob->isEmpty(tid)) {
684  const DynInstPtr &inst = rob->readHeadInst(tid);
685 
686  ppCommitStall->notify(inst);
687 
688  DPRINTF(Commit,"[tid:%i] Can't commit, Instruction [sn:%llu] PC "
689  "%s is head of ROB and not ready\n",
690  tid, inst->seqNum, inst->pcState());
691  }
692 
693  DPRINTF(Commit, "[tid:%i] ROB has %d insts & %d free entries.\n",
694  tid, rob->countInsts(tid), rob->numFreeEntries(tid));
695  }
696 
697 
698  if (wroteToTimeBuffer) {
699  DPRINTF(Activity, "Activity This Cycle.\n");
701  }
702 
703  updateStatus();
704 }
705 
706 void
708 {
709  // Verify that we still have an interrupt to handle
710  if (!cpu->checkInterrupts(0)) {
711  DPRINTF(Commit, "Pending interrupt is cleared by requestor before "
712  "it got handled. Restart fetching from the orig path.\n");
713  toIEW->commitInfo[0].clearInterrupt = true;
714  interrupt = NoFault;
715  avoidQuiesceLiveLock = true;
716  return;
717  }
718 
719  // Wait until all in flight instructions are finished before enterring
720  // the interrupt.
721  if (canHandleInterrupts && cpu->instList.empty()) {
722  // Squash or record that I need to squash this cycle if
723  // an interrupt needed to be handled.
724  DPRINTF(Commit, "Interrupt detected.\n");
725 
726  // Clear the interrupt now that it's going to be handled
727  toIEW->commitInfo[0].clearInterrupt = true;
728 
729  assert(!thread[0]->noSquashFromTC);
730  thread[0]->noSquashFromTC = true;
731 
732  if (cpu->checker) {
733  cpu->checker->handlePendingInt();
734  }
735 
736  // CPU will handle interrupt. Note that we ignore the local copy of
737  // interrupt. This is because the local copy may no longer be the
738  // interrupt that the interrupt controller thinks is being handled.
740 
741  thread[0]->noSquashFromTC = false;
742 
744 
745  interrupt = NoFault;
746 
747  // Generate trap squash event.
749 
750  avoidQuiesceLiveLock = false;
751  } else {
752  DPRINTF(Commit, "Interrupt pending: instruction is %sin "
753  "flight, ROB is %sempty\n",
754  canHandleInterrupts ? "not " : "",
755  cpu->instList.empty() ? "" : "not " );
756  }
757 }
758 
759 void
761 {
762  // Don't propagate intterupts if we are currently handling a trap or
763  // in draining and the last observable instruction has been committed.
764  if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
765  tcSquash[0] || drainImminent)
766  return;
767 
768  // Process interrupts if interrupts are enabled, not in PAL
769  // mode, and no other traps or external squashes are currently
770  // pending.
771  // @todo: Allow other threads to handle interrupts.
772 
773  // Get any interrupt that happened
775 
776  // Tell fetch that there is an interrupt pending. This
777  // will make fetch wait until it sees a non PAL-mode PC,
778  // at which point it stops fetching instructions.
779  if (interrupt != NoFault)
780  toIEW->commitInfo[0].interruptPending = true;
781 }
782 
783 void
785 {
786  if (FullSystem) {
787  // Check if we have a interrupt and get read to handle it
788  if (cpu->checkInterrupts(0))
790  }
791 
793  // Check for any possible squashes, handle them first
795  std::list<ThreadID>::iterator threads = activeThreads->begin();
797 
798  int num_squashing_threads = 0;
799 
800  while (threads != end) {
801  ThreadID tid = *threads++;
802 
803  // Not sure which one takes priority. I think if we have
804  // both, that's a bad sign.
805  if (trapSquash[tid]) {
806  assert(!tcSquash[tid]);
807  squashFromTrap(tid);
808 
809  // If the thread is trying to exit (i.e., an exit syscall was
810  // executed), this trapSquash was originated by the exit
811  // syscall earlier. In this case, schedule an exit event in
812  // the next cycle to fully terminate this thread
813  if (cpu->isThreadExiting(tid))
815  } else if (tcSquash[tid]) {
816  assert(commitStatus[tid] != TrapPending);
817  squashFromTC(tid);
818  } else if (commitStatus[tid] == SquashAfterPending) {
819  // A squash from the previous cycle of the commit stage (i.e.,
820  // commitInsts() called squashAfter) is pending. Squash the
821  // thread now.
823  }
824 
825  // Squashed sequence number must be older than youngest valid
826  // instruction in the ROB. This prevents squashes from younger
827  // instructions overriding squashes from older instructions.
828  if (fromIEW->squash[tid] &&
829  commitStatus[tid] != TrapPending &&
830  fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
831 
832  if (fromIEW->mispredictInst[tid]) {
833  DPRINTF(Commit,
834  "[tid:%i] Squashing due to branch mispred "
835  "PC:%#x [sn:%llu]\n",
836  tid,
837  fromIEW->mispredictInst[tid]->pcState().instAddr(),
838  fromIEW->squashedSeqNum[tid]);
839  } else {
840  DPRINTF(Commit,
841  "[tid:%i] Squashing due to order violation [sn:%llu]\n",
842  tid, fromIEW->squashedSeqNum[tid]);
843  }
844 
845  DPRINTF(Commit, "[tid:%i] Redirecting to PC %#x\n",
846  tid, *fromIEW->pc[tid]);
847 
848  commitStatus[tid] = ROBSquashing;
849 
850  // If we want to include the squashing instruction in the squash,
851  // then use one older sequence number.
852  InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
853 
854  if (fromIEW->includeSquashInst[tid]) {
855  squashed_inst--;
856  }
857 
858  // All younger instructions will be squashed. Set the sequence
859  // number as the youngest instruction in the ROB.
860  youngestSeqNum[tid] = squashed_inst;
861 
862  rob->squash(squashed_inst, tid);
863  changedROBNumEntries[tid] = true;
864 
865  toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
866 
867  toIEW->commitInfo[tid].squash = true;
868 
869  // Send back the rob squashing signal so other stages know that
870  // the ROB is in the process of squashing.
871  toIEW->commitInfo[tid].robSquashing = true;
872 
873  toIEW->commitInfo[tid].mispredictInst =
874  fromIEW->mispredictInst[tid];
875  toIEW->commitInfo[tid].branchTaken =
876  fromIEW->branchTaken[tid];
877  toIEW->commitInfo[tid].squashInst =
878  rob->findInst(tid, squashed_inst);
879  if (toIEW->commitInfo[tid].mispredictInst) {
880  if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
881  toIEW->commitInfo[tid].branchTaken = true;
882  }
883  ++stats.branchMispredicts;
884  }
885 
886  set(toIEW->commitInfo[tid].pc, fromIEW->pc[tid]);
887  }
888 
889  if (commitStatus[tid] == ROBSquashing) {
890  num_squashing_threads++;
891  }
892  }
893 
894  // If commit is currently squashing, then it will have activity for the
895  // next cycle. Set its next status as active.
896  if (num_squashing_threads) {
898  }
899 
900  if (num_squashing_threads != numThreads) {
901  // If we're not currently squashing, then get instructions.
902  getInsts();
903 
904  // Try to commit any instructions.
905  commitInsts();
906  }
907 
908  //Check for any activity
909  threads = activeThreads->begin();
910 
911  while (threads != end) {
912  ThreadID tid = *threads++;
913 
914  if (changedROBNumEntries[tid]) {
915  toIEW->commitInfo[tid].usedROB = true;
916  toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
917 
918  wroteToTimeBuffer = true;
919  changedROBNumEntries[tid] = false;
920  if (rob->isEmpty(tid))
921  checkEmptyROB[tid] = true;
922  }
923 
924  // ROB is only considered "empty" for previous stages if: a)
925  // ROB is empty, b) there are no outstanding stores, c) IEW
926  // stage has received any information regarding stores that
927  // committed.
928  // c) is checked by making sure to not consider the ROB empty
929  // on the same cycle as when stores have been committed.
930  // @todo: Make this handle multi-cycle communication between
931  // commit and IEW.
932  if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
933  !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
934  checkEmptyROB[tid] = false;
935  toIEW->commitInfo[tid].usedROB = true;
936  toIEW->commitInfo[tid].emptyROB = true;
937  toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
938  wroteToTimeBuffer = true;
939  }
940 
941  }
942 }
943 
944 void
946 {
948  // Handle commit
949  // Note that commit will be handled prior to putting new
950  // instructions in the ROB so that the ROB only tries to commit
951  // instructions it has in this current cycle, and not instructions
952  // it is writing in during this cycle. Can't commit and squash
953  // things at the same time...
955 
956  DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
957 
958  unsigned num_committed = 0;
959 
960  DynInstPtr head_inst;
961 
962  // Commit as many instructions as possible until the commit bandwidth
963  // limit is reached, or it becomes impossible to commit any more.
964  while (num_committed < commitWidth) {
965  // hardware transactionally memory
966  // If executing within a transaction,
967  // need to handle interrupts specially
968 
969  ThreadID commit_thread = getCommittingThread();
970 
971  // Check for any interrupt that we've already squashed for
972  // and start processing it.
973  if (interrupt != NoFault) {
974  // If inside a transaction, postpone interrupts
975  if (executingHtmTransaction(commit_thread)) {
976  cpu->clearInterrupts(0);
977  toIEW->commitInfo[0].clearInterrupt = true;
978  interrupt = NoFault;
979  avoidQuiesceLiveLock = true;
980  } else {
981  handleInterrupt();
982  }
983  }
984 
985  // ThreadID commit_thread = getCommittingThread();
986 
987  if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
988  break;
989 
990  head_inst = rob->readHeadInst(commit_thread);
991 
992  ThreadID tid = head_inst->threadNumber;
993 
994  assert(tid == commit_thread);
995 
996  DPRINTF(Commit,
997  "Trying to commit head instruction, [tid:%i] [sn:%llu]\n",
998  tid, head_inst->seqNum);
999 
1000  // If the head instruction is squashed, it is ready to retire
1001  // (be removed from the ROB) at any time.
1002  if (head_inst->isSquashed()) {
1003 
1004  DPRINTF(Commit, "Retiring squashed instruction from "
1005  "ROB.\n");
1006 
1007  rob->retireHead(commit_thread);
1008 
1009  ++stats.commitSquashedInsts;
1010  // Notify potential listeners that this instruction is squashed
1011  ppSquash->notify(head_inst);
1012 
1013  // Record that the number of ROB entries has changed.
1014  changedROBNumEntries[tid] = true;
1015  } else {
1016  set(pc[tid], head_inst->pcState());
1017 
1018  // Try to commit the head instruction.
1019  bool commit_success = commitHead(head_inst, num_committed);
1020 
1021  if (commit_success) {
1022  ++num_committed;
1023  stats.committedInstType[tid][head_inst->opClass()]++;
1024  ppCommit->notify(head_inst);
1025 
1026  // hardware transactional memory
1027 
1028  // update nesting depth
1029  if (head_inst->isHtmStart())
1030  htmStarts[tid]++;
1031 
1032  // sanity check
1033  if (head_inst->inHtmTransactionalState()) {
1034  assert(executingHtmTransaction(tid));
1035  } else {
1036  assert(!executingHtmTransaction(tid));
1037  }
1038 
1039  // update nesting depth
1040  if (head_inst->isHtmStop())
1041  htmStops[tid]++;
1042 
1043  changedROBNumEntries[tid] = true;
1044 
1045  // Set the doneSeqNum to the youngest committed instruction.
1046  toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1047 
1048  if (tid == 0)
1049  canHandleInterrupts = !head_inst->isDelayedCommit();
1050 
1051  // at this point store conditionals should either have
1052  // been completed or predicated false
1053  assert(!head_inst->isStoreConditional() ||
1054  head_inst->isCompleted() ||
1055  !head_inst->readPredicate());
1056 
1057  // Updates misc. registers.
1058  head_inst->updateMiscRegs();
1059 
1060  // Check instruction execution if it successfully commits and
1061  // is not carrying a fault.
1062  if (cpu->checker) {
1063  cpu->checker->verify(head_inst);
1064  }
1065 
1066  cpu->traceFunctions(pc[tid]->instAddr());
1067 
1068  head_inst->staticInst->advancePC(*pc[tid]);
1069 
1070  // Keep track of the last sequence number commited
1071  lastCommitedSeqNum[tid] = head_inst->seqNum;
1072 
1073  // If this is an instruction that doesn't play nicely with
1074  // others squash everything and restart fetch
1075  if (head_inst->isSquashAfter())
1076  squashAfter(tid, head_inst);
1077 
1078  if (drainPending) {
1079  if (pc[tid]->microPC() == 0 && interrupt == NoFault &&
1080  !thread[tid]->trapPending) {
1081  // Last architectually committed instruction.
1082  // Squash the pipeline, stall fetch, and use
1083  // drainImminent to disable interrupts
1084  DPRINTF(Drain, "Draining: %i:%s\n", tid, *pc[tid]);
1085  squashAfter(tid, head_inst);
1086  cpu->commitDrained(tid);
1087  drainImminent = true;
1088  }
1089  }
1090 
1091  bool onInstBoundary = !head_inst->isMicroop() ||
1092  head_inst->isLastMicroop() ||
1093  !head_inst->isDelayedCommit();
1094 
1095  if (onInstBoundary) {
1096  int count = 0;
1097  Addr oldpc;
1098  // Make sure we're not currently updating state while
1099  // handling PC events.
1100  assert(!thread[tid]->noSquashFromTC &&
1101  !thread[tid]->trapPending);
1102  do {
1103  oldpc = pc[tid]->instAddr();
1104  thread[tid]->pcEventQueue.service(
1105  oldpc, thread[tid]->getTC());
1106  count++;
1107  } while (oldpc != pc[tid]->instAddr());
1108  if (count > 1) {
1109  DPRINTF(Commit,
1110  "PC skip function event, stopping commit\n");
1111  break;
1112  }
1113  }
1114 
1115  // Check if an instruction just enabled interrupts and we've
1116  // previously had an interrupt pending that was not handled
1117  // because interrupts were subsequently disabled before the
1118  // pipeline reached a place to handle the interrupt. In that
1119  // case squash now to make sure the interrupt is handled.
1120  //
1121  // If we don't do this, we might end up in a live lock
1122  // situation.
1123  if (!interrupt && avoidQuiesceLiveLock &&
1124  onInstBoundary && cpu->checkInterrupts(0))
1125  squashAfter(tid, head_inst);
1126  } else {
1127  DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1128  "[tid:%i] [sn:%llu].\n",
1129  head_inst->pcState(), tid ,head_inst->seqNum);
1130  break;
1131  }
1132  }
1133  }
1134 
1135  DPRINTF(CommitRate, "%i\n", num_committed);
1136  stats.numCommittedDist.sample(num_committed);
1137 
1138  if (num_committed == commitWidth) {
1139  stats.commitEligibleSamples++;
1140  }
1141 }
1142 
1143 bool
1144 Commit::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
1145 {
1146  assert(head_inst);
1147 
1148  ThreadID tid = head_inst->threadNumber;
1149 
1150  // If the instruction is not executed yet, then it will need extra
1151  // handling. Signal backwards that it should be executed.
1152  if (!head_inst->isExecuted()) {
1153  // Make sure we are only trying to commit un-executed instructions we
1154  // think are possible.
1155  assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1156  || head_inst->isReadBarrier() || head_inst->isWriteBarrier()
1157  || head_inst->isAtomic()
1158  || (head_inst->isLoad() && head_inst->strictlyOrdered()));
1159 
1160  DPRINTF(Commit,
1161  "Encountered a barrier or non-speculative "
1162  "instruction [tid:%i] [sn:%llu] "
1163  "at the head of the ROB, PC %s.\n",
1164  tid, head_inst->seqNum, head_inst->pcState());
1165 
1166  if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1167  DPRINTF(Commit,
1168  "[tid:%i] [sn:%llu] "
1169  "Waiting for all stores to writeback.\n",
1170  tid, head_inst->seqNum);
1171  return false;
1172  }
1173 
1174  toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1175 
1176  // Change the instruction so it won't try to commit again until
1177  // it is executed.
1178  head_inst->clearCanCommit();
1179 
1180  if (head_inst->isLoad() && head_inst->strictlyOrdered()) {
1181  DPRINTF(Commit, "[tid:%i] [sn:%llu] "
1182  "Strictly ordered load, PC %s.\n",
1183  tid, head_inst->seqNum, head_inst->pcState());
1184  toIEW->commitInfo[tid].strictlyOrdered = true;
1185  toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1186  } else {
1187  ++stats.commitNonSpecStalls;
1188  }
1189 
1190  return false;
1191  }
1192 
1193  // Check if the instruction caused a fault. If so, trap.
1194  Fault inst_fault = head_inst->getFault();
1195 
1196  // hardware transactional memory
1197  // if a fault occurred within a HTM transaction
1198  // ensure that the transaction aborts
1199  if (inst_fault != NoFault && head_inst->inHtmTransactionalState()) {
1200  // There exists a generic HTM fault common to all ISAs
1201  if (!std::dynamic_pointer_cast<GenericHtmFailureFault>(inst_fault)) {
1202  DPRINTF(HtmCpu, "%s - fault (%s) encountered within transaction"
1203  " - converting to GenericHtmFailureFault\n",
1204  head_inst->staticInst->getName(), inst_fault->name());
1205  inst_fault = std::make_shared<GenericHtmFailureFault>(
1206  head_inst->getHtmTransactionUid(),
1208  }
1209  // If this point is reached and the fault inherits from the HTM fault,
1210  // then there is no need to raise a new fault
1211  }
1212 
1213  // Stores mark themselves as completed.
1214  if (!head_inst->isStore() && inst_fault == NoFault) {
1215  head_inst->setCompleted();
1216  }
1217 
1218  if (inst_fault != NoFault) {
1219  DPRINTF(Commit, "Inst [tid:%i] [sn:%llu] PC %s has a fault\n",
1220  tid, head_inst->seqNum, head_inst->pcState());
1221 
1222  if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1223  DPRINTF(Commit,
1224  "[tid:%i] [sn:%llu] "
1225  "Stores outstanding, fault must wait.\n",
1226  tid, head_inst->seqNum);
1227  return false;
1228  }
1229 
1230  head_inst->setCompleted();
1231 
1232  // If instruction has faulted, let the checker execute it and
1233  // check if it sees the same fault and control flow.
1234  if (cpu->checker) {
1235  // Need to check the instruction before its fault is processed
1236  cpu->checker->verify(head_inst);
1237  }
1238 
1239  assert(!thread[tid]->noSquashFromTC);
1240 
1241  // Mark that we're in state update mode so that the trap's
1242  // execution doesn't generate extra squashes.
1243  thread[tid]->noSquashFromTC = true;
1244 
1245  // Execute the trap. Although it's slightly unrealistic in
1246  // terms of timing (as it doesn't wait for the full timing of
1247  // the trap event to complete before updating state), it's
1248  // needed to update the state as soon as possible. This
1249  // prevents external agents from changing any specific state
1250  // that the trap need.
1251  cpu->trap(inst_fault, tid,
1252  head_inst->notAnInst() ? nullStaticInstPtr :
1253  head_inst->staticInst);
1254 
1255  // Exit state update mode to avoid accidental updating.
1256  thread[tid]->noSquashFromTC = false;
1257 
1258  commitStatus[tid] = TrapPending;
1259 
1260  DPRINTF(Commit,
1261  "[tid:%i] [sn:%llu] Committing instruction with fault\n",
1262  tid, head_inst->seqNum);
1263  if (head_inst->traceData) {
1264  // We ignore ReExecution "faults" here as they are not real
1265  // (architectural) faults but signal flush/replays.
1266  if (debug::ExecFaulting
1267  && dynamic_cast<ReExec*>(inst_fault.get()) == nullptr) {
1268 
1269  head_inst->traceData->setFaulting(true);
1270  head_inst->traceData->setFetchSeq(head_inst->seqNum);
1271  head_inst->traceData->setCPSeq(thread[tid]->numOp);
1272  head_inst->traceData->dump();
1273  }
1274  delete head_inst->traceData;
1275  head_inst->traceData = NULL;
1276  }
1277 
1278  // Generate trap squash event.
1279  generateTrapEvent(tid, inst_fault);
1280  return false;
1281  }
1282 
1283  updateComInstStats(head_inst);
1284 
1285  DPRINTF(Commit,
1286  "[tid:%i] [sn:%llu] Committing instruction with PC %s\n",
1287  tid, head_inst->seqNum, head_inst->pcState());
1288  if (head_inst->traceData) {
1289  head_inst->traceData->setFetchSeq(head_inst->seqNum);
1290  head_inst->traceData->setCPSeq(thread[tid]->numOp);
1291  head_inst->traceData->dump();
1292  delete head_inst->traceData;
1293  head_inst->traceData = NULL;
1294  }
1295  if (head_inst->isReturn()) {
1296  DPRINTF(Commit,
1297  "[tid:%i] [sn:%llu] Return Instruction Committed PC %s \n",
1298  tid, head_inst->seqNum, head_inst->pcState());
1299  }
1300 
1301  // Update the commit rename map
1302  for (int i = 0; i < head_inst->numDestRegs(); i++) {
1303  renameMap[tid]->setEntry(head_inst->flattenedDestIdx(i),
1304  head_inst->renamedDestIdx(i));
1305  }
1306 
1307  // hardware transactional memory
1308  // the HTM UID is purely for correctness and debugging purposes
1309  if (head_inst->isHtmStart())
1310  iewStage->setLastRetiredHtmUid(tid, head_inst->getHtmTransactionUid());
1311 
1312  // Finally clear the head ROB entry.
1313  rob->retireHead(tid);
1314 
1315 #if TRACING_ON
1316  if (debug::O3PipeView) {
1317  head_inst->commitTick = curTick() - head_inst->fetchTick;
1318  }
1319 #endif
1320 
1321  // If this was a store, record it for this cycle.
1322  if (head_inst->isStore() || head_inst->isAtomic())
1323  committedStores[tid] = true;
1324 
1325  // Return true to indicate that we have committed an instruction.
1326  return true;
1327 }
1328 
1329 void
1331 {
1332  DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1333 
1334  // Read any renamed instructions and place them into the ROB.
1335  int insts_to_process = std::min((int)renameWidth, fromRename->size);
1336 
1337  for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1338  const DynInstPtr &inst = fromRename->insts[inst_num];
1339  ThreadID tid = inst->threadNumber;
1340 
1341  if (!inst->isSquashed() &&
1342  commitStatus[tid] != ROBSquashing &&
1343  commitStatus[tid] != TrapPending) {
1344  changedROBNumEntries[tid] = true;
1345 
1346  DPRINTF(Commit, "[tid:%i] [sn:%llu] Inserting PC %s into ROB.\n",
1347  tid, inst->seqNum, inst->pcState());
1348 
1349  rob->insertInst(inst);
1350 
1351  assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1352 
1353  youngestSeqNum[tid] = inst->seqNum;
1354  } else {
1355  DPRINTF(Commit, "[tid:%i] [sn:%llu] "
1356  "Instruction PC %s was squashed, skipping.\n",
1357  tid, inst->seqNum, inst->pcState());
1358  }
1359  }
1360 }
1361 
1362 void
1364 {
1365  // Grab completed insts out of the IEW instruction queue, and mark
1366  // instructions completed within the ROB.
1367  for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
1368  assert(fromIEW->insts[inst_num]);
1369  if (!fromIEW->insts[inst_num]->isSquashed()) {
1370  DPRINTF(Commit, "[tid:%i] Marking PC %s, [sn:%llu] ready "
1371  "within ROB.\n",
1372  fromIEW->insts[inst_num]->threadNumber,
1373  fromIEW->insts[inst_num]->pcState(),
1374  fromIEW->insts[inst_num]->seqNum);
1375 
1376  // Mark the instruction as ready to commit.
1377  fromIEW->insts[inst_num]->setCanCommit();
1378  }
1379  }
1380 }
1381 
1382 void
1384 {
1385  ThreadID tid = inst->threadNumber;
1386 
1387  if (!inst->isMicroop() || inst->isLastMicroop())
1388  stats.instsCommitted[tid]++;
1389  stats.opsCommitted[tid]++;
1390 
1391  // To match the old model, don't count nops and instruction
1392  // prefetches towards the total commit count.
1393  if (!inst->isNop() && !inst->isInstPrefetch()) {
1394  cpu->instDone(tid, inst);
1395  }
1396 
1397  //
1398  // Control Instructions
1399  //
1400  if (inst->isControl())
1401  stats.branches[tid]++;
1402 
1403  //
1404  // Memory references
1405  //
1406  if (inst->isMemRef()) {
1407  stats.memRefs[tid]++;
1408 
1409  if (inst->isLoad()) {
1410  stats.loads[tid]++;
1411  }
1412 
1413  if (inst->isAtomic()) {
1414  stats.amos[tid]++;
1415  }
1416  }
1417 
1418  if (inst->isFullMemBarrier()) {
1419  stats.membars[tid]++;
1420  }
1421 
1422  // Integer Instruction
1423  if (inst->isInteger())
1424  stats.integer[tid]++;
1425 
1426  // Floating Point Instruction
1427  if (inst->isFloating())
1428  stats.floating[tid]++;
1429  // Vector Instruction
1430  if (inst->isVector())
1431  stats.vectorInstructions[tid]++;
1432 
1433  // Function Calls
1434  if (inst->isCall())
1435  stats.functionCalls[tid]++;
1436 
1437 }
1438 
1440 // //
1441 // SMT COMMIT POLICY MAINTAINED HERE //
1442 // //
1444 ThreadID
1446 {
1447  if (numThreads > 1) {
1448  switch (commitPolicy) {
1449  case CommitPolicy::RoundRobin:
1450  return roundRobin();
1451 
1452  case CommitPolicy::OldestReady:
1453  return oldestReady();
1454 
1455  default:
1456  return InvalidThreadID;
1457  }
1458  } else {
1459  assert(!activeThreads->empty());
1460  ThreadID tid = activeThreads->front();
1461 
1462  if (commitStatus[tid] == Running ||
1463  commitStatus[tid] == Idle ||
1464  commitStatus[tid] == FetchTrapPending) {
1465  return tid;
1466  } else {
1467  return InvalidThreadID;
1468  }
1469  }
1470 }
1471 
1472 ThreadID
1474 {
1475  std::list<ThreadID>::iterator pri_iter = priority_list.begin();
1477 
1478  while (pri_iter != end) {
1479  ThreadID tid = *pri_iter;
1480 
1481  if (commitStatus[tid] == Running ||
1482  commitStatus[tid] == Idle ||
1483  commitStatus[tid] == FetchTrapPending) {
1484 
1485  if (rob->isHeadReady(tid)) {
1486  priority_list.erase(pri_iter);
1487  priority_list.push_back(tid);
1488 
1489  return tid;
1490  }
1491  }
1492 
1493  pri_iter++;
1494  }
1495 
1496  return InvalidThreadID;
1497 }
1498 
1499 ThreadID
1501 {
1502  unsigned oldest = 0;
1503  unsigned oldest_seq_num = 0;
1504  bool first = true;
1505 
1506  std::list<ThreadID>::iterator threads = activeThreads->begin();
1508 
1509  while (threads != end) {
1510  ThreadID tid = *threads++;
1511 
1512  if (!rob->isEmpty(tid) &&
1513  (commitStatus[tid] == Running ||
1514  commitStatus[tid] == Idle ||
1515  commitStatus[tid] == FetchTrapPending)) {
1516 
1517  if (rob->isHeadReady(tid)) {
1518 
1519  const DynInstPtr &head_inst = rob->readHeadInst(tid);
1520 
1521  if (first) {
1522  oldest = tid;
1523  oldest_seq_num = head_inst->seqNum;
1524  first = false;
1525  } else if (head_inst->seqNum < oldest_seq_num) {
1526  oldest = tid;
1527  oldest_seq_num = head_inst->seqNum;
1528  }
1529  }
1530  }
1531  }
1532 
1533  if (!first) {
1534  return oldest;
1535  } else {
1536  return InvalidThreadID;
1537  }
1538 }
1539 
1540 } // namespace o3
1541 } // namespace gem5
gem5::o3::Commit::drainPending
bool drainPending
Is a drain pending? Commit is looking for an instruction boundary while there are no pending interrup...
Definition: commit.hh:404
gem5::o3::Commit::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition: commit.cc:299
gem5::o3::Commit::renameMap
UnifiedRenameMap * renameMap[MaxThreads]
Rename map interface.
Definition: commit.hh:446
gem5::o3::Commit::setROB
void setROB(ROB *rob_ptr)
Sets pointer to the ROB.
Definition: commit.cc:311
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::o3::Commit::TrapPending
@ TrapPending
Definition: commit.hh:109
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::o3::Commit::fetchToCommitDelay
const Cycles fetchToCommitDelay
Definition: commit.hh:388
gem5::o3::ROB::doSquash
void doSquash(ThreadID tid)
Executes the squash, marking squashed instructions.
Definition: rob.cc:309
gem5::o3::Commit::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: commit.cc:400
gem5::o3::Commit::CommitStats::instsCommitted
statistics::Vector instsCommitted
Total number of instructions committed.
Definition: commit.hh:483
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::o3::Commit::squashFromTC
void squashFromTC(ThreadID tid)
Handles squashing due to an TC write.
Definition: commit.cc:585
gem5::o3::ROB::squash
void squash(InstSeqNum squash_num, ThreadID tid)
Squashes all instructions younger than the given sequence number for the specific thread.
Definition: rob.cc:473
gem5::o3::Commit::regProbePoints
void regProbePoints()
Registers probes.
Definition: commit.cc:139
gem5::o3::Commit::Commit
Commit(CPU *_cpu, const O3CPUParams &params)
Construct a Commit with the given parameters.
Definition: commit.cc:85
commit.hh
gem5::o3::Commit::CommitStats::loads
statistics::Vector loads
Stat for the total number of committed loads.
Definition: commit.hh:489
gem5::o3::Commit::renameWidth
const unsigned renameWidth
Rename width, in instructions.
Definition: commit.hh:393
gem5::o3::Commit::setIEWQueue
void setIEWQueue(TimeBuffer< IEWStruct > *iq_ptr)
Sets the pointer to the queue coming from IEW.
Definition: commit.cc:284
gem5::o3::Commit::CommitStats::numCommittedDist
statistics::Distribution numCommittedDist
Distribution of the number of committed instructions each cycle.
Definition: commit.hh:480
gem5::o3::Commit::drain
void drain()
Initializes the draining of commit.
Definition: commit.cc:348
gem5::o3::Commit::CommitStats::committedInstType
statistics::Vector2d committedInstType
Committed instructions by instruction type (OpClass)
Definition: commit.hh:505
gem5::o3::Commit::renameQueue
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue interface, for ROB.
Definition: commit.hh:335
gem5::o3::Commit::ppSquash
ProbePointArg< DynInstPtr > * ppSquash
To probe when an instruction is squashed.
Definition: commit.hh:128
gem5::o3::Commit::squashAfterInst
DynInstPtr squashAfterInst[MaxThreads]
Instruction passed to squashAfter().
Definition: commit.hh:374
gem5::statistics::Vector2dBase::init
Derived & init(size_type _x, size_type _y)
Definition: statistics.hh:1174
gem5::o3::Commit::setThreads
void setThreads(std::vector< ThreadState * > &threads)
Sets the list of threads.
Definition: commit.cc:248
gem5::o3::Commit::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
Time buffer interface.
Definition: commit.hh:316
gem5::o3::Commit::fromIEW
TimeBuffer< IEWStruct >::wire fromIEW
Wire to read information from IEW queue.
Definition: commit.hh:332
gem5::o3::CPU::processInterrupts
void processInterrupts(const Fault &interrupt)
Processes any an interrupt fault.
Definition: cpu.cc:828
gem5::o3::CPU::getInterrupts
Fault getInterrupts()
Returns the Fault for any valid interrupt.
Definition: cpu.cc:821
gem5::o3::Commit::priority_list
std::list< ThreadID > priority_list
Priority List used for Commit Policy.
Definition: commit.hh:377
gem5::o3::Commit::wroteToTimeBuffer
bool wroteToTimeBuffer
Records that commit has written to the time buffer this cycle.
Definition: commit.hh:354
gem5::o3::ROB::insertInst
void insertInst(const DynInstPtr &inst)
Function to insert an instruction into the ROB.
Definition: rob.cc:197
gem5::o3::Commit::changedROBEntries
bool changedROBEntries()
Returns if any of the threads have the number of ROB entries changed on this cycle.
Definition: commit.cc:476
gem5::o3::Commit::startupStage
void startupStage()
Initializes stage by sending back the number of free entries.
Definition: commit.cc:314
gem5::o3::ROB::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: rob.cc:134
exetrace.hh
gem5::o3::Commit::setRenameMap
void setRenameMap(UnifiedRenameMap rm_ptr[MaxThreads])
Sets pointer to the commited state rename map.
Definition: commit.cc:305
gem5::o3::Commit::commitInsts
void commitInsts()
Commits as many instructions as possible.
Definition: commit.cc:945
gem5::o3::Commit::ppCommit
ProbePointArg< DynInstPtr > * ppCommit
Probe Points.
Definition: commit.hh:125
gem5::o3::ROB::isDoneSquashing
bool isDoneSquashing(ThreadID tid) const
Reads the PC of the oldest head instruction.
Definition: rob.hh:250
std::vector
STL vector class.
Definition: stl.hh:37
dyn_inst.hh
gem5::o3::CPU::instList
std::list< DynInstPtr > instList
List of all the instructions in flight.
Definition: cpu.hh:435
gem5::o3::Commit::FetchTrapPending
@ FetchTrapPending
Definition: commit.hh:110
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
faults.hh
gem5::o3::Commit::squashFromSquashAfter
void squashFromSquashAfter(ThreadID tid)
Handles a squash from a squashAfter() request.
Definition: commit.cc:601
gem5::o3::ROB::numFreeEntries
unsigned numFreeEntries()
Returns the number of total free entries in the ROB.
Definition: rob.cc:297
gem5::o3::Commit::setRenameQueue
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets the pointer to the queue coming from rename.
Definition: commit.cc:275
gem5::o3::Commit::committedStores
bool committedStores[MaxThreads]
Records if there were any stores committed this cycle.
Definition: commit.hh:436
gem5::o3::Commit::generateTrapEvent
void generateTrapEvent(ThreadID tid, Fault inst_fault)
Generates an event to schedule a squash due to a trap.
Definition: commit.cc:499
gem5::o3::Commit::deactivateThread
void deactivateThread(ThreadID tid)
Deschedules a thread from scheduling.
Definition: commit.cc:415
gem5::o3::ROB::resetEntries
void resetEntries()
Re-adjust ROB partitioning.
Definition: rob.cc:148
gem5::statistics::dist
const FlagsType dist
Print the distribution.
Definition: info.hh:66
gem5::RefCountingPtr< DynInst >
gem5::TimeBuffer
Definition: timebuf.hh:40
gem5::o3::Commit::numROBFreeEntries
size_t numROBFreeEntries(ThreadID tid)
Returns the number of free ROB entries for a specific thread.
Definition: commit.cc:493
gem5::o3::CPU::checker
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
Definition: cpu.hh:578
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::Commit::htmStarts
int htmStarts[MaxThreads]
Definition: commit.hh:461
gem5::o3::ROB::getMaxEntries
unsigned getMaxEntries(ThreadID tid)
Returns the maximum number of entries for a specific thread.
Definition: rob.hh:179
gem5::o3::CPU::deactivateStage
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
Definition: cpu.hh:550
gem5::HtmFailureFaultCause::EXCEPTION
@ EXCEPTION
gem5::o3::Commit::name
std::string name() const
Returns the name of the Commit.
Definition: commit.cc:136
gem5::o3::Commit::CommitStats::branchMispredicts
statistics::Scalar branchMispredicts
Stat for the total number of branch mispredicts that caused a squash.
Definition: commit.hh:478
gem5::o3::Commit::iewStage
IEW * iewStage
The pointer to the IEW stage.
Definition: commit.hh:164
gem5::statistics::pdf
const FlagsType pdf
Print the percent of the total that this entry represents.
Definition: info.hh:62
timebuf.hh
gem5::o3::Commit::activeThreads
std::list< ThreadID > * activeThreads
Pointer to the list of active threads.
Definition: commit.hh:443
gem5::o3::Commit::changedROBNumEntries
bool changedROBNumEntries[MaxThreads]
Records if the number of ROB entries has changed this cycle.
Definition: commit.hh:359
gem5::o3::Commit::iewQueue
TimeBuffer< IEWStruct > * iewQueue
IEW instruction queue interface.
Definition: commit.hh:329
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::o3::Commit::generateTCEvent
void generateTCEvent(ThreadID tid)
Records that commit needs to initiate a squash due to an external state update through the TC.
Definition: commit.cc:524
gem5::o3::Commit::renameToROBDelay
const Cycles renameToROBDelay
Rename to ROB delay.
Definition: commit.hh:386
gem5::o3::Commit::squashAll
void squashAll(ThreadID tid)
Squashes all in flight instructions.
Definition: commit.cc:533
gem5::o3::Commit::CommitStats::floating
statistics::Vector floating
Total number of floating point instructions.
Definition: commit.hh:499
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::statistics::Distribution::init
Distribution & init(Counter min, Counter max, Counter bkt)
Set the parameters of this distribution.
Definition: statistics.hh:2113
gem5::o3::Commit
Commit handles single threaded and SMT commit.
Definition: commit.hh:91
gem5::o3::Commit::propagateInterrupt
void propagateInterrupt()
Get fetch redirecting so we can handle an interrupt.
Definition: commit.cc:760
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::BaseISA::newPCState
virtual PCStateBase * newPCState(Addr new_inst_addr=0) const =0
gem5::o3::Commit::Running
@ Running
Definition: commit.hh:106
gem5::o3::Commit::processTrapEvent
void processTrapEvent(ThreadID tid)
Mark the thread as processing a trap.
Definition: commit.cc:78
gem5::o3::Commit::isDrained
bool isDrained() const
Has the stage drained?
Definition: commit.cc:373
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::o3::Commit::rob
ROB * rob
ROB interface.
Definition: commit.hh:342
gem5::o3::Commit::commitStatus
ThreadStatus commitStatus[MaxThreads]
Per-thread status.
Definition: commit.hh:120
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::o3::Commit::roundRobin
ThreadID roundRobin()
Returns the thread ID to use based on a round robin policy.
Definition: commit.cc:1473
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::o3::Commit::Active
@ Active
Definition: commit.hh:99
gem5::o3::Commit::getInsts
void getInsts()
Gets instructions from rename and inserts them into the ROB.
Definition: commit.cc:1330
gem5::o3::ROB::readHeadInst
const DynInstPtr & readHeadInst(ThreadID tid)
Returns pointer to the head instruction within the ROB.
Definition: rob.cc:502
gem5::o3::Commit::avoidQuiesceLiveLock
bool avoidQuiesceLiveLock
Have we had an interrupt pending and then seen it de-asserted because of a masking change?...
Definition: commit.hh:455
gem5::o3::Commit::htmStops
int htmStops[MaxThreads]
Definition: commit.hh:462
gem5::o3::Commit::ROBSquashing
@ ROBSquashing
Definition: commit.hh:108
gem5::o3::CPU::scheduleThreadExitEvent
void scheduleThreadExitEvent(ThreadID tid)
If a thread is trying to exit and its corresponding trap event has been completed,...
Definition: cpu.cc:1600
gem5::o3::CPU::CommitIdx
@ CommitIdx
Definition: cpu.hh:511
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
cpu.hh
gem5::o3::Commit::pc
std::unique_ptr< PCStateBase > pc[MaxThreads]
The commit PC state of each thread.
Definition: commit.hh:424
gem5::o3::Commit::commitHead
bool commitHead(const DynInstPtr &head_inst, unsigned inst_num)
Tries to commit the head ROB instruction passed in.
Definition: commit.cc:1144
gem5::o3::CPU::activateStage
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
Definition: cpu.hh:543
gem5::o3::Commit::toIEW
TimeBuffer< TimeStruct >::wire toIEW
Wire to write information heading to previous stages.
Definition: commit.hh:319
gem5::o3::Commit::resetHtmStartsStops
void resetHtmStartsStops(ThreadID)
Definition: commit.cc:435
gem5::ReExec
Definition: faults.hh:92
gem5::o3::CPU::tcBase
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
Definition: cpu.hh:566
gem5::o3::Commit::squashAfter
void squashAfter(ThreadID tid, const DynInstPtr &head_inst)
Handle squashing from instruction with SquashAfter set.
Definition: commit.cc:618
gem5::o3::Commit::oldestReady
ThreadID oldestReady()
Returns the thread ID to use based on an oldest instruction policy.
Definition: commit.cc:1500
gem5::o3::ROB::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to the list of active threads.
Definition: rob.cc:127
gem5::o3::Commit::CommitStats::commitSquashedInsts
statistics::Scalar commitSquashedInsts
Stat for the total number of squashed instructions discarded by commit.
Definition: commit.hh:470
gem5::o3::Commit::commitWidth
const unsigned commitWidth
Commit width, in instructions.
Definition: commit.hh:396
gem5::o3::Commit::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: commit.cc:334
thread_state.hh
gem5::InvalidThreadID
const ThreadID InvalidThreadID
Definition: types.hh:243
gem5::o3::MaxWidth
static constexpr int MaxWidth
Definition: limits.hh:37
gem5::o3::Commit::thread
std::vector< ThreadState * > thread
Vector of all of the threads.
Definition: commit.hh:349
compiler.hh
gem5::o3::Commit::cpu
CPU * cpu
Pointer to O3CPU.
Definition: commit.hh:346
gem5::o3::ROB::isHeadReady
bool isHeadReady(ThreadID tid)
Is the oldest instruction across all threads ready.
Definition: rob.cc:268
gem5::o3::Commit::checkEmptyROB
bool checkEmptyROB[MaxThreads]
Records if commit should check if the ROB is truly empty (see commit_impl.hh).
Definition: commit.hh:440
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::Commit::CommitStats::integer
statistics::Vector integer
Total number of integer instructions.
Definition: commit.hh:501
gem5::o3::Commit::fromFetch
TimeBuffer< FetchStruct >::wire fromFetch
Definition: commit.hh:326
gem5::o3::Commit::CommitStats::vectorInstructions
statistics::Vector vectorInstructions
Total number of vector instructions.
Definition: commit.hh:497
gem5::o3::Commit::updateComInstStats
void updateComInstStats(const DynInstPtr &inst)
Updates commit stats based on this instruction.
Definition: commit.cc:1383
full_system.hh
gem5::o3::Commit::getCommittingThread
ThreadID getCommittingThread()
Gets the thread to commit, based on the SMT policy.
Definition: commit.cc:1445
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::o3::Commit::commit
void commit()
Handles any squashes that are sent from IEW, and adds instructions to the ROB and tries to commit ins...
Definition: commit.cc:784
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::o3::ROB::getThreadEntries
unsigned getThreadEntries(ThreadID tid)
Returns the number of entries being used by a specific thread.
Definition: rob.hh:183
gem5::o3::IEW::setLastRetiredHtmUid
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
Definition: iew.hh:234
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::CPU::activityThisCycle
void activityThisCycle()
Records that there was time buffer activity this cycle.
Definition: cpu.hh:539
gem5::o3::Commit::CommitStats::amos
statistics::Vector amos
Stat for the total number of committed atomics.
Definition: commit.hh:491
gem5::o3::Commit::drainResume
void drainResume()
Resumes execution after draining.
Definition: commit.cc:351
gem5::o3::ROB::findInst
DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst)
Returns a pointer to the instruction with the given sequence if it is in the ROB.
Definition: rob.cc:534
gem5::o3::Commit::executingHtmTransaction
bool executingHtmTransaction(ThreadID) const
Is the CPU currently processing a HTM transaction?
Definition: commit.cc:426
base.hh
gem5::statistics::DataWrap::prereq
Derived & prereq(const Stat &prereq)
Set the prerequisite stat and marks this stat to print at the end of simulation.
Definition: statistics.hh:372
gem5::o3::CPU::commitDrained
void commitDrained(ThreadID tid)
Commit has reached a safe point to drain a thread.
Definition: cpu.cc:988
gem5::o3::Commit::SquashAfterPending
@ SquashAfterPending
Definition: commit.hh:111
gem5::o3::Commit::Idle
@ Idle
Definition: commit.hh:107
gem5::o3::CPU::trap
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
Definition: cpu.cc:844
gem5::o3::Commit::interrupt
Fault interrupt
The interrupt fault.
Definition: commit.hh:419
gem5::o3::Commit::lastCommitedSeqNum
InstSeqNum lastCommitedSeqNum[MaxThreads]
The sequence number of the last commited instruction.
Definition: commit.hh:430
gem5::o3::ROB::isEmpty
bool isEmpty() const
Returns if the ROB is empty.
Definition: rob.hh:195
gem5::o3::Commit::setFetchQueue
void setFetchQueue(TimeBuffer< FetchStruct > *fq_ptr)
Definition: commit.cc:266
gem5::o3::Commit::trapSquash
bool trapSquash[MaxThreads]
Records if a thread has to squash this cycle due to a trap.
Definition: commit.hh:362
gem5::o3::CPU::isThreadExiting
bool isThreadExiting(ThreadID tid) const
Is the thread trying to exit?
Definition: cpu.cc:1594
gem5::o3::Commit::commitPolicy
CommitPolicy commitPolicy
Commit policy used in SMT mode.
Definition: commit.hh:122
gem5::o3::Commit::trapInFlight
bool trapInFlight[MaxThreads]
Records if there is a trap currently in flight.
Definition: commit.hh:433
gem5::o3::Commit::_status
CommitStatus _status
Overall commit status.
Definition: commit.hh:116
logging.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::Commit::CommitStats::memRefs
statistics::Vector memRefs
Stat for the total number of committed memory references.
Definition: commit.hh:487
gem5::o3::Commit::_nextStatus
CommitStatus _nextStatus
Next commit status, to be set at the end of the cycle.
Definition: commit.hh:118
gem5::statistics::Group::stats
std::vector< Info * > stats
Definition: group.hh:221
gem5::statistics::DataWrapVec2d::ysubnames
Derived & ysubnames(const char **names)
Definition: statistics.hh:478
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::Commit::CommitStats::opsCommitted
statistics::Vector opsCommitted
Total number of ops (including micro ops) committed.
Definition: commit.hh:485
gem5::o3::ROB::retireHead
void retireHead(ThreadID tid)
Retires the head instruction, removing it from the ROB.
Definition: rob.cc:234
gem5::o3::Commit::CommitStats::CommitStats
CommitStats(CPU *cpu, Commit *commit)
Definition: commit.cc:149
gem5::o3::Commit::CommitStats::commitNonSpecStalls
statistics::Scalar commitNonSpecStalls
Stat for the total number of times commit has had to stall due to a non-speculative instruction reach...
Definition: commit.hh:474
gem5::o3::Commit::tick
void tick()
Ticks the commit stage, which tries to commit instructions.
Definition: commit.cc:629
gem5::o3::Commit::Inactive
@ Inactive
Definition: commit.hh:100
symtab.hh
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:358
gem5::o3::Commit::ppCommitStall
ProbePointArg< DynInstPtr > * ppCommitStall
Definition: commit.hh:126
cpu.hh
std::list< ThreadID >
gem5::EventBase::CPU_Tick_Pri
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:204
gem5::o3::Commit::youngestSeqNum
InstSeqNum youngestSeqNum[MaxThreads]
The sequence number of the youngest valid instruction in the ROB.
Definition: commit.hh:427
gem5::o3::Commit::CommitStats::functionCalls
statistics::Vector functionCalls
Total number of function calls.
Definition: commit.hh:503
gem5::o3::IEW::hasStoresToWB
bool hasStoresToWB()
Returns if the LSQ has any stores to writeback.
Definition: iew.hh:221
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::o3::ROB::countInsts
int countInsts()
This is more of a debugging function than anything.
Definition: rob.cc:180
gem5::o3::Commit::numThreads
const ThreadID numThreads
Number of Active Threads.
Definition: commit.hh:399
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
limits.hh
gem5::statistics::VectorBase::init
Derived & init(size_type size)
Set this vector to have the given size.
Definition: statistics.hh:1040
gem5::o3::Commit::markCompletedInsts
void markCompletedInsts()
Marks completed instructions using information sent from IEW.
Definition: commit.cc:1363
gem5::o3::Commit::drainImminent
bool drainImminent
Is a drain imminent? Commit has found an instruction boundary while no interrupts were present or in ...
Definition: commit.hh:411
gem5::o3::Commit::updateStatus
void updateStatus()
Updates the overall status of commit with the nextStatus, and tell the CPU if commit is active/inacti...
Definition: commit.cc:446
gem5::o3::ROB
ROB class.
Definition: rob.hh:72
gem5::o3::Commit::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the main time buffer pointer, used for backwards communication.
Definition: commit.cc:254
gem5::o3::Commit::squashFromTrap
void squashFromTrap(ThreadID tid)
Handles squashing due to a trap.
Definition: commit.cc:568
gem5::o3::Commit::trapLatency
const Cycles trapLatency
The latency to handle a trap.
Definition: commit.hh:416
gem5::o3::Commit::canHandleInterrupts
bool canHandleInterrupts
True if last committed microop can be followed by an interrupt.
Definition: commit.hh:449
gem5::o3::Commit::handleInterrupt
void handleInterrupt()
Handles processing an interrupt.
Definition: commit.cc:707
gem5::o3::Commit::setIEWStage
void setIEWStage(IEW *iew_stage)
Sets the pointer to the IEW stage.
Definition: commit.cc:293
gem5::o3::Commit::fromRename
TimeBuffer< RenameStruct >::wire fromRename
Wire to read information from rename queue.
Definition: commit.hh:338
gem5::o3::Commit::CommitStats::branches
statistics::Vector branches
Total number of committed branches.
Definition: commit.hh:495
gem5::o3::Commit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: commit.cc:358
gem5::o3::CPU::instDone
void instDone(ThreadID tid, const DynInstPtr &inst)
Function to tell the CPU that an instruction has completed.
Definition: cpu.cc:1338
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::ROB::takeOverFrom
void takeOverFrom()
Takes over another CPU's thread.
Definition: rob.cc:142
gem5::o3::Commit::CommitStats::membars
statistics::Vector membars
Total number of committed memory barriers.
Definition: commit.hh:493
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::o3::UnifiedRenameMap::setEntry
void setEntry(const RegId &arch_reg, PhysRegIdPtr phys_reg)
Update rename map with a specific mapping.
Definition: rename_map.hh:302
gem5::o3::UnifiedRenameMap
Unified register rename map for all classes of registers.
Definition: rename_map.hh:173
gem5::o3::Commit::iewToCommitDelay
const Cycles iewToCommitDelay
IEW to Commit delay.
Definition: commit.hh:380
gem5::o3::Commit::robInfoFromIEW
TimeBuffer< TimeStruct >::wire robInfoFromIEW
Wire to read information from IEW (for ROB).
Definition: commit.hh:322
gem5::o3::Commit::fetchQueue
TimeBuffer< FetchStruct > * fetchQueue
Definition: commit.hh:324
gem5::o3::Commit::tcSquash
bool tcSquash[MaxThreads]
Records if a thread has to squash this cycle due to an XC write.
Definition: commit.hh:365

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