gem5 v24.1.0.1
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#include <bop.hh>
Classes | |
struct | DelayQueueEntry |
In a first implementation of the BO prefetcher, both banks of the RR were written simultaneously when a prefetched line is inserted into the cache. More... | |
Public Member Functions | |
BOP (const BOPPrefetcherParams &p) | |
~BOP ()=default | |
void | calculatePrefetch (const PrefetchInfo &pfi, std::vector< AddrPriority > &addresses, const CacheAccessor &cache) override |
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Queued (const QueuedPrefetcherParams &p) | |
virtual | ~Queued () |
void | notify (const CacheAccessProbeArg &acc, const PrefetchInfo &pfi) override |
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters.) | |
void | insert (const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority, const CacheAccessor &cache) |
PacketPtr | getPacket () override |
Tick | nextPrefetchReadyTime () const override |
void | printQueue (const std::list< DeferredPacket > &queue) const |
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Base (const BasePrefetcherParams &p) | |
virtual | ~Base ()=default |
virtual void | setParentInfo (System *sys, ProbeManager *pm, unsigned blk_size) |
virtual void | notifyEvict (const EvictionInfo &info) |
Notify prefetcher of cache eviction. | |
void | prefetchUnused () |
void | incrDemandMhsrMisses () |
void | pfHitInCache () |
void | pfHitInMSHR () |
void | pfHitInWB () |
void | regProbeListeners () override |
Register probe points for this object. | |
void | probeNotify (const CacheAccessProbeArg &acc, bool miss) |
Process a notification event from the ProbeListener. | |
void | addEventProbe (SimObject *obj, const char *name) |
Add a SimObject and a probe name to listen events from. | |
void | addMMU (BaseMMU *mmu) |
Add a BaseMMU object to be used whenever a translation is needed. | |
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ClockedObject (const ClockedObjectParams &p) | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
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const Params & | params () const |
SimObject (const Params &p) | |
virtual | ~SimObject () |
virtual void | init () |
init() is called after all C++ SimObjects have been created and all ports are connected. | |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. | |
virtual void | regProbePoints () |
Register probe points for this object. | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. | |
virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
Get a port with a given name and index. | |
virtual void | startup () |
startup() is the final initialization call before simulation. | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
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EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. | |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
Event manger manages events in the event queue. | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
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Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
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DrainState | drainState () const |
Return the current drain state of an object. | |
virtual void | notifyFork () |
Notify a child process of a fork. | |
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Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. | |
virtual void | resetStats () |
Callback to reset stats. | |
virtual void | preDumpStats () |
Callback before stats are dumped. | |
void | addStat (statistics::Info *info) |
Register a stat with this group. | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. | |
void | mergeStatGroup (Group *block) |
Merge the contents (stats & children) of a block to this block. | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
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Named (const std::string &name_) | |
virtual | ~Named ()=default |
virtual std::string | name () const |
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void | updateClockPeriod () |
Update the tick to the current tick. | |
Tick | clockEdge (Cycles cycles=Cycles(0)) const |
Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. | |
Cycles | curCycle () const |
Determine the current cycle, corresponding to a tick aligned to a clock edge. | |
Tick | nextCycle () const |
Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. | |
uint64_t | frequency () const |
Tick | clockPeriod () const |
double | voltage () const |
Cycles | ticksToCycles (Tick t) const |
Tick | cyclesToTicks (Cycles c) const |
Public Attributes | |
unsigned int | degree |
The prefetch degree, i.e. | |
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PowerState * | powerState |
Private Types | |
enum | RRWay { Left , Right } |
typedef std::pair< int16_t, uint8_t > | OffsetListEntry |
Structure to save the offset and the score. | |
Private Member Functions | |
void | delayQueueEventWrapper () |
Event to handle the delay queue processing. | |
unsigned int | index (Addr addr, unsigned int way) const |
Generate a hash for the specified address to index the RR table. | |
void | insertIntoRR (Addr addr, Addr addr_tag, unsigned int way) |
Insert the specified address into the RR table. | |
void | insertIntoDelayQueue (Addr addr) |
Insert the specified address into the delay queue. | |
void | resetScores () |
Reset all the scores from the offset list. | |
Addr | tag (Addr addr) const |
Generate the tag for the specified address based on the tag bits and the block size. | |
bool | testRR (Addr) const |
Test if @X-O is hitting in the RR table to update the offset score. | |
void | bestOffsetLearning (Addr) |
Learning phase of the BOP. | |
void | notifyFill (const CacheAccessProbeArg &arg) override |
Update the RR right table after a prefetch fill. | |
Private Attributes | |
const unsigned int | scoreMax |
Learning phase parameters. | |
const unsigned int | roundMax |
const unsigned int | badScore |
const unsigned int | rrEntries |
Recent requests table parameteres. | |
const unsigned int | tagMask |
const bool | delayQueueEnabled |
Delay queue parameters. | |
const unsigned int | delayQueueSize |
const unsigned int | delayTicks |
std::vector< Addr > | rrLeft |
std::vector< Addr > | rrRight |
std::vector< OffsetListEntry > | offsetsList |
std::deque< DelayQueueEntry > | delayQueue |
EventFunctionWrapper | delayQueueEvent |
bool | issuePrefetchRequests |
Hardware prefetcher enabled. | |
Addr | bestOffset |
Current best offset to issue prefetches. | |
Addr | phaseBestOffset |
Current best offset found in the learning phase. | |
std::vector< OffsetListEntry >::iterator | offsetsListIterator |
Current test offset index. | |
unsigned int | bestScore |
Max score found so far. | |
unsigned int | round |
Current round. | |
Additional Inherited Members | |
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using | AddrPriority = std::pair< Addr, int32_t > |
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using | Params = ClockedObjectParams |
Parameters of ClockedObject. | |
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typedef SimObjectParams | Params |
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static void | serializeAll (const std::string &cpt_dir) |
Create a checkpoint by serializing all SimObjects in the system. | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. | |
static void | setSimObjectResolver (SimObjectResolver *resolver) |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
static SimObjectResolver * | getSimObjectResolver () |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
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static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. | |
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using | const_iterator = std::list< DeferredPacket >::const_iterator |
using | iterator = std::list< DeferredPacket >::iterator |
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bool | observeAccess (const PacketPtr &pkt, bool miss, bool prefetched) const |
Determine if this access should be observed. | |
bool | samePage (Addr a, Addr b) const |
Determine if addresses are on the same page. | |
Addr | blockAddress (Addr a) const |
Determine the address of the block in which a lays. | |
Addr | blockIndex (Addr a) const |
Determine the address of a at block granularity. | |
Addr | pageAddress (Addr a) const |
Determine the address of the page in which a lays. | |
Addr | pageOffset (Addr a) const |
Determine the page-offset of a | |
Addr | pageIthBlockAddress (Addr page, uint32_t i) const |
Build the address of the i-th block inside the page. | |
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Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. | |
void | signalDrainDone () const |
Signal that an object is drained. | |
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Clocked (ClockDomain &clk_domain) | |
Create a clocked object and set the clock domain based on the parameters. | |
Clocked (Clocked &)=delete | |
Clocked & | operator= (Clocked &)=delete |
virtual | ~Clocked () |
Virtual destructor due to inheritance. | |
void | resetClock () const |
Reset the object's clock using the current global tick value. | |
virtual void | clockPeriodUpdated () |
A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. | |
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std::list< DeferredPacket > | pfq |
std::list< DeferredPacket > | pfqMissingTranslation |
const unsigned | queueSize |
Maximum size of the prefetch queue. | |
const unsigned | missingTranslationQueueSize |
Maximum size of the queue holding prefetch requests with missing address translations. | |
const Cycles | latency |
Cycles after generation when a prefetch can first be issued. | |
const bool | queueSquash |
Squash queued prefetch if demand access observed. | |
const bool | queueFilter |
Filter prefetches if already queued. | |
const bool | cacheSnoop |
Snoop the cache before generating prefetch (cheating basically) | |
const bool | tagPrefetch |
Tag prefetch with PC of generating access? | |
const unsigned int | throttleControlPct |
Percentage of requests that can be throttled. | |
gem5::prefetch::Queued::QueuedStats | statsQueued |
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System * | system |
Pointer to the parent system. | |
ProbeManager * | probeManager |
Pointer to the parent cache's probe manager. | |
unsigned | blkSize |
The block size of the parent cache. | |
unsigned | lBlkSize |
log_2(block size of the parent cache). | |
const bool | onMiss |
Only consult prefetcher on cache misses? | |
const bool | onRead |
Consult prefetcher on reads? | |
const bool | onWrite |
Consult prefetcher on reads? | |
const bool | onData |
Consult prefetcher on data accesses? | |
const bool | onInst |
Consult prefetcher on instruction accesses? | |
const RequestorID | requestorId |
Request id for prefetches. | |
const Addr | pageBytes |
const bool | prefetchOnAccess |
Prefetch on every access, not just misses. | |
const bool | prefetchOnPfHit |
Prefetch on hit on prefetched lines. | |
const bool | useVirtualAddresses |
Use Virtual Addresses for prefetching. | |
gem5::prefetch::Base::StatGroup | prefetchStats |
uint64_t | issuedPrefetches |
Total prefetches issued. | |
uint64_t | usefulPrefetches |
Total prefetches that has been useful. | |
BaseMMU * | mmu |
Registered mmu for address translations. | |
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const SimObjectParams & | _params |
Cached copy of the object parameters. | |
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EventQueue * | eventq |
A pointer to this object's event queue. | |
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gem5::prefetch::BOP::BOP | ( | const BOPPrefetcherParams & | p | ) |
Definition at line 40 of file bop.cc.
References delayQueueEventWrapper().
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Learning phase of the BOP.
Update the intermediate values of the round and update the best offset if found
Definition at line 226 of file bop.cc.
References badScore, bestOffset, bestScore, DPRINTF, issuePrefetchRequests, gem5::prefetch::Base::lBlkSize, offsetsList, offsetsListIterator, phaseBestOffset, resetScores(), round, roundMax, scoreMax, tag(), and testRR().
Referenced by calculatePrefetch().
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Implements gem5::prefetch::Queued.
Definition at line 286 of file bop.cc.
References gem5::X86ISA::addr, bestOffset, bestOffsetLearning(), degree, delayQueueEnabled, DPRINTF, gem5::prefetch::Base::PrefetchInfo::getAddr(), gem5::ArmISA::i, insertIntoDelayQueue(), insertIntoRR(), issuePrefetchRequests, gem5::prefetch::Base::lBlkSize, Left, and tag().
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Event to handle the delay queue processing.
Definition at line 108 of file bop.cc.
References gem5::curTick(), delayQueue, delayQueueEvent, insertIntoRR(), Left, gem5::EventManager::schedule(), and tag().
Referenced by BOP().
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Generate a hash for the specified address to index the RR table.
addr | address to hash |
way | RR table to which is addressed (left/right) |
Definition at line 126 of file bop.cc.
References gem5::X86ISA::addr, gem5::floorLog2(), gem5::prefetch::Base::lBlkSize, and rrEntries.
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Insert the specified address into the delay queue.
This will trigger an event after the delay cycles pass
addr | address to insert into the delay queue |
Definition at line 174 of file bop.cc.
References gem5::curTick(), delayQueue, delayQueueEvent, delayQueueSize, delayTicks, gem5::EventManager::schedule(), gem5::Event::scheduled(), and gem5::RiscvISA::x.
Referenced by calculatePrefetch().
Insert the specified address into the RR table.
addr | address to insert |
addr_tag | The tag to insert in the RR table |
way | RR table to which the address will be inserted |
Definition at line 161 of file bop.cc.
References gem5::X86ISA::addr, gem5::MipsISA::index, Left, Right, rrLeft, rrRight, and tag().
Referenced by calculatePrefetch(), delayQueueEventWrapper(), and notifyFill().
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Update the RR right table after a prefetch fill.
Reimplemented from gem5::prefetch::Base.
Definition at line 315 of file bop.cc.
References gem5::X86ISA::addr, bestOffset, gem5::Packet::cmd, gem5::Packet::getAddr(), insertIntoRR(), gem5::MemCmd::isHWPrefetch(), issuePrefetchRequests, gem5::CacheAccessProbeArg::pkt, Right, and tag().
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Reset all the scores from the offset list.
Definition at line 194 of file bop.cc.
References offsetsList.
Referenced by bestOffsetLearning().
Generate the tag for the specified address based on the tag bits and the block size.
addr | address to get the tag from |
Definition at line 202 of file bop.cc.
References gem5::X86ISA::addr, gem5::prefetch::Base::lBlkSize, and tagMask.
Referenced by bestOffsetLearning(), calculatePrefetch(), delayQueueEventWrapper(), insertIntoRR(), and notifyFill().
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Test if @X-O is hitting in the RR table to update the offset score.
Definition at line 208 of file bop.cc.
References gem5::X86ISA::addr, rrLeft, and rrRight.
Referenced by bestOffsetLearning().
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Definition at line 66 of file bop.hh.
Referenced by bestOffsetLearning().
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Current best offset to issue prefetches.
Definition at line 106 of file bop.hh.
Referenced by bestOffsetLearning(), calculatePrefetch(), and notifyFill().
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unsigned int gem5::prefetch::BOP::degree |
The prefetch degree, i.e.
the number of prefetches to generate
Definition at line 157 of file bop.hh.
Referenced by calculatePrefetch().
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Definition at line 97 of file bop.hh.
Referenced by delayQueueEventWrapper(), and insertIntoDelayQueue().
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Definition at line 101 of file bop.hh.
Referenced by delayQueueEventWrapper(), and insertIntoDelayQueue().
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Definition at line 72 of file bop.hh.
Referenced by insertIntoDelayQueue().
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Definition at line 73 of file bop.hh.
Referenced by insertIntoDelayQueue().
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Hardware prefetcher enabled.
Definition at line 104 of file bop.hh.
Referenced by bestOffsetLearning(), calculatePrefetch(), and notifyFill().
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Definition at line 80 of file bop.hh.
Referenced by bestOffsetLearning(), and resetScores().
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Current test offset index.
Definition at line 110 of file bop.hh.
Referenced by bestOffsetLearning().
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Current best offset found in the learning phase.
Definition at line 108 of file bop.hh.
Referenced by bestOffsetLearning().
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Definition at line 65 of file bop.hh.
Referenced by bestOffsetLearning().
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Definition at line 75 of file bop.hh.
Referenced by insertIntoRR(), and testRR().
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Definition at line 76 of file bop.hh.
Referenced by insertIntoRR(), and testRR().
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Learning phase parameters.
Definition at line 64 of file bop.hh.
Referenced by bestOffsetLearning().
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