gem5 v24.0.0.0
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exetrace.cc
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1/*
2 * Copyright (c) 2017, 2019, 2023 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#include "cpu/exetrace.hh"
42
43#include <iomanip>
44#include <sstream>
45
46#include "base/loader/symtab.hh"
47#include "cpu/base.hh"
48#include "cpu/static_inst.hh"
49#include "cpu/thread_context.hh"
50#include "debug/ExecAll.hh"
51#include "debug/FmtTicksOff.hh"
52#include "enums/OpClass.hh"
53
54namespace gem5
55{
56
57namespace trace {
58
59void
61{
62 std::stringstream outs;
63
64 const bool in_user_mode = thread->getIsaPtr()->inUserMode();
65 if (in_user_mode && !debug::ExecUser)
66 return;
67 if (!in_user_mode && !debug::ExecKernel)
68 return;
69
70 if (debug::ExecAsid) {
71 outs << "A" << std::dec <<
73 }
74
75 if (debug::ExecThread)
76 outs << "T" << thread->threadId() << " : ";
77
78 Addr cur_pc = pc->instAddr();
80 ccprintf(outs, "%#x", cur_pc);
81 if (debug::ExecSymbol && (!FullSystem || !in_user_mode) &&
82 (it = loader::debugSymbolTable.findNearest(cur_pc)) !=
84 Addr delta = cur_pc - it->address();
85 if (delta)
86 ccprintf(outs, " @%s+%d", it->name(), delta);
87 else
88 ccprintf(outs, " @%s", it->name());
89 }
90
91 if (inst->isMicroop()) {
92 ccprintf(outs, ".%2d", pc->microPC());
93 } else {
94 ccprintf(outs, " ");
95 }
96
97 ccprintf(outs, " : ");
98
99 //
100 // Print decoded instruction
101 //
102
103 outs << std::setw(26) << std::left;
105
106 if (ran) {
107 outs << " : ";
108
109 if (debug::ExecOpClass) {
110 outs << enums::OpClassStrings[inst->opClass()] << " : ";
111 }
112
113 if (debug::ExecResult && !predicate) {
114 outs << "Predicated False";
115 }
116
117 if (debug::ExecResult && dataStatus != DataInvalid) {
118 if (dataStatus == DataReg) {
119 if (vectorLengthInBytes > 0 && inst->isVector()) {
120 outs << " D=" << data.asReg.asString(vectorLengthInBytes);
121 } else {
122 ccprintf(outs, " D=%s", data.asReg.asString());
123 }
124 } else {
125 ccprintf(outs, " D=%#018x", data.asInt);
126 }
127 }
128
129 if (debug::ExecEffAddr && getMemValid())
130 outs << " A=0x" << std::hex << addr;
131
132 if (debug::ExecFetchSeq && fetch_seq_valid)
133 outs << " FetchSeq=" << std::dec << fetch_seq;
134
135 if (debug::ExecCPSeq && cp_seq_valid)
136 outs << " CPSeq=" << std::dec << cp_seq;
137
138 if (debug::ExecFlags) {
139 outs << " flags=(";
140 inst->printFlags(outs, "|");
141 outs << ")";
142 }
143 }
144
145 //
146 // End of line...
147 //
148 outs << std::endl;
149
151 when, thread->getCpuPtr()->name(), "ExecEnable", "%s",
152 outs.str().c_str());
153}
154
155void
157{
158 /*
159 * The behavior this check tries to achieve is that if ExecMacro is on,
160 * the macroop will be printed. If it's on and microops are also on, it's
161 * printed before the microops start printing to give context. If the
162 * microops aren't printed, then it's printed only when the final microop
163 * finishes. Macroops then behave like regular instructions and don't
164 * complete/print when they fault.
165 */
166 if (debug::ExecMacro && staticInst->isMicroop() &&
167 ((debug::ExecMicro &&
169 (!debug::ExecMicro &&
172 }
173 if (debug::ExecMicro || !staticInst->isMicroop()) {
174 traceInst(staticInst, true);
175 }
176}
177
178} // namespace trace
179} // namespace gem5
virtual bool inUserMode() const =0
virtual uint64_t getExecutingAsid() const
Definition isa.hh:87
std::string asString() const
Definition inst_res.hh:170
virtual std::string name() const
Definition named.hh:47
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
bool isFirstMicroop() const
bool isVector() const
bool isLastMicroop() const
bool isMicroop() const
virtual BaseISA * getIsaPtr() const =0
virtual BaseCPU * getCpuPtr()=0
virtual int threadId() const =0
SymbolVector::const_iterator const_iterator
Definition symtab.hh:272
const ExeTracer & tracer
Definition exetrace.hh:77
void traceInst(const StaticInstPtr &inst, bool ran)
Definition exetrace.cc:60
Addr addr
The address that was accessed.
Definition insttracer.hh:86
StaticInstPtr staticInst
Definition insttracer.hh:71
StaticInstPtr macroStaticInst
Definition insttracer.hh:73
ThreadContext * thread
Definition insttracer.hh:68
std::unique_ptr< PCStateBase > pc
Definition insttracer.hh:72
bool predicate
is the predicate for execution this inst true or false (not execed)?
union gem5::trace::InstRecord::Data data
std::string disassemble(StaticInstPtr inst, const PCStateBase &pc, const loader::SymbolTable *symtab=nullptr) const
void dprintf_flag(Tick when, const std::string &name, const std::string &flag, const char *fmt, const Args &...args)
Log a single message with a flag prefix.
Definition trace.hh:93
bool cp_seq_valid
Are the commit sequence number fields valid?
enum gem5::trace::InstRecord::DataStatus dataStatus
bool fetch_seq_valid
Are the fetch sequence number fields valid?
SymbolTable debugSymbolTable
Global unified debugging symbol table (for target).
Definition symtab.cc:55
Logger * getDebugLogger()
Get the current global debug logger.
Definition trace.cc:68
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition root.cc:220
void ccprintf(cp::Print &print)
Definition cprintf.hh:130

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