gem5  v21.1.0.2
exetrace.cc
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40 
41 #include "cpu/exetrace.hh"
42 
43 #include <iomanip>
44 #include <sstream>
45 
46 #include "base/loader/symtab.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/base.hh"
49 #include "cpu/static_inst.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/ExecAll.hh"
52 #include "debug/FmtTicksOff.hh"
53 #include "enums/OpClass.hh"
54 
55 namespace gem5
56 {
57 
58 namespace Trace {
59 
60 void
62 {
63  std::stringstream outs;
64 
65  const bool in_user_mode = thread->getIsaPtr()->inUserMode();
66  if (in_user_mode && !debug::ExecUser)
67  return;
68  if (!in_user_mode && !debug::ExecKernel)
69  return;
70 
71  if (debug::ExecAsid) {
72  outs << "A" << std::dec <<
73  thread->getIsaPtr()->getExecutingAsid() << " ";
74  }
75 
76  if (debug::ExecThread)
77  outs << "T" << thread->threadId() << " : ";
78 
79  Addr cur_pc = pc.instAddr();
81  ccprintf(outs, "%#x", cur_pc);
82  if (debug::ExecSymbol && (!FullSystem || !in_user_mode) &&
83  (it = loader::debugSymbolTable.findNearest(cur_pc)) !=
85  Addr delta = cur_pc - it->address;
86  if (delta)
87  ccprintf(outs, " @%s+%d", it->name, delta);
88  else
89  ccprintf(outs, " @%s", it->name);
90  }
91 
92  if (inst->isMicroop()) {
93  ccprintf(outs, ".%2d", pc.microPC());
94  } else {
95  ccprintf(outs, " ");
96  }
97 
98  ccprintf(outs, " : ");
99 
100  //
101  // Print decoded instruction
102  //
103 
104  outs << std::setw(26) << std::left;
105  outs << inst->disassemble(cur_pc, &loader::debugSymbolTable);
106 
107  if (ran) {
108  outs << " : ";
109 
110  if (debug::ExecOpClass) {
111  outs << enums::OpClassStrings[inst->opClass()] << " : ";
112  }
113 
114  if (debug::ExecResult && !predicate) {
115  outs << "Predicated False";
116  }
117 
118  if (debug::ExecResult && data_status != DataInvalid) {
119  switch (data_status) {
120  case DataVec:
121  ccprintf(outs, " D=%s", *data.as_vec);
122  break;
123  case DataVecPred:
124  ccprintf(outs, " D=%s", *data.as_pred);
125  break;
126  default:
127  ccprintf(outs, " D=%#018x", data.as_int);
128  break;
129  }
130  }
131 
132  if (debug::ExecEffAddr && getMemValid())
133  outs << " A=0x" << std::hex << addr;
134 
135  if (debug::ExecFetchSeq && fetch_seq_valid)
136  outs << " FetchSeq=" << std::dec << fetch_seq;
137 
138  if (debug::ExecCPSeq && cp_seq_valid)
139  outs << " CPSeq=" << std::dec << cp_seq;
140 
141  if (debug::ExecFlags) {
142  outs << " flags=(";
143  inst->printFlags(outs, "|");
144  outs << ")";
145  }
146  }
147 
148  //
149  // End of line...
150  //
151  outs << std::endl;
152 
154  when, thread->getCpuPtr()->name(), "ExecEnable", "%s",
155  outs.str().c_str());
156 }
157 
158 void
160 {
161  /*
162  * The behavior this check tries to achieve is that if ExecMacro is on,
163  * the macroop will be printed. If it's on and microops are also on, it's
164  * printed before the microops start printing to give context. If the
165  * microops aren't printed, then it's printed only when the final microop
166  * finishes. Macroops then behave like regular instructions and don't
167  * complete/print when they fault.
168  */
169  if (debug::ExecMacro && staticInst->isMicroop() &&
170  ((debug::ExecMicro &&
171  macroStaticInst && staticInst->isFirstMicroop()) ||
172  (!debug::ExecMicro &&
173  macroStaticInst && staticInst->isLastMicroop()))) {
174  traceInst(macroStaticInst, false);
175  }
176  if (debug::ExecMicro || !staticInst->isMicroop()) {
177  traceInst(staticInst, true);
178  }
179 }
180 
181 } // namespace Trace
182 } // namespace gem5
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:208
gem5::Trace::Logger::dprintf_flag
void dprintf_flag(Tick when, const std::string &name, const std::string &flag, const char *fmt, const Args &...args)
Log a single message with a flag prefix.
Definition: trace.hh:75
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Trace::getDebugLogger
Logger * getDebugLogger()
Get the current global debug logger.
Definition: trace.cc:69
exetrace.hh
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::loader::SymbolTable::const_iterator
SymbolVector::const_iterator const_iterator
Definition: symtab.hh:170
gem5::RefCountingPtr< StaticInst >
gem5::StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:232
gem5::Trace::ExeTracerRecord::dump
void dump()
Definition: exetrace.cc:159
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:75
base.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
symtab.hh
gem5::loader::debugSymbolTable
SymbolTable debugSymbolTable
Global unified debugging symbol table (for target).
Definition: symtab.cc:44
gem5::Trace::ExeTracerRecord::traceInst
void traceInst(const StaticInstPtr &inst, bool ran)
Definition: exetrace.cc:61
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::StaticInst::printFlags
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
Definition: static_inst.cc:86
thread_context.hh
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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