gem5  v22.0.0.2
gic.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2017, 2021-2022 Arm Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __ARCH_ARM_KVM_GIC_HH__
39 #define __ARCH_ARM_KVM_GIC_HH__
40 
41 #include "arch/arm/system.hh"
42 #include "cpu/kvm/device.hh"
43 #include "cpu/kvm/vm.hh"
44 #include "dev/arm/gic_v2.hh"
45 #include "dev/arm/gic_v3.hh"
46 #include "dev/platform.hh"
47 
48 #include "params/MuxingKvmGicV2.hh"
49 #include "params/MuxingKvmGicV3.hh"
50 
51 namespace gem5
52 {
53 
62 {
63  public:
75  KvmKernelGic(KvmVM &vm, uint32_t dev, unsigned it_lines);
76  virtual ~KvmKernelGic();
77 
78  KvmKernelGic(const KvmKernelGic &other) = delete;
79  KvmKernelGic(const KvmKernelGic &&other) = delete;
80  KvmKernelGic &operator=(const KvmKernelGic &&rhs) = delete;
81  KvmKernelGic &operator=(const KvmKernelGic &rhs) = delete;
82 
83  virtual void init() {}
84 
85  public:
96  void setSPI(unsigned spi);
102  void clearSPI(unsigned spi);
103 
110  void setPPI(unsigned vcpu, unsigned ppi);
111 
118  void clearPPI(unsigned vcpu, unsigned ppi);
119 
120  /* @} */
121 
122  protected:
131  void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high);
132 
135 
138 };
139 
141 {
142  public:
153  const MuxingKvmGicV2Params &params);
154 
155  public: // GicV2Registers
156  uint32_t readDistributor(ContextID ctx, Addr daddr) override;
157  uint32_t readCpu(ContextID ctx, Addr daddr) override;
158 
159  void writeDistributor(ContextID ctx, Addr daddr,
160  uint32_t data) override;
161  void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
162 
163  protected:
171  uint32_t getGicReg(unsigned group, unsigned vcpu, unsigned offset);
172 
181  void setGicReg(unsigned group, unsigned vcpu, unsigned offset,
182  unsigned value);
183 
184  private:
189 };
190 
192 {
193  public:
204  const MuxingKvmGicV3Params &params);
205 
206  void init() override;
207 
208  public: // Gicv3Registers
209  uint32_t readDistributor(Addr daddr) override;
210  uint32_t readRedistributor(const ArmISA::Affinity &aff,
211  Addr daddr) override;
212  RegVal readCpu(const ArmISA::Affinity &aff,
213  ArmISA::MiscRegIndex misc_reg) override;
214 
215  void writeDistributor(Addr daddr, uint32_t data) override;
216  void writeRedistributor(const ArmISA::Affinity &aff,
217  Addr daddr, uint32_t data) override;
218  void writeCpu(const ArmISA::Affinity &aff,
219  ArmISA::MiscRegIndex misc_reg, RegVal data) override;
220 
221  protected:
229  template <typename Ret>
230  Ret getGicReg(unsigned group, unsigned mpidr, unsigned offset);
231 
240  template <typename Arg>
241  void setGicReg(unsigned group, unsigned mpidr, unsigned offset,
242  Arg value);
243 
244  private:
249 };
250 
252 {
253  using SimGic = GicV2;
255  using Params = MuxingKvmGicV2Params;
256 };
257 
259 {
260  using SimGic = Gicv3;
262  using Params = MuxingKvmGicV3Params;
263 };
264 
265 template <class Types>
266 class MuxingKvmGic : public Types::SimGic
267 {
268  using SimGic = typename Types::SimGic;
269  using KvmGic = typename Types::KvmGic;
270  using Params = typename Types::Params;
271 
272  public: // SimObject / Serializable / Drainable
273  MuxingKvmGic(const Params &p);
274 
275  void startup() override;
276  DrainState drain() override;
277  void drainResume() override;
278 
279  public: // PioDevice
280  Tick read(PacketPtr pkt) override;
281  Tick write(PacketPtr pkt) override;
282 
283  public: // GicV2
284  void sendInt(uint32_t num) override;
285  void clearInt(uint32_t num) override;
286 
287  void sendPPInt(uint32_t num, uint32_t cpu) override;
288  void clearPPInt(uint32_t num, uint32_t cpu) override;
289 
290  protected: // BaseGic
291  bool blockIntUpdate() const override;
292 
293  protected:
296 
299 
300  private:
301  bool usingKvm;
302 
304  void fromGicToKvm();
305  void fromKvmToGic();
306 };
307 
308 } // namespace gem5
309 
310 #endif // __ARCH_ARM_KVM_GIC_HH__
gem5::KvmKernelGic::KvmKernelGic
KvmKernelGic(KvmVM &vm, uint32_t dev, unsigned it_lines)
Instantiate a KVM in-kernel GIC model.
Definition: gic.cc:51
gem5::MuxingKvmGic::KvmGic
typename Types::KvmGic KvmGic
Definition: gic.hh:269
gem5::KvmKernelGic::init
virtual void init()
Definition: gic.hh:83
gem5::KvmKernelGicV3::readRedistributor
uint32_t readRedistributor(const ArmISA::Affinity &aff, Addr daddr) override
Definition: gic.cc:243
gem5::GicV2Types::Params
MuxingKvmGicV2Params Params
Definition: gic.hh:255
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::MuxingKvmGic::SimGic
typename Types::SimGic SimGic
Definition: gic.hh:268
gem5::Gicv3Registers
Definition: gic_v3.hh:57
gem5::MuxingKvmGic::fromKvmToGic
void fromKvmToGic()
Definition: gic.cc:419
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::KvmKernelGic::setIntState
void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high)
Update the kernel's VGIC interrupt state.
Definition: gic.cc:91
gem5::MuxingKvmGic::clearPPInt
void clearPPInt(uint32_t num, uint32_t cpu) override
Definition: gic.cc:389
gem5::KvmKernelGic::vm
KvmVM & vm
KVM VM in the parent system.
Definition: gic.hh:134
gem5::KvmKernelGic
KVM in-kernel GIC abstraction.
Definition: gic.hh:61
gem5::KvmKernelGic::setPPI
void setPPI(unsigned vcpu, unsigned ppi)
Raise a private peripheral interrupt.
Definition: gic.cc:79
gem5::MuxingKvmGic::blockIntUpdate
bool blockIntUpdate() const override
Definition: gic.cc:400
gem5::GicV2Types
Definition: gic.hh:251
gem5::KvmKernelGic::kdev
KvmDevice kdev
Kernel interface to the GIC.
Definition: gic.hh:137
gem5::MuxingKvmGic
Definition: gic.hh:266
gem5::MuxingKvmGic::read
Tick read(PacketPtr pkt) override
Definition: gic.cc:337
system.hh
gem5::MuxingKvmGic::clearInt
void clearInt(uint32_t num) override
Definition: gic.cc:368
gem5::KvmKernelGicV3::readDistributor
uint32_t readDistributor(Addr daddr) override
Definition: gic.cc:237
gem5::KvmKernelGicV2::getGicReg
uint32_t getGicReg(unsigned group, unsigned vcpu, unsigned offset)
Get value of GIC register "from" a cpu.
Definition: gic.cc:128
gem5::KvmKernelGicV3::distRange
const AddrRange distRange
Address range for the distributor.
Definition: gic.hh:248
gem5::KvmKernelGicV3::init
void init() override
Definition: gic.cc:200
gem5::KvmVM
KVM VM container.
Definition: vm.hh:301
gem5::MuxingKvmGic::write
Tick write(PacketPtr pkt) override
Definition: gic.cc:347
gem5::GicV2Registers
Definition: gic_v2.hh:62
gem5::KvmKernelGic::clearPPI
void clearPPI(unsigned vcpu, unsigned ppi)
Clear a private peripheral interrupt.
Definition: gic.cc:85
gem5::ArmISA::irq
Bitfield< 1 > irq
Definition: misc_types.hh:331
gem5::KvmKernelGicV3::redistRange
const AddrRange redistRange
Address range for the redistributor.
Definition: gic.hh:246
gem5::KvmKernelGicV3::writeCpu
void writeCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg, RegVal data) override
Definition: gic.cc:270
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::KvmKernelGic::clearSPI
void clearSPI(unsigned spi)
Clear a shared peripheral interrupt.
Definition: gic.cc:73
gem5::high
high
Definition: intmath.hh:176
gem5::System
Definition: system.hh:75
gem5::KvmKernelGicV2::KvmKernelGicV2
KvmKernelGicV2(KvmVM &vm, const MuxingKvmGicV2Params &params)
Instantiate a KVM in-kernel GICv2 model.
Definition: gic.cc:115
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::KvmKernelGicV3::writeRedistributor
void writeRedistributor(const ArmISA::Affinity &aff, Addr daddr, uint32_t data) override
Definition: gic.cc:263
gem5::MuxingKvmGic::fromGicToKvm
void fromGicToKvm()
Multiplexing implementation.
Definition: gic.cc:411
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::GicV2
Definition: gic_v2.hh:91
gem5::KvmKernelGicV3
Definition: gic.hh:191
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::type
type
Definition: misc.hh:727
device.hh
gem5::KvmKernelGicV2::writeDistributor
void writeDistributor(ContextID ctx, Addr daddr, uint32_t data) override
Definition: gic.cc:170
gem5::KvmKernelGic::setSPI
void setSPI(unsigned spi)
Raise a shared peripheral interrupt.
Definition: gic.cc:67
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::KvmKernelGicV3::writeDistributor
void writeDistributor(Addr daddr, uint32_t data) override
Definition: gic.cc:257
gem5::MuxingKvmGic::MuxingKvmGic
MuxingKvmGic(const Params &p)
Definition: gic.cc:279
gem5::KvmKernelGicV2::setGicReg
void setGicReg(unsigned group, unsigned vcpu, unsigned offset, unsigned value)
Set value of GIC register "from" a cpu.
Definition: gic.cc:142
gem5::MuxingKvmGic::usingKvm
bool usingKvm
Definition: gic.hh:301
gem5::KvmKernelGicV3::getGicReg
Ret getGicReg(unsigned group, unsigned mpidr, unsigned offset)
Get value of GIC register "from" a cpu.
Definition: gic.cc:208
gem5::KvmKernelGicV2::readDistributor
uint32_t readDistributor(ContextID ctx, Addr daddr) override
Definition: gic.cc:156
platform.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::KvmKernelGicV2::cpuRange
const AddrRange cpuRange
Address range for the CPU interfaces.
Definition: gic.hh:186
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
vm.hh
gem5::KvmKernelGic::~KvmKernelGic
virtual ~KvmKernelGic()
Definition: gic.cc:62
gem5::KvmKernelGic::operator=
KvmKernelGic & operator=(const KvmKernelGic &&rhs)=delete
gem5::KvmKernelGicV2::readCpu
uint32_t readCpu(ContextID ctx, Addr daddr) override
Definition: gic.cc:163
gem5::Gicv3
Definition: gic_v3.hh:95
gem5::KvmDevice
KVM device wrapper.
Definition: device.hh:60
gem5::MuxingKvmGic::kernelGic
KvmKernelGic * kernelGic
Kernel GIC device.
Definition: gic.hh:298
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::MuxingKvmGic::Params
typename Types::Params Params
Definition: gic.hh:270
gem5::MuxingKvmGic::sendInt
void sendInt(uint32_t num) override
Definition: gic.cc:357
gem5::MuxingKvmGic::drain
DrainState drain() override
Definition: gic.cc:310
gem5::KvmKernelGicV3::setGicReg
void setGicReg(unsigned group, unsigned mpidr, unsigned offset, Arg value)
Set value of GIC register "from" a cpu.
Definition: gic.cc:223
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
gem5::GicV3Types::Params
MuxingKvmGicV3Params Params
Definition: gic.hh:262
gic_v2.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::KvmKernelGicV2::writeCpu
void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override
Definition: gic.cc:177
gem5::MuxingKvmGic::drainResume
void drainResume() override
Definition: gic.cc:319
gem5::KvmKernelGicV3::readCpu
RegVal readCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg) override
Definition: gic.cc:249
gem5::KvmKernelGicV3::KvmKernelGicV3
KvmKernelGicV3(KvmVM &vm, const MuxingKvmGicV3Params &params)
Instantiate a KVM in-kernel GICv3 model.
Definition: gic.cc:187
gic_v3.hh
gem5::MuxingKvmGic::sendPPInt
void sendPPInt(uint32_t num, uint32_t cpu) override
Definition: gic.cc:379
gem5::MuxingKvmGic::startup
void startup() override
Definition: gic.cc:293
gem5::MuxingKvmGic::system
System & system
System this interrupt controller belongs to.
Definition: gic.hh:295
gem5::KvmKernelGicV2::distRange
const AddrRange distRange
Address range for the distributor.
Definition: gic.hh:188
gem5::KvmKernelGicV2
Definition: gic.hh:140
gem5::GicV3Types
Definition: gic.hh:258

Generated on Thu Jul 28 2022 13:32:22 for gem5 by doxygen 1.8.17